Файловый менеджер - Редактировать - /var/www/html/xtfpga.zip
Ðазад
PK ! 7�� � include/platform/serial.hnu �[��� /* * arch/xtensa/platform/xtavnet/include/platform/serial.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001, 2006 Tensilica Inc. */ #ifndef __ASM_XTENSA_XTAVNET_SERIAL_H #define __ASM_XTENSA_XTAVNET_SERIAL_H #include <platform/hardware.h> #define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16) #endif /* __ASM_XTENSA_XTAVNET_SERIAL_H */ PK ! �]�Ý � include/platform/hardware.hnu �[��� /* * arch/xtensa/platform/xtavnet/include/platform/hardware.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2006 Tensilica Inc. */ /* * This file contains the hardware configuration of the XTAVNET boards. */ #include <asm/types.h> #ifndef __XTENSA_XTAVNET_HARDWARE_H #define __XTENSA_XTAVNET_HARDWARE_H /* Default assignment of LX60 devices to external interrupts. */ #ifdef CONFIG_XTENSA_MX #define DUART16552_INTNUM XCHAL_EXTINT3_NUM #define OETH_IRQ XCHAL_EXTINT4_NUM #define C67X00_IRQ XCHAL_EXTINT8_NUM #else #define DUART16552_INTNUM XCHAL_EXTINT0_NUM #define OETH_IRQ XCHAL_EXTINT1_NUM #define C67X00_IRQ XCHAL_EXTINT5_NUM #endif /* * Device addresses and parameters. */ /* UART */ #define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020) /* Misc. */ #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000) /* Clock frequency in Hz (read-only): */ #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04) /* Setting of 8 DIP switches: */ #define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C) /* Software reset (write 0xdead): */ #define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10) /* OpenCores Ethernet controller: */ /* regs + RX/TX descriptors */ #define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000) #define OETH_REGS_SIZE 0x1000 #define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000) /* 5*rx buffs + 5*tx buffs */ #define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600) #define C67X00_PADDR (XCHAL_KIO_PADDR + 0x0D0D0000) #define C67X00_SIZE 0x10 #endif /* __XTENSA_XTAVNET_HARDWARE_H */ PK ! �ߩ. include/platform/lcd.hnu �[��� /* * arch/xtensa/platform/xtavnet/include/platform/lcd.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001, 2006 Tensilica Inc. */ #ifndef __XTENSA_XTAVNET_LCD_H #define __XTENSA_XTAVNET_LCD_H #ifdef CONFIG_XTFPGA_LCD /* Display string STR at position POS on the LCD. */ void lcd_disp_at_pos(char *str, unsigned char pos); /* Shift the contents of the LCD display left or right. */ void lcd_shiftleft(void); void lcd_shiftright(void); #else static inline void lcd_disp_at_pos(char *str, unsigned char pos) { } static inline void lcd_shiftleft(void) { } static inline void lcd_shiftright(void) { } #endif #endif PK ! �+�ד � Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only # Makefile for the Tensilica xtavnet Emulation Board # # Note! Dependencies are done automagically by 'make dep', which also # removes any old dependencies. DON'T put your own dependencies here # unless it's something special (ie not a .c file). # # Note 2! The CFLAGS definitions are in the main makefile... obj-y += setup.o obj-$(CONFIG_XTFPGA_LCD) += lcd.o PK ! 7�� � include/platform/serial.hnu �[��� PK ! �]�Ý � 8 include/platform/hardware.hnu �[��� PK ! �ߩ. include/platform/lcd.hnu �[��� PK ! �+�ד � h Makefilenu �[��� PK R 3
| ver. 1.1 | |
.
| PHP 8.4.18 | Ð“ÐµÐ½ÐµÑ€Ð°Ñ†Ð¸Ñ Ñтраницы: 0 |
proxy
|
phpinfo
|
ÐаÑтройка