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PK ! �Pya a cchips/hd6446x/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_HD64461) += hd64461.o ccflags-y := -Werror PK ! �8�� cchips/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 menu "Companion Chips" config HD6446X_SERIES bool choice prompt "HD6446x options" depends on HD6446X_SERIES default HD64461 config HD64461 bool "Hitachi HD64461 companion chip support" help The Hitachi HD64461 provides an interface for the SH7709 CPU, supporting a LCD controller, CRT color controller, IrDA up to 4 Mbps, and a PCMCIA controller supporting 2 slots. More information is available at <http://semiconductor.hitachi.com/windowsce/superh/sld013.htm>. Say Y if you want support for the HD64461. Otherwise, say N. endchoice # These will also be split into the Kconfig's below config HD64461_IRQ int "HD64461 IRQ" depends on HD64461 default "36" help The default setting of the HD64461 IRQ is 36. Do not change this unless you know what you are doing. config HD64461_ENABLER bool "HD64461 PCMCIA enabler" depends on HD64461 help Say Y here if you want to enable PCMCIA support via the HD64461 companion chip. Otherwise, say N. endmenu PK ! Ʋ9j� � include/mach-sh03/mach/io.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * include/asm-sh/sh03/io.h * * Copyright 2004 Interface Co.,Ltd. Saito.K * * IO functions for an Interface CTP/PCI-SH03 */ #ifndef _ASM_SH_IO_SH03_H #define _ASM_SH_IO_SH03_H #include <linux/time.h> #define IRL0_IRQ 2 #define IRL0_PRIORITY 13 #define IRL1_IRQ 5 #define IRL1_PRIORITY 10 #define IRL2_IRQ 8 #define IRL2_PRIORITY 7 #define IRL3_IRQ 11 #define IRL3_PRIORITY 4 void heartbeat_sh03(void); #endif /* _ASM_SH_IO_SH03_H */ PK ! "�hM� � include/mach-sh03/mach/sh03.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SH03_H #define __ASM_SH_SH03_H /* * linux/include/asm-sh/sh03/sh03.h * * Copyright (C) 2004 Interface Co., Ltd. Saito.K * * Interface CTP/PCI-SH03 support */ #define PA_PCI_IO (0xbe240000) /* PCI I/O space */ #define PA_PCI_MEM (0xbd000000) /* PCI MEM space */ #define PCIPAR (0xa4000cf8) /* PCI Config address */ #define PCIPDR (0xa4000cfc) /* PCI Config data */ #endif /* __ASM_SH_SH03_H */ PK ! K�%7 7 ! include/mach-dreamcast/mach/pci.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/dreamcast/pci.h * * Copyright (C) 2001, 2002 M. R. Brown * Copyright (C) 2002, 2003 Paul Mundt */ #ifndef __ASM_SH_DREAMCAST_PCI_H #define __ASM_SH_DREAMCAST_PCI_H #include <mach-dreamcast/mach/sysasic.h> #define GAPSPCI_REGS 0x01001400 #define GAPSPCI_DMA_BASE 0x01840000 #define GAPSPCI_DMA_SIZE 32768 #define GAPSPCI_BBA_CONFIG 0x01001600 #define GAPSPCI_BBA_CONFIG_SIZE 0x2000 #define GAPSPCI_IRQ HW_EVENT_EXTERNAL extern struct pci_ops gapspci_pci_ops; #endif /* __ASM_SH_DREAMCAST_PCI_H */ PK ! y�<�{ { # include/mach-dreamcast/mach/maple.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_MAPLE_H #define __ASM_MAPLE_H #define MAPLE_PORTS 4 #define MAPLE_PNP_INTERVAL HZ #define MAPLE_MAXPACKETS 8 #define MAPLE_DMA_ORDER 14 #define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER) #define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \ MAPLE_DMA_ORDER - PAGE_SHIFT : 0) /* Maple Bus registers */ #define MAPLE_BASE 0xa05f6c00 #define MAPLE_DMAADDR (MAPLE_BASE+0x04) #define MAPLE_TRIGTYPE (MAPLE_BASE+0x10) #define MAPLE_ENABLE (MAPLE_BASE+0x14) #define MAPLE_STATE (MAPLE_BASE+0x18) #define MAPLE_SPEED (MAPLE_BASE+0x80) #define MAPLE_RESET (MAPLE_BASE+0x8c) #define MAPLE_MAGIC 0x6155404f #define MAPLE_2MBPS 0 #define MAPLE_TIMEOUT(n) ((n)<<15) /* Function codes */ #define MAPLE_FUNC_CONTROLLER 0x001 #define MAPLE_FUNC_MEMCARD 0x002 #define MAPLE_FUNC_LCD 0x004 #define MAPLE_FUNC_CLOCK 0x008 #define MAPLE_FUNC_MICROPHONE 0x010 #define MAPLE_FUNC_ARGUN 0x020 #define MAPLE_FUNC_KEYBOARD 0x040 #define MAPLE_FUNC_LIGHTGUN 0x080 #define MAPLE_FUNC_PURUPURU 0x100 #define MAPLE_FUNC_MOUSE 0x200 #endif /* __ASM_MAPLE_H */ PK ! ��� % include/mach-dreamcast/mach/sysasic.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/dreamcast/sysasic.h * * Definitions for the Dreamcast System ASIC and related peripherals. * * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org> * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org> * * This file is part of the LinuxDC project (www.linuxdc.org) */ #ifndef __ASM_SH_DREAMCAST_SYSASIC_H #define __ASM_SH_DREAMCAST_SYSASIC_H #include <asm/irq.h> /* Hardware events - Each of these events correspond to a bit within the Event Mask Registers/ Event Status Registers. Because of the virtual IRQ numbering scheme, a base offset must be used when calculating the virtual IRQ that each event takes. */ #define HW_EVENT_IRQ_BASE 48 /* IRQ 13 */ #define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */ #define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */ #define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */ #define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */ #define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */ /* IRQ 11 */ #define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */ #define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */ #define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */ #define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95) /* arch/sh/boards/mach-dreamcast/irq.c */ extern int systemasic_irq_demux(int); extern void systemasic_irq_init(void); #endif /* __ASM_SH_DREAMCAST_SYSASIC_H */ PK ! �y�� � ! include/mach-dreamcast/mach/dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/dreamcast/dma.h * * Copyright (C) 2003 Paul Mundt */ #ifndef __ASM_SH_DREAMCAST_DMA_H #define __ASM_SH_DREAMCAST_DMA_H /* Number of DMA channels */ #define G2_NR_DMA_CHANNELS 4 /* Channels for cascading */ #define PVR2_CASCADE_CHAN 2 #define G2_CASCADE_CHAN 3 /* PVR2 DMA Registers */ #define PVR2_DMA_BASE 0xa05f6800 #define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0) #define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4) #define PVR2_DMA_MODE (PVR2_DMA_BASE + 8) #define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132) #define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136) /* G2 DMA Register */ #define G2_DMA_BASE 0xa05f7800 #endif /* __ASM_SH_DREAMCAST_DMA_H */ PK ! !_�� � include/cpu-sh2/cpu/cache.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh2/cache.h * * Copyright (C) 2003 Paul Mundt */ #ifndef __ASM_CPU_SH2_CACHE_H #define __ASM_CPU_SH2_CACHE_H #define L1_CACHE_SHIFT 4 #define SH_CACHE_VALID 1 #define SH_CACHE_UPDATED 2 #define SH_CACHE_COMBINED 4 #define SH_CACHE_ASSOC 8 #if defined(CONFIG_CPU_SUBTYPE_SH7619) #define SH_CCR 0xffffffec #define CCR_CACHE_CE 0x01 /* Cache enable */ #define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */ /* 0x00000000-0x7fffffff: Write-through */ /* 0x80000000-0x9fffffff: Write-back */ /* 0xc0000000-0xdfffffff: Write-through */ #define CCR_CACHE_CB 0x04 /* CCR[bit1=0,bit2=0] */ /* 0x00000000-0x7fffffff: Write-back */ /* 0x80000000-0x9fffffff: Write-through */ /* 0xc0000000-0xdfffffff: Write-back */ #define CCR_CACHE_CF 0x08 /* Cache invalidate */ #define CACHE_OC_ADDRESS_ARRAY 0xf0000000 #define CACHE_OC_DATA_ARRAY 0xf1000000 #define CCR_CACHE_ENABLE CCR_CACHE_CE #define CCR_CACHE_INVALIDATE CCR_CACHE_CF #define CACHE_PHYSADDR_MASK 0x1ffffc00 #endif #endif /* __ASM_CPU_SH2_CACHE_H */ PK ! j� include/cpu-sh2/cpu/freq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh2/freq.h * * Copyright (C) 2006 Yoshinori Sato */ #ifndef __ASM_CPU_SH2_FREQ_H #define __ASM_CPU_SH2_FREQ_H #if defined(CONFIG_CPU_SUBTYPE_SH7619) #define FREQCR 0xf815ff80 #endif #endif /* __ASM_CPU_SH2_FREQ_H */ PK ! ���_ _ include/cpu-sh2/cpu/watchdog.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh2/watchdog.h * * Copyright (C) 2002, 2003 Paul Mundt */ #ifndef __ASM_CPU_SH2_WATCHDOG_H #define __ASM_CPU_SH2_WATCHDOG_H /* * More SH-2 brilliance .. its not good enough that we can't read * and write the same sizes to WTCNT, now we have to read and write * with different sizes at different addresses for WTCNT _and_ RSTCSR. * * At least on the bright side no one has managed to screw over WTCSR * in this fashion .. yet. */ /* Register definitions */ #define WTCNT 0xfffffe80 #define WTCSR 0xfffffe80 #define RSTCSR 0xfffffe82 #define WTCNT_R (WTCNT + 1) #define RSTCSR_R (RSTCSR + 1) /* Bit definitions */ #define WTCSR_IOVF 0x80 #define WTCSR_WT 0x40 #define WTCSR_TME 0x20 #define WTCSR_RSTS 0x00 #define RSTCSR_RSTS 0x20 /** * sh_wdt_read_rstcsr - Read from Reset Control/Status Register * * Reads back the RSTCSR value. */ static inline __u8 sh_wdt_read_rstcsr(void) { /* * Same read/write brain-damage as for WTCNT here.. */ return __raw_readb(RSTCSR_R); } /** * sh_wdt_write_csr - Write to Reset Control/Status Register * * @val: Value to write * * Writes the given value @val to the lower byte of the control/status * register. The upper byte is set manually on each write. */ static inline void sh_wdt_write_rstcsr(__u8 val) { /* * Note: Due to the brain-damaged nature of this register, * we can't presently touch the WOVF bit, since the upper byte * has to be swapped for this. So just leave it alone.. */ __raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR); } #endif /* __ASM_CPU_SH2_WATCHDOG_H */ PK ! eY�p p include/cpu-common/cpu/pfc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * SH Pin Function Control Initialization * * Copyright (C) 2012 Renesas Solutions Corp. */ #ifndef __ARCH_SH_CPU_PFC_H__ #define __ARCH_SH_CPU_PFC_H__ #include <linux/types.h> struct resource; int sh_pfc_register(const char *name, struct resource *resource, u32 num_resources); #endif /* __ARCH_SH_CPU_PFC_H__ */ PK ! �;J� � $ include/cpu-common/cpu/mmu_context.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh2/mmu_context.h * * Copyright (C) 2003 Paul Mundt */ #ifndef __ASM_CPU_SH2_MMU_CONTEXT_H #define __ASM_CPU_SH2_MMU_CONTEXT_H /* No MMU */ #endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */ PK ! t�:� � # include/cpu-common/cpu/sigcontext.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CPU_SH2_SIGCONTEXT_H #define __ASM_CPU_SH2_SIGCONTEXT_H struct sigcontext { unsigned long oldmask; /* CPU registers */ unsigned long sc_regs[16]; unsigned long sc_pc; unsigned long sc_pr; unsigned long sc_sr; unsigned long sc_gbr; unsigned long sc_mach; unsigned long sc_macl; }; #endif /* __ASM_CPU_SH2_SIGCONTEXT_H */ PK ! 4�D{� � include/cpu-common/cpu/rtc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CPU_SH2_RTC_H #define __ASM_SH_CPU_SH2_RTC_H #define rtc_reg_size sizeof(u16) #define RTC_BIT_INVERTED 0 #define RTC_DEF_CAPABILITIES 0UL #endif /* __ASM_SH_CPU_SH2_RTC_H */ PK ! �m�� � include/cpu-common/cpu/timer.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CPU_SH2_TIMER_H #define __ASM_CPU_SH2_TIMER_H /* Nothing needed yet */ #endif /* __ASM_CPU_SH2_TIMER_H */ PK ! 6,�w w " include/cpu-common/cpu/addrspace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Definitions for the address spaces of the SH-2 CPUs. * * Copyright (C) 2003 Paul Mundt */ #ifndef __ASM_CPU_SH2_ADDRSPACE_H #define __ASM_CPU_SH2_ADDRSPACE_H #define P0SEG 0x00000000 #define P1SEG 0x80000000 #define P2SEG 0xa0000000 #define P3SEG 0xc0000000 #define P4SEG 0xe0000000 #endif /* __ASM_CPU_SH2_ADDRSPACE_H */ PK ! ��n�+ + % include/mach-ecovec24/mach/romimage.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifdef __ASSEMBLY__ /* EcoVec board specific boot code: * converts the "partner-jet-script.txt" script into assembly * the assembly code is the first code to be executed in the romImage */ #include <asm/romimage-macros.h> #include <mach/partner-jet-setup.txt> /* execute icbi after enabling cache */ mov.l 1f, r0 icbi @r0 /* jump to cached area */ mova 2f, r0 jmp @r0 nop .align 2 1 : .long 0xa8000000 2 : #else /* __ASSEMBLY__ */ /* Ecovec board specific information: * * Set the following to enable MMCIF boot from the MMC card in CN12: * * DS1.5 = OFF (SH BOOT pin set to L) * DS2.6 = OFF (Select MMCIF on CN12 instead of SDHI1) * DS2.7 = ON (Select MMCIF on CN12 instead of SDHI1) * */ #define HIZCRA 0xa4050158 #define PGDR 0xa405012c static inline void mmcif_update_progress(int nr) { /* disable Hi-Z for LED pins */ __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA); /* update progress on LED4, LED5, LED6 and LED7 */ __raw_writeb(1 << (nr - 1), PGDR); } #endif /* __ASSEMBLY__ */ PK ! �'��� � 0 include/mach-ecovec24/mach/partner-jet-setup.txtnu �[��� LIST "SPDX-License-Identifier: GPL-2.0" LIST "partner-jet-setup.txt" LIST "(C) Copyright 2009 Renesas Solutions Corp" LIST "Kuninori Morimoto <morimoto.kuninori@renesas.com>" LIST "--------------------------------" LIST "zImage (RAM boot)" LIST "This script can be used to boot the kernel from RAM via JTAG:" LIST "> < partner-jet-setup.txt" LIST "> RD zImage, 0xa8800000" LIST "> G=0xa8800000" LIST "--------------------------------" LIST "romImage (Flash boot)" LIST "Use the following command to burn the zImage to flash via JTAG:" LIST "> RD romImage, 0" LIST "--------------------------------" LIST "disable watchdog" EW 0xa4520004, 0xa507 LIST "MMU" ED 0xff000010, 0x00000004 LIST "setup clocks" ED 0xa4150024, 0x00004000 ED 0xa4150000, 0x8E003508 WAIT 1 LIST "BSC" ED 0xff800020, 0xa5a50000 ED 0xfec10000, 0x00001013 ED 0xfec10004, 0x11110400 ED 0xfec10024, 0x00000440 WAIT 1 LIST "setup sdram" ED 0xfd000108, 0x00000181 ED 0xfd000020, 0x015B0002 ED 0xfd000030, 0x03061502 ED 0xfd000034, 0x02020102 ED 0xfd000038, 0x01090305 ED 0xfd00003c, 0x00000002 ED 0xfd000008, 0x00000005 ED 0xfd000018, 0x00000001 WAIT 1 ED 0xfd000014, 0x00000002 ED 0xfd000060, 0x00020000 ED 0xfd000060, 0x00030000 ED 0xfd000060, 0x00010040 ED 0xfd000060, 0x00000532 ED 0xfd000014, 0x00000002 ED 0xfd000014, 0x00000004 ED 0xfd000014, 0x00000004 ED 0xfd000060, 0x00000432 ED 0xfd000060, 0x000103C0 ED 0xfd000060, 0x00010040 WAIT 1 ED 0xfd000010, 0x00000001 ED 0xfd000044, 0x00000613 ED 0xfd000048, 0x238C003A ED 0xfd000014, 0x00000002 LIST "Dummy read" DD 0x0c400000, 0x0c400000 ED 0xfd000014, 0x00000002 ED 0xfd000014, 0x00000004 ED 0xfd000108, 0x00000080 ED 0xfd000040, 0x00010000 WAIT 1 LIST "setup cache" ED 0xff00001c, 0x0000090b LIST "disable USB" EW 0xA4D80000, 0x0000 PK ! , �� � include/cpu-sh4a/cpu/serial.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __CPU_SH4A_SERIAL_H #define __CPU_SH4A_SERIAL_H /* arch/sh/kernel/cpu/sh4a/serial-sh7722.c */ extern struct plat_sci_port_ops sh7722_sci_port_ops; #endif /* __CPU_SH4A_SERIAL_H */ PK ! ���( ( include/cpu-sh4a/cpu/dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H #define __ASM_SH_CPU_SH4_DMA_SH7780_H #include <linux/sh_intc.h> #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ defined(CONFIG_CPU_SUBTYPE_SH7730) #define DMTE0_IRQ evt2irq(0x800) #define DMTE4_IRQ evt2irq(0xb80) #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) #define DMTE0_IRQ evt2irq(0x800) #define DMTE4_IRQ evt2irq(0xb80) #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) #define DMTE0_IRQ evt2irq(0x640) #define DMTE4_IRQ evt2irq(0x780) #define DMAE0_IRQ evt2irq(0x6c0) #define SH_DMAC_BASE0 0xFF608020 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ #define DMTE6_IRQ evt2irq(0x700) #define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ #define DMTE9_IRQ evt2irq(0x760) #define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ #define DMTE11_IRQ evt2irq(0xb20) #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMAC_BASE1 0xFDC08020 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ #define DMTE6_IRQ evt2irq(0x700) #define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ #define DMTE9_IRQ evt2irq(0x760) #define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ #define DMTE11_IRQ evt2irq(0xb20) #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMAC_BASE1 0xFDC08020 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) #define DMTE0_IRQ evt2irq(0x640) #define DMTE4_IRQ evt2irq(0x780) #define DMTE6_IRQ evt2irq(0x7c0) #define DMTE8_IRQ evt2irq(0xd80) #define DMTE9_IRQ evt2irq(0xda0) #define DMTE10_IRQ evt2irq(0xdc0) #define DMTE11_IRQ evt2irq(0xde0) #define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFC818020 #else /* SH7785 */ #define DMTE0_IRQ evt2irq(0x620) #define DMTE4_IRQ evt2irq(0x6a0) #define DMTE6_IRQ evt2irq(0x880) #define DMTE8_IRQ evt2irq(0x8c0) #define DMTE9_IRQ evt2irq(0x8e0) #define DMTE10_IRQ evt2irq(0x900) #define DMTE11_IRQ evt2irq(0x920) #define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */ #define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFCC08020 #endif #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ PK ! ���? ? include/mach-sdk7786/mach/fpga.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_SDK7786_FPGA_H #define __MACH_SDK7786_FPGA_H #include <linux/io.h> #include <linux/types.h> #include <linux/bitops.h> #define SRSTR 0x000 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */ #define INTASR 0x010 #define INTAMR 0x020 #define MODSWR 0x030 #define INTTESTR 0x040 #define SYSSR 0x050 #define NRGPR 0x060 #define NMISR 0x070 #define NMISR_MAN_NMI BIT(0) #define NMISR_AUX_NMI BIT(1) #define NMISR_MASK (NMISR_MAN_NMI | NMISR_AUX_NMI) #define NMIMR 0x080 #define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */ #define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */ #define NMIMR_MASK (NMIMR_MAN_NMIM | NMIMR_AUX_NMIM) #define INTBSR 0x090 #define INTBMR 0x0a0 #define USRLEDR 0x0b0 #define MAPSWR 0x0c0 #define FPGAVR 0x0d0 #define FPGADR 0x0e0 #define PCBRR 0x0f0 #define RSR 0x100 #define EXTASR 0x110 #define SPCAR 0x120 #define INTMSR 0x130 #define PCIECR 0x140 #define PCIECR_PCIEMUX1 BIT(15) #define PCIECR_PCIEMUX0 BIT(14) #define PCIECR_PRST4 BIT(12) /* slot 4 card present */ #define PCIECR_PRST3 BIT(11) /* slot 3 card present */ #define PCIECR_PRST2 BIT(10) /* slot 2 card present */ #define PCIECR_PRST1 BIT(9) /* slot 1 card present */ #define PCIECR_CLKEN BIT(4) /* oscillator enable */ #define FAER 0x150 #define USRGPIR 0x160 /* 0x170 reserved */ #define LCLASR 0x180 #define LCLASR_FRAMEN BIT(15) #define LCLASR_FPGA_SEL_SHIFT 12 #define LCLASR_NAND_SEL_SHIFT 8 #define LCLASR_NORB_SEL_SHIFT 4 #define LCLASR_NORA_SEL_SHIFT 0 #define LCLASR_AREA_MASK 0x7 #define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT) #define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT) #define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT) #define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT) #define SBCR 0x190 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ #define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */ #define PWRCR 0x1a0 #define PWRCR_SCISEL0 BIT(0) #define PWRCR_SCISEL1 BIT(1) #define PWRCR_SCIEN BIT(2) /* Serial port enable */ #define PWRCR_PDWNACK BIT(5) /* Power down acknowledge */ #define PWRCR_PDWNREQ BIT(7) /* Power down request */ #define PWRCR_INT2 BIT(11) /* INT2 connection to power manager */ #define PWRCR_BUPINIT BIT(13) /* DDR backup initialize */ #define PWRCR_BKPRST BIT(15) /* Backup power reset */ #define SPCBR 0x1b0 #define SPICR 0x1c0 #define SPIDR 0x1d0 #define I2CCR 0x1e0 #define I2CDR 0x1f0 #define FPGACR 0x200 #define IASELR1 0x210 #define IASELR2 0x220 #define IASELR3 0x230 #define IASELR4 0x240 #define IASELR5 0x250 #define IASELR6 0x260 #define IASELR7 0x270 #define IASELR8 0x280 #define IASELR9 0x290 #define IASELR10 0x2a0 #define IASELR11 0x2b0 #define IASELR12 0x2c0 #define IASELR13 0x2d0 #define IASELR14 0x2e0 #define IASELR15 0x2f0 /* 0x300 reserved */ #define IBSELR1 0x310 #define IBSELR2 0x320 #define IBSELR3 0x330 #define IBSELR4 0x340 #define IBSELR5 0x350 #define IBSELR6 0x360 #define IBSELR7 0x370 #define IBSELR8 0x380 #define IBSELR9 0x390 #define IBSELR10 0x3a0 #define IBSELR11 0x3b0 #define IBSELR12 0x3c0 #define IBSELR13 0x3d0 #define IBSELR14 0x3e0 #define IBSELR15 0x3f0 #define USRACR 0x400 #define BEEPR 0x410 #define USRLCDR 0x420 #define SMBCR 0x430 #define SMBDR 0x440 #define USBCR 0x450 #define AMSR 0x460 #define ACCR 0x470 #define SDIFCR 0x480 /* arch/sh/boards/mach-sdk7786/fpga.c */ extern void __iomem *sdk7786_fpga_base; extern void sdk7786_fpga_init(void); /* arch/sh/boards/mach-sdk7786/nmi.c */ extern void sdk7786_nmi_init(void); #define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg)) /* * A convenience wrapper from register offset to internal I2C address, * when the FPGA is in I2C slave mode. */ #define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3) static inline u16 fpga_read_reg(unsigned int reg) { return ioread16(sdk7786_fpga_base + reg); } static inline void fpga_write_reg(u16 val, unsigned int reg) { iowrite16(val, sdk7786_fpga_base + reg); } #endif /* __MACH_SDK7786_FPGA_H */ PK ! 4��� � include/mach-sdk7786/mach/irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_SDK7786_IRQ_H #define __MACH_SDK7786_IRQ_H /* arch/sh/boards/mach-sdk7786/irq.c */ extern void sdk7786_init_irq(void); #endif /* __MACH_SDK7786_IRQ_H */ PK ! �C3�& & include/cpu-sh2a/cpu/cache.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh2a/cache.h * * Copyright (C) 2004 Paul Mundt */ #ifndef __ASM_CPU_SH2A_CACHE_H #define __ASM_CPU_SH2A_CACHE_H #define L1_CACHE_SHIFT 4 #define SH_CACHE_VALID 1 #define SH_CACHE_UPDATED 2 #define SH_CACHE_COMBINED 4 #define SH_CACHE_ASSOC 8 #define SH_CCR 0xfffc1000 /* CCR1 */ #define SH_CCR2 0xfffc1004 /* * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not * listed here are reserved. */ #define CCR_CACHE_CB 0x0000 /* Hack */ #define CCR_CACHE_OCE 0x0001 #define CCR_CACHE_WT 0x0002 #define CCR_CACHE_OCI 0x0008 /* OCF */ #define CCR_CACHE_ICE 0x0100 #define CCR_CACHE_ICI 0x0800 /* ICF */ #define CACHE_IC_ADDRESS_ARRAY 0xf0000000 #define CACHE_OC_ADDRESS_ARRAY 0xf0800000 #define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE) #define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI) #define CCR_ICACHE_INVALIDATE CCR_CACHE_ICI #define CCR_OCACHE_INVALIDATE CCR_CACHE_OCI #define CACHE_PHYSADDR_MASK 0x1ffffc00 #endif /* __ASM_CPU_SH2A_CACHE_H */ PK ! `,�|� � include/cpu-sh2a/cpu/freq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh2a/freq.h * * Copyright (C) 2006 Yoshinori Sato */ #ifndef __ASM_CPU_SH2A_FREQ_H #define __ASM_CPU_SH2A_FREQ_H #define FREQCR 0xfffe0010 #endif /* __ASM_CPU_SH2A_FREQ_H */ PK ! ���.� � include/cpu-sh2a/cpu/sh7203.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7203_H__ #define __ASM_SH7203_H__ enum { /* PA */ GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4, GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0, /* PB */ GPIO_PB12, GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0, /* PC */ GPIO_PC14, GPIO_PC13, GPIO_PC12, GPIO_PC11, GPIO_PC10, GPIO_PC9, GPIO_PC8, GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, /* PD */ GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12, GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8, GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, /* PE */ GPIO_PE15, GPIO_PE14, GPIO_PE13, GPIO_PE12, GPIO_PE11, GPIO_PE10, GPIO_PE9, GPIO_PE8, GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, /* PF */ GPIO_PF30, GPIO_PF29, GPIO_PF28, GPIO_PF27, GPIO_PF26, GPIO_PF25, GPIO_PF24, GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20, GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16, GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12, GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8, GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, /* INTC: IRQ and PINT on PB/PD/PE */ GPIO_FN_PINT7_PB, GPIO_FN_PINT6_PB, GPIO_FN_PINT5_PB, GPIO_FN_PINT4_PB, GPIO_FN_PINT3_PB, GPIO_FN_PINT2_PB, GPIO_FN_PINT1_PB, GPIO_FN_PINT0_PB, GPIO_FN_PINT7_PD, GPIO_FN_PINT6_PD, GPIO_FN_PINT5_PD, GPIO_FN_PINT4_PD, GPIO_FN_PINT3_PD, GPIO_FN_PINT2_PD, GPIO_FN_PINT1_PD, GPIO_FN_PINT0_PD, GPIO_FN_IRQ7_PB, GPIO_FN_IRQ6_PB, GPIO_FN_IRQ5_PB, GPIO_FN_IRQ4_PB, GPIO_FN_IRQ3_PB, GPIO_FN_IRQ2_PB, GPIO_FN_IRQ1_PB, GPIO_FN_IRQ0_PB, GPIO_FN_IRQ7_PD, GPIO_FN_IRQ6_PD, GPIO_FN_IRQ5_PD, GPIO_FN_IRQ4_PD, GPIO_FN_IRQ3_PD, GPIO_FN_IRQ2_PD, GPIO_FN_IRQ1_PD, GPIO_FN_IRQ0_PD, GPIO_FN_IRQ7_PE, GPIO_FN_IRQ6_PE, GPIO_FN_IRQ5_PE, GPIO_FN_IRQ4_PE, GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE, GPIO_FN_WDTOVF, GPIO_FN_IRQOUT, GPIO_FN_REFOUT, GPIO_FN_IRQOUT_REFOUT, GPIO_FN_UBCTRG, /* CAN */ GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, /* IIC3 */ GPIO_FN_SDA3, GPIO_FN_SCL3, GPIO_FN_SDA2, GPIO_FN_SCL2, GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0, /* DMAC */ GPIO_FN_TEND0_PD, GPIO_FN_TEND0_PE, GPIO_FN_DACK0_PD, GPIO_FN_DACK0_PE, GPIO_FN_DREQ0_PD, GPIO_FN_DREQ0_PE, GPIO_FN_TEND1_PD, GPIO_FN_TEND1_PE, GPIO_FN_DACK1_PD, GPIO_FN_DACK1_PE, GPIO_FN_DREQ1_PD, GPIO_FN_DREQ1_PE, GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DACK3, GPIO_FN_DREQ3, /* ADC */ GPIO_FN_ADTRG_PD, GPIO_FN_ADTRG_PE, /* BSC */ GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28, GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24, GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20, GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16, GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_CS4, GPIO_FN_MRES, GPIO_FN_BS, GPIO_FN_IOIS16, GPIO_FN_CS1, GPIO_FN_CS6_CE1B, GPIO_FN_CE2B, GPIO_FN_CS5_CE1A, GPIO_FN_CE2A, GPIO_FN_FRAME, GPIO_FN_WAIT, GPIO_FN_RDWR, GPIO_FN_CKE, GPIO_FN_CASU, GPIO_FN_BREQ, GPIO_FN_RASU, GPIO_FN_BACK, GPIO_FN_CASL, GPIO_FN_RASL, GPIO_FN_WE3_DQMUU_AH_ICIO_WR, GPIO_FN_WE2_DQMUL_ICIORD, GPIO_FN_WE1_DQMLU_WE, GPIO_FN_WE0_DQMLL, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_A1, GPIO_FN_A0, GPIO_FN_CS7, /* TMU */ GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A, GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A, GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A, GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, GPIO_FN_TCLKD_PD, GPIO_FN_TCLKC_PD, GPIO_FN_TCLKB_PD, GPIO_FN_TCLKA_PD, GPIO_FN_TCLKD_PF, GPIO_FN_TCLKC_PF, GPIO_FN_TCLKB_PF, GPIO_FN_TCLKA_PF, /* SSU */ GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD, GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF, GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD, GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF, /* SCIF */ GPIO_FN_TXD0, GPIO_FN_RXD0, GPIO_FN_SCK0, GPIO_FN_TXD1, GPIO_FN_RXD1, GPIO_FN_SCK1, GPIO_FN_TXD2, GPIO_FN_RXD2, GPIO_FN_SCK2, GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3, GPIO_FN_SCK3, /* SSI */ GPIO_FN_AUDIO_CLK, GPIO_FN_SSIDATA3, GPIO_FN_SSIWS3, GPIO_FN_SSISCK3, GPIO_FN_SSIDATA2, GPIO_FN_SSIWS2, GPIO_FN_SSISCK2, GPIO_FN_SSIDATA1, GPIO_FN_SSIWS1, GPIO_FN_SSISCK1, GPIO_FN_SSIDATA0, GPIO_FN_SSIWS0, GPIO_FN_SSISCK0, /* FLCTL */ GPIO_FN_FCE, GPIO_FN_FRB, GPIO_FN_NAF7, GPIO_FN_NAF6, GPIO_FN_NAF5, GPIO_FN_NAF4, GPIO_FN_NAF3, GPIO_FN_NAF2, GPIO_FN_NAF1, GPIO_FN_NAF0, GPIO_FN_FSC, GPIO_FN_FOE, GPIO_FN_FCDE, GPIO_FN_FWE, /* LCDC */ GPIO_FN_LCD_VEPWC, GPIO_FN_LCD_VCPWC, GPIO_FN_LCD_CLK, GPIO_FN_LCD_FLM, GPIO_FN_LCD_M_DISP, GPIO_FN_LCD_CL2, GPIO_FN_LCD_CL1, GPIO_FN_LCD_DON, GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14, GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12, GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10, GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8, GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6, GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4, GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2, GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0, }; #endif /* __ASM_SH7203_H__ */ PK ! ��9N� � include/cpu-sh2a/cpu/sh7264.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7264_H__ #define __ASM_SH7264_H__ enum { /* Port A */ GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0, /* Port B */ GPIO_PB22, GPIO_PB21, GPIO_PB20, GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16, GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12, GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, GPIO_PB3, GPIO_PB2, GPIO_PB1, /* Port C */ GPIO_PC10, GPIO_PC9, GPIO_PC8, GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, /* Port D */ GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12, GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8, GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, /* Port E */ GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, /* Port F */ GPIO_PF12, GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8, GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, /* Port G */ GPIO_PG24, GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20, GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16, GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12, GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8, GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4, GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0, /* Port H - Port H does not have a Data Register */ /* Port I - not on device */ /* Port J */ GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8, GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4, GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0, /* Port K */ GPIO_PK11, GPIO_PK10, GPIO_PK9, GPIO_PK8, GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4, GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0, /* INTC: IRQ and PINT on PB/PD/PE */ GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG, GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, GPIO_FN_IRQ7_PC, GPIO_FN_IRQ6_PC, GPIO_FN_IRQ5_PC, GPIO_FN_IRQ4_PC, GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ, GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE, /* WDT */ GPIO_FN_WDTOVF, /* CAN */ GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, /* DMAC */ GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1, /* ADC */ GPIO_FN_ADTRG, /* BSC */ GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, GPIO_FN_BS, GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0, GPIO_FN_CS6CE1B, GPIO_FN_CS5CE1A, GPIO_FN_CE2A, GPIO_FN_CE2B, GPIO_FN_RD, GPIO_FN_RDWR, GPIO_FN_ICIOWRAH, GPIO_FN_ICIORD, GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML, GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE, GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK, GPIO_FN_IOIS16, /* TMU */ GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A, GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A, GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A, GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, /* SCIF */ GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3, GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3, GPIO_FN_TXD0, GPIO_FN_TXD1, GPIO_FN_TXD2, GPIO_FN_TXD3, GPIO_FN_RXD4, GPIO_FN_RXD5, GPIO_FN_RXD6, GPIO_FN_RXD7, GPIO_FN_TXD4, GPIO_FN_TXD5, GPIO_FN_TXD6, GPIO_FN_TXD7, GPIO_FN_RTS1, GPIO_FN_RTS3, GPIO_FN_CTS1, GPIO_FN_CTS3, /* RSPI */ GPIO_FN_RSPCK0, GPIO_FN_MOSI0, GPIO_FN_MISO0_PF12, GPIO_FN_MISO1, GPIO_FN_SSL00, GPIO_FN_RSPCK1, GPIO_FN_MOSI1, GPIO_FN_MISO1_PG19, GPIO_FN_SSL10, /* IIC3 */ GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2, GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0, /* SSI */ GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0, GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3, GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3, GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3, GPIO_FN_AUDIO_CLK, /* SIOF */ GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK, /* SPDIF */ GPIO_FN_SPDIF_IN, GPIO_FN_SPDIF_OUT, /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ GPIO_FN_FCE, GPIO_FN_FRB, /* VDC3 */ GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC, GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4, GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0, GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK, GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE, GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14, GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12, GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10, GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8, GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6, GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4, GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2, GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0, GPIO_FN_LCD_M_DISP, }; #endif /* __ASM_SH7264_H__ */ PK ! \ � � include/cpu-sh2a/cpu/rtc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CPU_SH2A_RTC_H #define __ASM_SH_CPU_SH2A_RTC_H #define rtc_reg_size sizeof(u16) #define RTC_BIT_INVERTED 0 #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR #endif /* __ASM_SH_CPU_SH2A_RTC_H */ PK ! G�BR R include/cpu-sh2a/cpu/sh7269.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7269_H__ #define __ASM_SH7269_H__ enum { /* Port A */ GPIO_PA1, GPIO_PA0, /* Port B */ GPIO_PB22, GPIO_PB21, GPIO_PB20, GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16, GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12, GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, GPIO_PB3, GPIO_PB2, GPIO_PB1, /* Port C */ GPIO_PC8, GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, /* Port D */ GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12, GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8, GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, /* Port E */ GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, /* Port F */ GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20, GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16, GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12, GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8, GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, /* Port G */ GPIO_PG27, GPIO_PG26, GPIO_PG25, GPIO_PG24, GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20, GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16, GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12, GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8, GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4, GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0, /* Port H - Port H does not have a Data Register */ /* Port I - not on device */ /* Port J */ GPIO_PJ31, GPIO_PJ30, GPIO_PJ29, GPIO_PJ28, GPIO_PJ27, GPIO_PJ26, GPIO_PJ25, GPIO_PJ24, GPIO_PJ23, GPIO_PJ22, GPIO_PJ21, GPIO_PJ20, GPIO_PJ19, GPIO_PJ18, GPIO_PJ17, GPIO_PJ16, GPIO_PJ15, GPIO_PJ14, GPIO_PJ13, GPIO_PJ12, GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8, GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4, GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0, /* INTC: IRQ and PINT */ GPIO_FN_IRQ7_PG, GPIO_FN_IRQ6_PG, GPIO_FN_IRQ5_PG, GPIO_FN_IRQ4_PG, GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PG, GPIO_FN_IRQ0_PG, GPIO_FN_IRQ7_PF, GPIO_FN_IRQ6_PF, GPIO_FN_IRQ5_PF, GPIO_FN_IRQ4_PF, GPIO_FN_IRQ3_PJ, GPIO_FN_IRQ2_PJ, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ, GPIO_FN_IRQ1_PC, GPIO_FN_IRQ0_PC, GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG, GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, GPIO_FN_PINT0_PG, GPIO_FN_PINT7_PH, GPIO_FN_PINT6_PH, GPIO_FN_PINT5_PH, GPIO_FN_PINT4_PH, GPIO_FN_PINT3_PH, GPIO_FN_PINT2_PH, GPIO_FN_PINT1_PH, GPIO_FN_PINT0_PH, GPIO_FN_PINT7_PJ, GPIO_FN_PINT6_PJ, GPIO_FN_PINT5_PJ, GPIO_FN_PINT4_PJ, GPIO_FN_PINT3_PJ, GPIO_FN_PINT2_PJ, GPIO_FN_PINT1_PJ, GPIO_FN_PINT0_PJ, /* WDT */ GPIO_FN_WDTOVF, /* CAN */ GPIO_FN_CTX2, GPIO_FN_CRX2, GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CRX0, GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1, GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2, GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20, GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22, GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22, GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20, /* DMAC */ GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1, /* ADC */ GPIO_FN_ADTRG, /* BSC */ GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, GPIO_FN_BS, GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0, GPIO_FN_CS5CE1A, GPIO_FN_CE2A, GPIO_FN_CE2B, GPIO_FN_RD, GPIO_FN_RDWR, GPIO_FN_WE3ICIOWRAHDQMUU, GPIO_FN_WE2ICIORDDQMUL, GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML, GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE, GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK, GPIO_FN_IOIS16, /* TMU */ GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A, GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A, GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A, GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, /* SCIF */ GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0, GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1, GPIO_FN_SCK2, GPIO_FN_RXD2, GPIO_FN_TXD2, GPIO_FN_SCK3, GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_SCK4, GPIO_FN_RXD4, GPIO_FN_TXD4, GPIO_FN_SCK5, GPIO_FN_RXD5, GPIO_FN_TXD5, GPIO_FN_RTS5, GPIO_FN_CTS5, GPIO_FN_SCK6, GPIO_FN_RXD6, GPIO_FN_TXD6, GPIO_FN_SCK7, GPIO_FN_RXD7, GPIO_FN_TXD7, GPIO_FN_RTS7, GPIO_FN_CTS7, /* RSPI */ GPIO_FN_MISO0_PJ19, GPIO_FN_MISO0_PB20, GPIO_FN_MOSI0_PJ18, GPIO_FN_MOSI0_PB19, GPIO_FN_SSL00_PJ17, GPIO_FN_SSL00_PB18, GPIO_FN_RSPCK0_PJ16, GPIO_FN_RSPCK0_PB17, GPIO_FN_RSPCK1, GPIO_FN_MOSI1, GPIO_FN_MISO1, GPIO_FN_SSL10, /* IIC3 */ GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2, GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0, /* SSI */ GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0, GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3, GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3, GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3, GPIO_FN_AUDIO_CLK, GPIO_FN_AUDIO_XOUT, /* SIOF */ GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK, /* SPDIF */ GPIO_FN_SPDIF_IN, GPIO_FN_SPDIF_OUT, /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ GPIO_FN_FCE, GPIO_FN_FRB, /* VDC */ GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC, GPIO_FN_DV_DATA23, GPIO_FN_DV_DATA22, GPIO_FN_DV_DATA21, GPIO_FN_DV_DATA20, GPIO_FN_DV_DATA19, GPIO_FN_DV_DATA18, GPIO_FN_DV_DATA17, GPIO_FN_DV_DATA16, GPIO_FN_DV_DATA15, GPIO_FN_DV_DATA14, GPIO_FN_DV_DATA13, GPIO_FN_DV_DATA12, GPIO_FN_DV_DATA11, GPIO_FN_DV_DATA10, GPIO_FN_DV_DATA9, GPIO_FN_DV_DATA8, GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4, GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0, GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK, GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE, GPIO_FN_LCD_DATA23_PG23, GPIO_FN_LCD_DATA22_PG22, GPIO_FN_LCD_DATA21_PG21, GPIO_FN_LCD_DATA20_PG20, GPIO_FN_LCD_DATA19_PG19, GPIO_FN_LCD_DATA18_PG18, GPIO_FN_LCD_DATA17_PG17, GPIO_FN_LCD_DATA16_PG16, GPIO_FN_LCD_DATA15_PG15, GPIO_FN_LCD_DATA14_PG14, GPIO_FN_LCD_DATA13_PG13, GPIO_FN_LCD_DATA12_PG12, GPIO_FN_LCD_DATA11_PG11, GPIO_FN_LCD_DATA10_PG10, GPIO_FN_LCD_DATA9_PG9, GPIO_FN_LCD_DATA8_PG8, GPIO_FN_LCD_DATA7_PG7, GPIO_FN_LCD_DATA6_PG6, GPIO_FN_LCD_DATA5_PG5, GPIO_FN_LCD_DATA4_PG4, GPIO_FN_LCD_DATA3_PG3, GPIO_FN_LCD_DATA2_PG2, GPIO_FN_LCD_DATA1_PG1, GPIO_FN_LCD_DATA0_PG0, GPIO_FN_LCD_DATA23_PJ23, GPIO_FN_LCD_DATA22_PJ22, GPIO_FN_LCD_DATA21_PJ21, GPIO_FN_LCD_DATA20_PJ20, GPIO_FN_LCD_DATA19_PJ19, GPIO_FN_LCD_DATA18_PJ18, GPIO_FN_LCD_DATA17_PJ17, GPIO_FN_LCD_DATA16_PJ16, GPIO_FN_LCD_DATA15_PJ15, GPIO_FN_LCD_DATA14_PJ14, GPIO_FN_LCD_DATA13_PJ13, GPIO_FN_LCD_DATA12_PJ12, GPIO_FN_LCD_DATA11_PJ11, GPIO_FN_LCD_DATA10_PJ10, GPIO_FN_LCD_DATA9_PJ9, GPIO_FN_LCD_DATA8_PJ8, GPIO_FN_LCD_DATA7_PJ7, GPIO_FN_LCD_DATA6_PJ6, GPIO_FN_LCD_DATA5_PJ5, GPIO_FN_LCD_DATA4_PJ4, GPIO_FN_LCD_DATA3_PJ3, GPIO_FN_LCD_DATA2_PJ2, GPIO_FN_LCD_DATA1_PJ1, GPIO_FN_LCD_DATA0_PJ0, GPIO_FN_LCD_M_DISP, }; #endif /* __ASM_SH7269_H__ */ PK ! ,��C" " include/cpu-sh2a/cpu/addrspace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CPU_SH2A_ADDRSPACE_H #define __ASM_SH_CPU_SH2A_ADDRSPACE_H #define P0SEG 0x00000000 #define P1SEG 0x00000000 #define P2SEG 0x20000000 #define P3SEG 0x40000000 #define P4SEG 0x60000000 #endif /* __ASM_SH_CPU_SH2A_ADDRSPACE_H */ PK ! j�~ I I include/cpu-sh2a/cpu/watchdog.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <cpu-sh2/cpu/watchdog.h> PK ! ι�� � include/mach-migor/mach/migor.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_MIGOR_H #define __ASM_SH_MIGOR_H #define PORT_MSELCRA 0xa4050180 #define PORT_MSELCRB 0xa4050182 #define BSC_CS4BCR 0xfec10010 #define BSC_CS6ABCR 0xfec1001c #define BSC_CS4WCR 0xfec10030 #include <video/sh_mobile_lcdc.h> int migor_lcd_qvga_setup(void *sys_ops_handle, struct sh_mobile_lcdc_sys_bus_ops *sys_ops); #endif /* __ASM_SH_MIGOR_H */ PK ! %k�_� � ! include/mach-x3proto/mach/ilsel.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_ILSEL_H #define __ASM_SH_ILSEL_H typedef enum { ILSEL_NONE, ILSEL_LAN, ILSEL_USBH_I, ILSEL_USBH_S, ILSEL_USBH_V, ILSEL_RTC, ILSEL_USBP_I, ILSEL_USBP_S, ILSEL_USBP_V, ILSEL_KEY, /* * ILSEL Aliases - corner cases for interleaved level tables. * * Someone thought this was a good idea and less hassle than * demuxing a shared vector, really. */ /* ILSEL0 and 2 */ ILSEL_FPGA0, ILSEL_FPGA1, ILSEL_EX1, ILSEL_EX2, ILSEL_EX3, ILSEL_EX4, /* ILSEL1 and 3 */ ILSEL_FPGA2 = ILSEL_FPGA0, ILSEL_FPGA3 = ILSEL_FPGA1, ILSEL_EX5 = ILSEL_EX1, ILSEL_EX6 = ILSEL_EX2, ILSEL_EX7 = ILSEL_EX3, ILSEL_EX8 = ILSEL_EX4, } ilsel_source_t; /* arch/sh/boards/renesas/x3proto/ilsel.c */ int ilsel_enable(ilsel_source_t set); int ilsel_enable_fixed(ilsel_source_t set, unsigned int level); void ilsel_disable(unsigned int irq); #endif /* __ASM_SH_ILSEL_H */ PK ! Ǵ�8 8 $ include/mach-x3proto/mach/hardware.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_X3PROTO_HARDWARE_H #define __MACH_X3PROTO_HARDWARE_H struct gpio_chip; /* arch/sh/boards/mach-x3proto/gpio.c */ int x3proto_gpio_setup(void); extern struct gpio_chip x3proto_gpio_chip; #define NR_BASEBOARD_GPIOS 16 #endif /* __MACH_X3PROTO_HARDWARE_H */ PK ! �� �� � include/mach-common/mach/r2d.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_RTS7751R2D_H #define __ASM_SH_RENESAS_RTS7751R2D_H /* * linux/include/asm-sh/renesas_rts7751r2d.h * * Copyright (C) 2000 Atom Create Engineering Co., Ltd. * * Renesas Technology Sales RTS7751R2D support */ /* Board specific addresses. */ #define PA_BCR 0xa4000000 /* FPGA */ #define PA_IRLMON 0xa4000002 /* Interrupt Status control */ #define PA_CFCTL 0xa4000004 /* CF Timing control */ #define PA_CFPOW 0xa4000006 /* CF Power control */ #define PA_DISPCTL 0xa4000008 /* Display Timing control */ #define PA_SDMPOW 0xa400000a /* SD Power control */ #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ #define PA_PCICD 0xa400000e /* PCI Extension detect control */ #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */ #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */ #define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */ #define PA_R2D1_EXTRST 0xa4000028 /* Extension Reset control */ #define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ #define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */ #define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */ #define PA_R2DPLUS_EXTRST 0xa4000026 /* Extension Reset control */ #define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ #define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ #define PA_POWOFF 0xa4000030 /* Board Power OFF control */ #define PA_VERREG 0xa4000032 /* FPGA Version Register */ #define PA_INPORT 0xa4000034 /* KEY Input Port control */ #define PA_OUTPORT 0xa4000036 /* LED control */ #define PA_BVERREG 0xa4000038 /* Board Revision Register */ #define PA_AX88796L 0xaa000400 /* AX88796L Area */ #define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define R2D_FPGA_IRQ_BASE 100 #define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0) #define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1) #define IRQ_TP (R2D_FPGA_IRQ_BASE + 2) #define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3) #define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4) #define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5) #define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6) #define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7) #define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8) #define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9) #define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10) #define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11) #define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12) #define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13) /* arch/sh/boards/renesas/rts7751r2d/irq.c */ void init_rts7751r2d_IRQ(void); int rts7751r2d_irq_demux(int); #endif /* __ASM_SH_RENESAS_RTS7751R2D */ PK ! .V� � " include/mach-common/mach/sdk7780.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_SDK7780_H #define __ASM_SH_RENESAS_SDK7780_H /* * linux/include/asm-sh/sdk7780.h * * Renesas Solutions SH7780 SDK Support * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk> */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0xa0800000 /* Flash-ROM */ #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ #define PA_SDRAM_SIZE 0x08000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_EXT_USER PA_EXT4 /* User Expansion Space */ #define PA_PERIPHERAL PA_AREA5_IO /* SRAM/Reserved */ #define PA_RESERVED (PA_PERIPHERAL + 0) /* FPGA base address */ #define PA_FPGA (PA_PERIPHERAL + 0x01000000) /* SMC LAN91C111 */ #define PA_LAN (PA_PERIPHERAL + 0x01800000) #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */ #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */ #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */ #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */ #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */ #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */ #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */ #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */ #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */ #define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */ #define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */ #define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */ #define PA_LED FPGA_SLEDR #define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */ #define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */ #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */ #define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */ #define FPGA_EASR (PA_FPGA + 0x110) /* External area select */ #define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */ #define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */ #define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */ #define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */ #define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */ #define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */ #define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */ #define SDK7780_NR_IRL 15 /* IDE/ATA interrupt */ #define IRQ_CFCARD evt2irq(0x3c0) /* SMC interrupt */ #define IRQ_ETHERNET evt2irq(0x2c0) /* arch/sh/boards/renesas/sdk7780/irq.c */ void init_sdk7780_IRQ(void); #define __IO_PREFIX sdk7780 #include <asm/io_generic.h> #endif /* __ASM_SH_RENESAS_SDK7780_H */ PK ! e��b ' include/mach-common/mach/magicpanelr2.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/magicpanelr2.h * * Copyright (C) 2007 Markus Brunner, Mark Jonas * * I/O addresses and bitmasks for Magic Panel Release 2 board */ #ifndef __ASM_SH_MAGICPANELR2_H #define __ASM_SH_MAGICPANELR2_H #include <linux/gpio.h> #define __IO_PREFIX mpr2 #include <asm/io_generic.h> #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) #define PA_LED PORT_PADR /* LED */ /* BSC */ #define CMNCR 0xA4FD0000UL #define CS0BCR 0xA4FD0004UL #define CS2BCR 0xA4FD0008UL #define CS3BCR 0xA4FD000CUL #define CS4BCR 0xA4FD0010UL #define CS5ABCR 0xA4FD0014UL #define CS5BBCR 0xA4FD0018UL #define CS6ABCR 0xA4FD001CUL #define CS6BBCR 0xA4FD0020UL #define CS0WCR 0xA4FD0024UL #define CS2WCR 0xA4FD0028UL #define CS3WCR 0xA4FD002CUL #define CS4WCR 0xA4FD0030UL #define CS5AWCR 0xA4FD0034UL #define CS5BWCR 0xA4FD0038UL #define CS6AWCR 0xA4FD003CUL #define CS6BWCR 0xA4FD0040UL /* usb */ #define PORT_UTRCTL 0xA405012CUL #define PORT_UCLKCR_W 0xA40A0008UL #define INTC_ICR0 0xA414FEE0UL #define INTC_ICR1 0xA4140010UL #define INTC_ICR2 0xA4140012UL /* MTD */ #define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL #define MPR2_MTD_KERNEL_SIZE 0x00200000UL #endif /* __ASM_SH_MAGICPANELR2_H */ PK ! �>��� � # include/mach-common/mach/microdev.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * linux/include/asm-sh/microdev.h * * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) * * Definitions for the SuperH SH4-202 MicroDev board. */ #ifndef __ASM_SH_MICRODEV_H #define __ASM_SH_MICRODEV_H extern void init_microdev_irq(void); extern void microdev_print_fpga_intc_status(void); /* * The following are useful macros for manipulating the interrupt * controller (INTC) on the CPU-board FPGA. should be noted that there * is an INTC on the FPGA, and a separate INTC on the SH4-202 core - * these are two different things, both of which need to be prorammed to * correctly route - unfortunately, they have the same name and * abbreviations! */ #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */ #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */ /* * The following are the IRQ numbers for the Linux Kernel for external * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'. */ #define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ #define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */ #define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */ #define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ #define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */ #define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ #define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */ #define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */ /* * The following are the IRQ numbers for the INTC on the FPGA for * external interrupts. i.e. the bits in the INTC registers in the * FPGA. */ #define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ #define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */ #define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ #define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ #define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */ #define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */ #define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */ #define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */ #define MICRODEV_IRQ_PCI_INTA 8 #define MICRODEV_IRQ_PCI_INTB 9 #define MICRODEV_IRQ_PCI_INTC 10 #define MICRODEV_IRQ_PCI_INTD 11 #define __IO_PREFIX microdev #include <asm/io_generic.h> #endif /* __ASM_SH_MICRODEV_H */ PK ! � �]� � # include/mach-common/mach/romimage.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifdef __ASSEMBLY__ /* do nothing here by default */ #else /* __ASSEMBLY__ */ static inline void mmcif_update_progress(int nr) { } #endif /* __ASSEMBLY__ */ PK ! �aS� � ! include/mach-common/mach/sh2007.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_SH2007_H #define __MACH_SH2007_H #define CS5BCR 0xff802050 #define CS5WCR 0xff802058 #define CS5PCR 0xff802070 #define BUS_SZ8 1 #define BUS_SZ16 2 #define BUS_SZ32 3 #define PCMCIA_IODYN 1 #define PCMCIA_ATA 0 #define PCMCIA_IO8 2 #define PCMCIA_IO16 3 #define PCMCIA_COMM8 4 #define PCMCIA_COMM16 5 #define PCMCIA_ATTR8 6 #define PCMCIA_ATTR16 7 #define TYPE_SRAM 0 #define TYPE_PCMCIA 4 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ #define IWW5 0 #define IWW6 3 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRWD5 2 #define IWRWD6 2 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRWS5 2 #define IWRWS6 2 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRRD5 2 #define IWRRD6 2 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRRS5 0 #define IWRRS6 2 /* burst count (0-3:4,8,16,32) */ #define BST5 0 #define BST6 0 /* bus size */ #define SZ5 BUS_SZ16 #define SZ6 BUS_SZ16 /* RD hold for SRAM (0-1:0,1) */ #define RDSPL5 0 #define RDSPL6 0 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ #define BW5 0 #define BW6 0 /* Multiplex (0-1:0,1) */ #define MPX5 0 #define MPX6 0 /* device type */ #define TYPE5 TYPE_PCMCIA #define TYPE6 TYPE_PCMCIA /* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define ADS5 0 #define ADS6 0 /* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define ADH5 0 #define ADH6 0 /* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define RDS5 0 #define RDS6 0 /* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define RDH5 0 #define RDH6 0 /* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define WTS5 0 #define WTS6 0 /* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define WTH5 0 #define WTH6 0 /* BS hold (0-1:1,2) */ #define BSH5 0 #define BSH6 0 /* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ #define IW5 6 /* 60ns PIO mode 4 */ #define IW6 15 /* 250ns */ #define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */ #define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */ #define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */ #define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */ /* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ #define PCIW5 12 /* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */ #define TEDA5 2 /* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */ #define TEDB5 4 /* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */ #define TEHA5 2 /* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */ #define TEHB5 3 #define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \ (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \ (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5) #define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \ (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5) #define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \ (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \ (TEDB5<<8)|(TEHA5<<4)|TEHB5) #define SMC0_BASE 0xb0800000 /* eth0 */ #define SMC1_BASE 0xb0900000 /* eth1 */ #define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */ #define IDE_BASE 0xb4000000 /* IDE */ #define PC104_IO_BASE 0xb8000000 #define PC104_MEM_BASE 0xba000000 #define SMC_IO_SIZE 0x100 #define CF_OFFSET 0x1f0 #define IDE_OFFSET 0x170 #endif /* __MACH_SH2007_H */ PK ! �)}' }' % include/mach-common/mach/highlander.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_R7780RP_H #define __ASM_SH_RENESAS_R7780RP_H /* Box specific addresses. */ #define PA_NORFLASH_ADDR 0x00000000 #define PA_NORFLASH_SIZE 0x04000000 #if defined(CONFIG_SH_R7780MP) #define PA_BCR 0xa4000000 /* FPGA */ #define PA_SDPOW (-1) #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */ #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */ #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */ #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */ #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */ #define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */ #define PA_PCICD (PA_BCR+0x0010) /* PCI Connector detect control */ #define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */ #define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */ #define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */ #define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */ #define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */ #define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */ #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ #define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */ #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ #define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ #define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */ #define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */ #define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */ #define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */ #define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */ #define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */ #define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */ #define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */ #define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */ #define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */ #define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */ #define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */ #define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */ #define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */ #define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */ #define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */ #define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */ #define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */ #define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */ #define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */ #define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */ #define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */ #define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */ #define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */ #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */ #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */ #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */ #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */ #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */ #define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */ #define PA_POFF (PA_BCR+0x0800) /* System Power Off control */ #define PA_PMR (PA_BCR+0x0900) /* */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define IVDR_CK_ON 8 /* iVDR Clock ON */ #elif defined(CONFIG_SH_R7780RP) #define PA_POFF (-1) #define PA_BCR 0xa5000000 /* FPGA */ #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ #define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */ #define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */ #define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */ #define PA_PCICD (PA_BCR+0x000a) /* PCI Connector detect control */ #define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */ #define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */ #define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */ #define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */ #define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */ #define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */ #define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */ #define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */ #define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */ #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ #define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */ #define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */ #define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */ #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ #define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ #define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */ #define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */ #define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */ #define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */ #define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */ #define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */ #define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */ #define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */ #define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */ #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */ #define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */ #define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */ #define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */ #define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */ #define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */ #define PA_AX88796L 0xa5800400 /* AX88796L Area */ #define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */ #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define IVDR_CK_ON 8 /* iVDR Clock ON */ #elif defined(CONFIG_SH_R7785RP) #define PA_BCR 0xa4000000 /* FPGA */ #define PA_SDPOW (-1) #define PA_PCISCR (PA_BCR+0x0000) #define PA_IRLPRA (PA_BCR+0x0002) #define PA_IRLPRB (PA_BCR+0x0004) #define PA_IRLPRC (PA_BCR+0x0006) #define PA_IRLPRD (PA_BCR+0x0008) #define IRLCNTR1 (PA_BCR+0x0010) #define PA_IRLPRE (PA_BCR+0x000a) #define PA_IRLPRF (PA_BCR+0x000c) #define PA_EXIRLCR (PA_BCR+0x000e) #define PA_IRLMCR1 (PA_BCR+0x0010) #define PA_IRLMCR2 (PA_BCR+0x0012) #define PA_IRLSSR1 (PA_BCR+0x0014) #define PA_IRLSSR2 (PA_BCR+0x0016) #define PA_CFTCR (PA_BCR+0x0100) #define PA_CFPCR (PA_BCR+0x0102) #define PA_PCICR (PA_BCR+0x0110) #define PA_IVDRCTL (PA_BCR+0x0112) #define PA_IVDRSR (PA_BCR+0x0114) #define PA_PDRSTCR (PA_BCR+0x0116) #define PA_POFF (PA_BCR+0x0120) #define PA_LCDCR (PA_BCR+0x0130) #define PA_TPCR (PA_BCR+0x0140) #define PA_TPCKCR (PA_BCR+0x0142) #define PA_TPRSTR (PA_BCR+0x0144) #define PA_TPXPDR (PA_BCR+0x0146) #define PA_TPYPDR (PA_BCR+0x0148) #define PA_GPIOPFR (PA_BCR+0x0150) #define PA_GPIODR (PA_BCR+0x0152) #define PA_OBLED (PA_BCR+0x0154) #define PA_SWSR (PA_BCR+0x0156) #define PA_VERREG (PA_BCR+0x0158) #define PA_SMCR (PA_BCR+0x0200) #define PA_SMSMADR (PA_BCR+0x0202) #define PA_SMMR (PA_BCR+0x0204) #define PA_SMSADR1 (PA_BCR+0x0206) #define PA_SMSADR32 (PA_BCR+0x0244) #define PA_SMTRDR1 (PA_BCR+0x0246) #define PA_SMTRDR16 (PA_BCR+0x0264) #define PA_CU3MDR (PA_BCR+0x0300) #define PA_CU5MDR (PA_BCR+0x0302) #define PA_MMSR (PA_BCR+0x0400) #define IVDR_CK_ON 4 /* iVDR Clock ON */ #endif #define HL_FPGA_IRQ_BASE 200 #define HL_NR_IRL 15 #define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) #define IRQ_CF (HL_FPGA_IRQ_BASE + 1) #define IRQ_PSW (HL_FPGA_IRQ_BASE + 2) #define IRQ_EXT0 (HL_FPGA_IRQ_BASE + 3) #define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 4) #define IRQ_EXT2 (HL_FPGA_IRQ_BASE + 5) #define IRQ_EXT3 (HL_FPGA_IRQ_BASE + 6) #define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 7) #define IRQ_EXT5 (HL_FPGA_IRQ_BASE + 8) #define IRQ_EXT6 (HL_FPGA_IRQ_BASE + 9) #define IRQ_EXT7 (HL_FPGA_IRQ_BASE + 10) #define IRQ_SMBUS (HL_FPGA_IRQ_BASE + 11) #define IRQ_TP (HL_FPGA_IRQ_BASE + 12) #define IRQ_RTC (HL_FPGA_IRQ_BASE + 13) #define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14) #define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15) #define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16) unsigned char *highlander_plat_irq_setup(void); #ifdef CONFIG_SH_R7785RP void highlander_plat_pinmux_setup(void); #else #define highlander_plat_pinmux_setup() do { } while (0) #endif #endif /* __ASM_SH_RENESAS_R7780RP */ PK ! J�8�� � include/mach-common/mach/shmin.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SHMIN_H #define __ASM_SH_SHMIN_H #define SHMIN_IO_BASE 0xb0000000UL #define SHMIN_NE_IRQ IRQ2_IRQ #define SHMIN_NE_BASE 0x300 #endif PK ! ��� ) include/mach-common/mach/secureedge5410.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/snapgear.h * * Modified version of io_se.h for the snapgear-specific functions. * * IO functions for a SnapGear */ #ifndef _ASM_SH_IO_SNAPGEAR_H #define _ASM_SH_IO_SNAPGEAR_H #define __IO_PREFIX snapgear #include <asm/io_generic.h> /* * We need to remember what was written to the ioport as some bits * are shared with other functions and you cannot read back what was * written :-| * * Bit Read Write * ----------------------------------------------- * D0 DCD on ttySC1 power * D1 Reset Switch heatbeat * D2 ttySC0 CTS (7100) LAN * D3 - WAN * D4 ttySC0 DCD (7100) CONSOLE * D5 - ONLINE * D6 - VPN * D7 - DTR on ttySC1 * D8 - ttySC0 RTS (7100) * D9 - ttySC0 DTR (7100) * D10 - RTC SCLK * D11 RTC DATA RTC DATA * D12 - RTS RESET */ #define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000) extern unsigned short secureedge5410_ioport; #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ (secureedge5410_ioport = \ ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) #define SECUREEDGE_READ_IOPORT() \ ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) #endif /* _ASM_SH_IO_SNAPGEAR_H */ PK ! :�W�� � " include/mach-common/mach/urquell.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_URQUELL_H #define __MACH_URQUELL_H /* * ------ 0x00000000 ------------------------------------ * CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH * -----+ 0x04000000 ------------------------------------ * CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH * -----+ 0x08000000 ------------------------------------ * CS2 | DDR3 * CS3 | * -----+ 0x10000000 ------------------------------------ * CS4 | PCIe * -----+ 0x14000000 ------------------------------------ * CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA * -----+ 0x18000000 ------------------------------------ * CS6 | ATA, NAND FLASH * -----+ 0x1c000000 ------------------------------------ * CS7 | SH7786 register * -----+------------------------------------------------ */ #define NOR_FLASH_ADDR 0x00000000 #define NOR_FLASH_SIZE 0x04000000 #define CS1_BASE 0x05000000 #define CS5_BASE 0x15000000 #define FPGA_BASE CS1_BASE #define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS) #define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS) #define SRSTR_OFS 0x0000 /* System reset register */ #define BDMR_OFS 0x0010 /* Board operating mode resister */ #define IRL0SR_OFS 0x0020 /* IRL0 Status register */ #define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */ #define IRL1SR_OFS 0x0040 /* IRL1 Status register */ #define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */ #define IRL2SR_OFS 0x0060 /* IRL2 Status register */ #define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */ #define IRL3SR_OFS 0x0080 /* IRL3 Status register */ #define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */ #define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */ #define SLEDR_OFS 0x0130 /* LED control resister */ #define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */ #define FPVERR_OFS 0x0150 /* FPGA Version register */ #define FPDATER_OFS 0x0160 /* FPGA Date register */ #define FPYEARR_OFS 0x0170 /* FPGA Year register */ #define TCLKCR_OFS 0x0180 /* TCLK Control register */ #define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */ #define FPODR_OFS 0x1010 /* Output port data register */ #define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */ #define FPINDR_OFS 0x1030 /* Input port data register */ #define MDSWMR_OFS 0x1040 /* MODE SW monitor register */ #define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */ #define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */ #define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */ #define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */ #define LATCHCR_OFS 0x3000 /* Latch control register */ #define LATCUAR_OFS 0x3010 /* Latch upper address register */ #define LATCLAR_OFS 0x3012 /* Latch lower address register */ #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */ #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */ #define CHARLED_OFS 0x2000 /* Character LED */ #endif /* __MACH_URQUELL_H */ PK ! al3� include/mach-common/mach/titan.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Platform definitions for Titan */ #ifndef _ASM_SH_TITAN_H #define _ASM_SH_TITAN_H #include <linux/sh_intc.h> #define __IO_PREFIX titan #include <asm/io_generic.h> /* IRQ assignments */ #define TITAN_IRQ_WAN evt2irq(0x240) /* eth0 (WAN) */ #define TITAN_IRQ_LAN evt2irq(0x2a0) /* eth1 (LAN) */ #define TITAN_IRQ_MPCIA evt2irq(0x300) /* mPCI A */ #define TITAN_IRQ_MPCIB evt2irq(0x360) /* mPCI B */ #define TITAN_IRQ_USB evt2irq(0x360) /* USB */ #endif /* __ASM_SH_TITAN_H */ PK ! �'yn� � & include/mach-common/mach/mangle-port.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * SH version cribbed from the MIPS copy: * * Copyright (C) 2003, 2004 Ralf Baechle */ #ifndef __MACH_COMMON_MANGLE_PORT_H #define __MACH_COMMON_MANGLE_PORT_H /* * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; * less sane hardware forces software to fiddle with this... * * Regardless, if the host bus endianness mismatches that of PCI/ISA, then * you can't have the numerical value of data and byte addresses within * multibyte quantities both preserved at the same time. Hence two * variations of functions: non-prefixed ones that preserve the value * and prefixed ones that preserve byte addresses. The latters are * typically used for moving raw data between a peripheral and memory (cf. * string I/O functions), hence the "__mem_" prefix. */ #if defined(CONFIG_SWAP_IO_SPACE) # define ioswabb(x) (x) # define __mem_ioswabb(x) (x) # define ioswabw(x) le16_to_cpu(x) # define __mem_ioswabw(x) (x) # define ioswabl(x) le32_to_cpu(x) # define __mem_ioswabl(x) (x) # define ioswabq(x) le64_to_cpu(x) # define __mem_ioswabq(x) (x) #else # define ioswabb(x) (x) # define __mem_ioswabb(x) (x) # define ioswabw(x) (x) # define __mem_ioswabw(x) cpu_to_le16(x) # define ioswabl(x) (x) # define __mem_ioswabl(x) cpu_to_le32(x) # define ioswabq(x) (x) # define __mem_ioswabq(x) cpu_to_le32(x) #endif #endif /* __MACH_COMMON_MANGLE_PORT_H */ PK ! L�|�Y Y include/mach-common/mach/hp6xx.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2003, 2004, 2005 Andriy Skulysh */ #ifndef __ASM_SH_HP6XX_H #define __ASM_SH_HP6XX_H #include <linux/sh_intc.h> #define HP680_BTN_IRQ evt2irq(0x600) /* IRQ0_IRQ */ #define HP680_TS_IRQ evt2irq(0x660) /* IRQ3_IRQ */ #define HP680_HD64461_IRQ evt2irq(0x680) /* IRQ4_IRQ */ #define DAC_LCD_BRIGHTNESS 0 #define DAC_SPEAKER_VOLUME 1 #define PGDR_OPENED 0x01 #define PGDR_MAIN_BATTERY_OUT 0x04 #define PGDR_PLAY_BUTTON 0x08 #define PGDR_REWIND_BUTTON 0x10 #define PGDR_RECORD_BUTTON 0x20 #define PHDR_TS_PEN_DOWN 0x08 #define PJDR_LED_BLINK 0x02 #define PKDR_LED_GREEN 0x10 /* HP Palmtop 620lx/660lx speaker on/off */ #define PKDR_SPEAKER 0x20 #define SCPDR_TS_SCAN_ENABLE 0x20 #define SCPDR_TS_SCAN_Y 0x02 #define SCPDR_TS_SCAN_X 0x01 #define SCPCR_TS_ENABLE 0x405 #define SCPCR_TS_MASK 0xc0f #define ADC_CHANNEL_TS_Y 1 #define ADC_CHANNEL_TS_X 2 #define ADC_CHANNEL_BATTERY 3 #define ADC_CHANNEL_BACKUP 4 #define ADC_CHANNEL_CHARGE 5 /* HP Jornada 680/690 speaker on/off */ #define HD64461_GPADR_SPEAKER 0x01 #define HD64461_GPADR_PCMCIA0 (0x02|0x08) #define HD64461_GPBDR_LCDOFF 0x01 #define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78 #define HD64461_GPBDR_LED_RED 0x80 #include <asm/hd64461.h> #include <asm/io.h> #define PJDR 0xa4000130 #define PKDR 0xa4000132 #endif /* __ASM_SH_HP6XX_H */ PK ! |� ̤ � $ include/mach-common/mach/sh7763rdp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SH7763RDP_H #define __ASM_SH_SH7763RDP_H /* * linux/include/asm-sh/sh7763drp.h * * Copyright (C) 2008 Renesas Solutions * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> */ #include <asm/addrspace.h> /* clock control */ #define MSTPCR1 0xFFC80038 /* PORT */ #define PORT_PSEL0 0xFFEF0070 #define PORT_PSEL1 0xFFEF0072 #define PORT_PSEL2 0xFFEF0074 #define PORT_PSEL3 0xFFEF0076 #define PORT_PSEL4 0xFFEF0078 #define PORT_PACR 0xFFEF0000 #define PORT_PCCR 0xFFEF0004 #define PORT_PFCR 0xFFEF000A #define PORT_PGCR 0xFFEF000C #define PORT_PHCR 0xFFEF000E #define PORT_PICR 0xFFEF0010 #define PORT_PJCR 0xFFEF0012 #define PORT_PKCR 0xFFEF0014 #define PORT_PLCR 0xFFEF0016 #define PORT_PMCR 0xFFEF0018 #define PORT_PNCR 0xFFEF001A /* FPGA */ #define CPLD_BOARD_ID_ERV_REG 0xB1000000 #define CPLD_CPLD_CMD_REG 0xB1000006 /* * USB SH7763RDP board can use Host only. */ #define USB_USBHSC 0xFFEC80f0 /* arch/sh/boards/renesas/sh7763rdp/irq.c */ void init_sh7763rdp_IRQ(void); int sh7763rdp_irq_demux(int irq); #define __IO_PREFIX sh7763rdp #include <asm/io_generic.h> #endif /* __ASM_SH_SH7763RDP_H */ PK ! ��s� $ include/mach-common/mach/sh7785lcr.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_SH7785LCR_H #define __ASM_SH_RENESAS_SH7785LCR_H /* * This board has 2 physical memory maps. * It can be changed with DIP switch(S2-5). * * phys address | S2-5 = OFF | S2-5 = ON * -----------------------------+---------------+--------------- * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB * 0x18000000 - 0x1bffffff(CS6) | reserved | SD * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) * */ #define NOR_FLASH_ADDR 0x00000000 #define NOR_FLASH_SIZE 0x04000000 #define PLD_BASE_ADDR 0x04000000 #define PLD_PCICR (PLD_BASE_ADDR + 0x00) #define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02) #define PLD_LOCALCR (PLD_BASE_ADDR + 0x04) #define PLD_POFCR (PLD_BASE_ADDR + 0x06) #define PLD_LEDCR (PLD_BASE_ADDR + 0x08) #define PLD_SWSR (PLD_BASE_ADDR + 0x0a) #define PLD_VERSR (PLD_BASE_ADDR + 0x0c) #define PLD_MMSR (PLD_BASE_ADDR + 0x0e) #define PCA9564_ADDR 0x06000000 /* I2C */ #define PCA9564_SIZE 0x00000100 #define PCA9564_PROTO_32BIT_ADDR 0x14000000 #define SM107_MEM_ADDR 0x10000000 #define SM107_MEM_SIZE 0x00e00000 #define SM107_REG_ADDR 0x13e00000 #define SM107_REG_SIZE 0x00200000 #if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS) #define R8A66597_ADDR 0x14000000 /* USB */ #define CG200_ADDR 0x18000000 /* SD */ #else #define R8A66597_ADDR 0x08000000 #define CG200_ADDR 0x0c000000 #endif #define R8A66597_SIZE 0x00000100 #define CG200_SIZE 0x00010000 #endif /* __ASM_SH_RENESAS_SH7785LCR_H */ PK ! �HK�J J " include/mach-common/mach/lboxre2.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_LBOXRE2_H #define __ASM_SH_LBOXRE2_H /* * Copyright (C) 2007 Nobuhiro Iwamatsu * * NTT COMWARE L-BOX RE2 support */ #include <linux/sh_intc.h> #define IRQ_CF1 evt2irq(0x320) /* CF1 */ #define IRQ_CF0 evt2irq(0x340) /* CF0 */ #define IRQ_INTD evt2irq(0x360) /* INTD */ #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */ #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */ #define IRQ_INTA evt2irq(0x3c0) /* INTA */ void init_lboxre2_IRQ(void); #define __IO_PREFIX lboxre2 #include <asm/io_generic.h> #endif /* __ASM_SH_LBOXRE2_H */ PK ! ,Y'� � include/uapi/asm/hw_breakpoint.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * There isn't anything here anymore, but the file must not be empty or patch * will delete it. */ PK ! ̈h߃ � include/uapi/asm/cpu-features.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_CPU_FEATURES_H #define __ASM_SH_CPU_FEATURES_H /* * Processor flags * * Note: When adding a new flag, keep cpu_flags[] in * arch/sh/kernel/setup.c in sync so symbolic name * mapping of the processor flags has a chance of being * reasonably accurate. * * These flags are also available through the ELF * auxiliary vector as AT_HWCAP. */ #define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ #define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ #define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ #define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ #define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ #define CPU_HAS_PTEA 0x0020 /* PTEA register */ #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ #define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */ #endif /* __ASM_SH_CPU_FEATURES_H */ PK ! ��YZ Z include/uapi/asm/unistd.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #include <asm/unistd_32.h> PK ! ��XW W include/uapi/asm/Kbuildnu �[��� # SPDX-License-Identifier: GPL-2.0 generated-y += unistd_32.h generic-y += ucontext.h PK ! ��K! ! ! include/uapi/asm/posix_types_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_POSIX_TYPES_32_H #define __ASM_SH_POSIX_TYPES_32_H typedef unsigned short __kernel_mode_t; #define __kernel_mode_t __kernel_mode_t typedef unsigned short __kernel_ipc_pid_t; #define __kernel_ipc_pid_t __kernel_ipc_pid_t typedef unsigned short __kernel_uid_t; #define __kernel_uid_t __kernel_uid_t typedef unsigned short __kernel_gid_t; #define __kernel_gid_t __kernel_gid_t typedef unsigned short __kernel_old_uid_t; #define __kernel_old_uid_t __kernel_old_uid_t typedef unsigned short __kernel_old_gid_t; #define __kernel_old_gid_t __kernel_old_gid_t typedef unsigned short __kernel_old_dev_t; #define __kernel_old_dev_t __kernel_old_dev_t #include <asm-generic/posix_types.h> #endif /* __ASM_SH_POSIX_TYPES_32_H */ PK ! ( ��_ _ include/uapi/asm/posix_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #include <asm/posix_types_32.h> PK ! �}4�R R include/uapi/asm/ptrace_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPI__ASM_SH_PTRACE_32_H #define _UAPI__ASM_SH_PTRACE_32_H /* * GCC defines register number like this: * ----------------------------- * 0 - 15 are integer registers * 17 - 22 are control/special registers * 24 - 39 fp registers * 40 - 47 xd registers * 48 - fpscr register * ----------------------------- * * We follows above, except: * 16 --- program counter (PC) * 22 --- syscall # * 23 --- floating point communication register */ #define REG_REG0 0 #define REG_REG15 15 #define REG_PC 16 #define REG_PR 17 #define REG_SR 18 #define REG_GBR 19 #define REG_MACH 20 #define REG_MACL 21 #define REG_SYSCALL 22 #define REG_FPREG0 23 #define REG_FPREG15 38 #define REG_XFREG0 39 #define REG_XFREG15 54 #define REG_FPSCR 55 #define REG_FPUL 56 /* * This struct defines the way the registers are stored on the * kernel stack during a system call or other kernel entry. */ struct pt_regs { unsigned long regs[16]; unsigned long pc; unsigned long pr; unsigned long sr; unsigned long gbr; unsigned long mach; unsigned long macl; long tra; }; /* * This struct defines the way the DSP registers are stored on the * kernel stack during a system call or other kernel entry. */ struct pt_dspregs { unsigned long a1; unsigned long a0g; unsigned long a1g; unsigned long m0; unsigned long m1; unsigned long a0; unsigned long x0; unsigned long x1; unsigned long y0; unsigned long y1; unsigned long dsr; unsigned long rs; unsigned long re; unsigned long mod; }; #endif /* _UAPI__ASM_SH_PTRACE_32_H */ PK ! �� \q q include/uapi/asm/signal.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_SIGNAL_H #define __ASM_SH_SIGNAL_H #define SA_RESTORER 0x04000000 #include <asm-generic/signal.h> #ifndef __KERNEL__ struct old_sigaction { __sighandler_t sa_handler; old_sigset_t sa_mask; unsigned long sa_flags; void (*sa_restorer)(void); }; #endif #endif /* __ASM_SH_SIGNAL_H */ PK ! ��z�g g include/uapi/asm/ptrace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright (C) 1999, 2000 Niibe Yutaka */ #ifndef _UAPI__ASM_SH_PTRACE_H #define _UAPI__ASM_SH_PTRACE_H #define PTRACE_GETREGS 12 /* General registers */ #define PTRACE_SETREGS 13 #define PTRACE_GETFPREGS 14 /* FPU registers */ #define PTRACE_SETFPREGS 15 #define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ #define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ #define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ #define PTRACE_GETDSPREGS 55 /* DSP registers */ #define PTRACE_SETDSPREGS 56 #define PT_TEXT_END_ADDR 240 #define PT_TEXT_ADDR 244 /* &(struct user)->start_code */ #define PT_DATA_ADDR 248 /* &(struct user)->start_data */ #define PT_TEXT_LEN 252 #include <asm/ptrace_32.h> #endif /* _UAPI__ASM_SH_PTRACE_H */ PK ! Y�� include/uapi/asm/byteorder.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_BYTEORDER_H #define __ASM_SH_BYTEORDER_H #ifdef __LITTLE_ENDIAN__ #include <linux/byteorder/little_endian.h> #else #include <linux/byteorder/big_endian.h> #endif #endif /* __ASM_SH_BYTEORDER_H */ PK ! D2�Z Z include/uapi/asm/sockios.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_SOCKIOS_H #define __ASM_SH_SOCKIOS_H #include <linux/time_types.h> /* Socket-level I/O control calls. */ #define FIOGETOWN _IOR('f', 123, int) #define FIOSETOWN _IOW('f', 124, int) #define SIOCATMARK _IOR('s', 7, int) #define SIOCSPGRP _IOW('s', 8, pid_t) #define SIOCGPGRP _IOR('s', 9, pid_t) #define SIOCGSTAMP_OLD _IOR('s', 100, struct __kernel_old_timeval) /* Get stamp (timeval) */ #define SIOCGSTAMPNS_OLD _IOR('s', 101, struct __kernel_old_timespec) /* Get stamp (timespec) */ #endif /* __ASM_SH_SOCKIOS_H */ PK ! �]:& & include/uapi/asm/sigcontext.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_SIGCONTEXT_H #define __ASM_SH_SIGCONTEXT_H struct sigcontext { unsigned long oldmask; /* CPU registers */ unsigned long sc_regs[16]; unsigned long sc_pc; unsigned long sc_pr; unsigned long sc_sr; unsigned long sc_gbr; unsigned long sc_mach; unsigned long sc_macl; /* FPU registers */ unsigned long sc_fpregs[16]; unsigned long sc_xfpregs[16]; unsigned int sc_fpscr; unsigned int sc_fpul; unsigned int sc_ownedfp; }; #endif /* __ASM_SH_SIGCONTEXT_H */ PK ! @��� � include/uapi/asm/swab.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_SWAB_H #define __ASM_SH_SWAB_H /* * Copyright (C) 1999 Niibe Yutaka * Copyright (C) 2000, 2001 Paolo Alberelli */ #include <linux/compiler.h> #include <linux/types.h> #include <asm-generic/swab.h> static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __asm__( "swap.b %1, %0\n\t" "swap.w %0, %0\n\t" "swap.b %0, %0" : "=r" (x) : "r" (x)); return x; } #define __arch_swab32 __arch_swab32 static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { __asm__( "swap.b %1, %0" : "=r" (x) : "r" (x)); return x; } #define __arch_swab16 __arch_swab16 static inline __u64 __arch_swab64(__u64 val) { union { struct { __u32 a,b; } s; __u64 u; } v, w; v.u = val; w.s.b = __arch_swab32(v.s.a); w.s.a = __arch_swab32(v.s.b); return w.u; } #define __arch_swab64 __arch_swab64 #endif /* __ASM_SH_SWAB_H */ PK ! ���Y� � include/uapi/asm/stat.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_STAT_H #define __ASM_SH_STAT_H struct __old_kernel_stat { unsigned short st_dev; unsigned short st_ino; unsigned short st_mode; unsigned short st_nlink; unsigned short st_uid; unsigned short st_gid; unsigned short st_rdev; unsigned long st_size; unsigned long st_atime; unsigned long st_mtime; unsigned long st_ctime; }; struct stat { unsigned long st_dev; unsigned long st_ino; unsigned short st_mode; unsigned short st_nlink; unsigned short st_uid; unsigned short st_gid; unsigned long st_rdev; unsigned long st_size; unsigned long st_blksize; unsigned long st_blocks; unsigned long st_atime; unsigned long st_atime_nsec; unsigned long st_mtime; unsigned long st_mtime_nsec; unsigned long st_ctime; unsigned long st_ctime_nsec; unsigned long __unused4; unsigned long __unused5; }; /* This matches struct stat64 in glibc2.1, hence the absolutely * insane amounts of padding around dev_t's. */ struct stat64 { unsigned long long st_dev; unsigned char __pad0[4]; #define STAT64_HAS_BROKEN_ST_INO 1 unsigned long __st_ino; unsigned int st_mode; unsigned int st_nlink; unsigned long st_uid; unsigned long st_gid; unsigned long long st_rdev; unsigned char __pad3[4]; long long st_size; unsigned long st_blksize; unsigned long long st_blocks; /* Number 512-byte blocks allocated. */ unsigned long st_atime; unsigned long st_atime_nsec; unsigned long st_mtime; unsigned long st_mtime_nsec; unsigned long st_ctime; unsigned long st_ctime_nsec; unsigned long long st_ino; }; #define STAT_HAVE_NSEC 1 #endif /* __ASM_SH_STAT_H */ PK ! � �!� � include/uapi/asm/ioctls.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_IOCTLS_H #define __ASM_SH_IOCTLS_H #include <asm/ioctl.h> #define FIOCLEX _IO('f', 1) #define FIONCLEX _IO('f', 2) #define FIOASYNC _IOW('f', 125, int) #define FIONBIO _IOW('f', 126, int) #define FIONREAD _IOR('f', 127, int) #define TIOCINQ FIONREAD #define FIOQSIZE _IOR('f', 128, loff_t) #define TCGETS 0x5401 #define TCSETS 0x5402 #define TCSETSW 0x5403 #define TCSETSF 0x5404 #define TCGETA 0x80127417 /* _IOR('t', 23, struct termio) */ #define TCSETA 0x40127418 /* _IOW('t', 24, struct termio) */ #define TCSETAW 0x40127419 /* _IOW('t', 25, struct termio) */ #define TCSETAF 0x4012741C /* _IOW('t', 28, struct termio) */ #define TCSBRK _IO('t', 29) #define TCXONC _IO('t', 30) #define TCFLSH _IO('t', 31) #define TIOCSWINSZ 0x40087467 /* _IOW('t', 103, struct winsize) */ #define TIOCGWINSZ 0x80087468 /* _IOR('t', 104, struct winsize) */ #define TIOCSTART _IO('t', 110) /* start output, like ^Q */ #define TIOCSTOP _IO('t', 111) /* stop output, like ^S */ #define TIOCOUTQ _IOR('t', 115, int) /* output queue size */ #define TIOCSPGRP _IOW('t', 118, int) #define TIOCGPGRP _IOR('t', 119, int) #define TIOCEXCL _IO('T', 12) /* 0x540C */ #define TIOCNXCL _IO('T', 13) /* 0x540D */ #define TIOCSCTTY _IO('T', 14) /* 0x540E */ #define TIOCSTI _IOW('T', 18, char) /* 0x5412 */ #define TIOCMGET _IOR('T', 21, unsigned int) /* 0x5415 */ #define TIOCMBIS _IOW('T', 22, unsigned int) /* 0x5416 */ #define TIOCMBIC _IOW('T', 23, unsigned int) /* 0x5417 */ #define TIOCMSET _IOW('T', 24, unsigned int) /* 0x5418 */ # define TIOCM_LE 0x001 # define TIOCM_DTR 0x002 # define TIOCM_RTS 0x004 # define TIOCM_ST 0x008 # define TIOCM_SR 0x010 # define TIOCM_CTS 0x020 # define TIOCM_CAR 0x040 # define TIOCM_RNG 0x080 # define TIOCM_DSR 0x100 # define TIOCM_CD TIOCM_CAR # define TIOCM_RI TIOCM_RNG #define TIOCGSOFTCAR _IOR('T', 25, unsigned int) /* 0x5419 */ #define TIOCSSOFTCAR _IOW('T', 26, unsigned int) /* 0x541A */ #define TIOCLINUX _IOW('T', 28, char) /* 0x541C */ #define TIOCCONS _IO('T', 29) /* 0x541D */ #define TIOCGSERIAL 0x803C541E /* _IOR('T', 30, struct serial_struct) 0x541E */ #define TIOCSSERIAL 0x403C541F /* _IOW('T', 31, struct serial_struct) 0x541F */ #define TIOCPKT _IOW('T', 32, int) /* 0x5420 */ # define TIOCPKT_DATA 0 # define TIOCPKT_FLUSHREAD 1 # define TIOCPKT_FLUSHWRITE 2 # define TIOCPKT_STOP 4 # define TIOCPKT_START 8 # define TIOCPKT_NOSTOP 16 # define TIOCPKT_DOSTOP 32 # define TIOCPKT_IOCTL 64 #define TIOCNOTTY _IO('T', 34) /* 0x5422 */ #define TIOCSETD _IOW('T', 35, int) /* 0x5423 */ #define TIOCGETD _IOR('T', 36, int) /* 0x5424 */ #define TCSBRKP _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */ #define TIOCSBRK _IO('T', 39) /* 0x5427 */ /* BSD compatibility */ #define TIOCCBRK _IO('T', 40) /* 0x5428 */ /* BSD compatibility */ #define TIOCGSID _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */ #define TCGETS2 _IOR('T', 42, struct termios2) #define TCSETS2 _IOW('T', 43, struct termios2) #define TCSETSW2 _IOW('T', 44, struct termios2) #define TCSETSF2 _IOW('T', 45, struct termios2) #define TIOCGRS485 _IOR('T', 46, struct serial_rs485) #define TIOCSRS485 _IOWR('T', 47, struct serial_rs485) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ #define TIOCVHANGUP _IO('T', 0x37) #define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */ #define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */ #define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */ #define TIOCGPTPEER _IO('T', 0x41) /* Safely open the slave */ #define TIOCGISO7816 _IOR('T', 0x42, struct serial_iso7816) #define TIOCSISO7816 _IOWR('T', 0x43, struct serial_iso7816) #define TIOCSERCONFIG _IO('T', 83) /* 0x5453 */ #define TIOCSERGWILD _IOR('T', 84, int) /* 0x5454 */ #define TIOCSERSWILD _IOW('T', 85, int) /* 0x5455 */ #define TIOCGLCKTRMIOS 0x5456 #define TIOCSLCKTRMIOS 0x5457 #define TIOCSERGSTRUCT 0x80d85458 /* _IOR('T', 88, struct async_struct) 0x5458 */ /* For debugging only */ #define TIOCSERGETLSR _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */ /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ # define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ #define TIOCSERGETMULTI 0x80A8545A /* _IOR('T', 90, struct serial_multiport_struct) 0x545A */ /* Get multiport config */ #define TIOCSERSETMULTI 0x40A8545B /* _IOW('T', 91, struct serial_multiport_struct) 0x545B */ /* Set multiport config */ #define TIOCMIWAIT _IO('T', 92) /* 0x545C */ /* wait for a change on serial input line(s) */ #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ #endif /* __ASM_SH_IOCTLS_H */ PK ! :�� � include/uapi/asm/cachectl.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _SH_CACHECTL_H #define _SH_CACHECTL_H /* Definitions for the cacheflush system call. */ #define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */ #define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */ #define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */ #define CACHEFLUSH_I 0x4 /* * Options for cacheflush system call */ #define ICACHE CACHEFLUSH_I /* flush instruction cache */ #define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */ #define BCACHE (ICACHE|DCACHE) /* flush both caches */ #endif /* _SH_CACHECTL_H */ PK ! x�rS S include/uapi/asm/auxvec.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_SH_AUXVEC_H #define __ASM_SH_AUXVEC_H /* * Architecture-neutral AT_ values in 0-17, leave some room * for more of them. */ /* * This entry gives some information about the FPU initialization * performed by the kernel. */ #define AT_FPUCW 18 /* Used FPU control word. */ #if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__) /* * Only define this in the vsyscall case, the entry point to * the vsyscall page gets placed here. The kernel will attempt * to build a gate VMA we don't care about otherwise.. */ #define AT_SYSINFO_EHDR 33 #endif /* * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the * value is -1, then the cache doesn't exist. Otherwise: * * bit 0-3: Cache set-associativity; 0 means fully associative. * bit 4-7: Log2 of cacheline size. * bit 8-31: Size of the entire cache >> 8. */ #define AT_L1I_CACHESHAPE 34 #define AT_L1D_CACHESHAPE 35 #define AT_L2_CACHESHAPE 36 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ #endif /* __ASM_SH_AUXVEC_H */ PK ! �Y��- - * include/mach-landisk/mach/iodata_landisk.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_IODATA_LANDISK_H #define __ASM_SH_IODATA_LANDISK_H /* * arch/sh/include/mach-landisk/mach/iodata_landisk.h * * Copyright (C) 2000 Atom Create Engineering Co., Ltd. * * IO-DATA LANDISK support */ #include <linux/sh_intc.h> /* Box specific addresses. */ #define PA_USB 0xa4000000 /* USB Controller M66590 */ #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */ #define PA_LED 0xb0000001 /* LED Control Register */ #define PA_STATUS 0xb0000002 /* Switch Status Register */ #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */ #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */ #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */ /* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */ #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */ #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */ #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */ #define IRQ_PCIINTA evt2irq(0x2a0) /* PCI INTA IRQ */ #define IRQ_PCIINTB evt2irq(0x2c0) /* PCI INTB IRQ */ #define IRQ_PCIINTC evt2irq(0x2e0) /* PCI INTC IRQ */ #define IRQ_PCIINTD evt2irq(0x300) /* PCI INTD IRQ */ #define IRQ_ATA evt2irq(0x320) /* ATA IRQ */ #define IRQ_FATA evt2irq(0x340) /* FATA IRQ */ #define IRQ_POWER evt2irq(0x360) /* Power Switch IRQ */ #define IRQ_BUTTON evt2irq(0x380) /* USL-5P Button IRQ */ #define IRQ_FAULT evt2irq(0x3a0) /* USL-5P Fault IRQ */ void init_landisk_IRQ(void); #define __IO_PREFIX landisk #include <asm/io_generic.h> #endif /* __ASM_SH_IODATA_LANDISK_H */ PK ! d��r include/mach-landisk/mach/gio.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_LANDISK_GIO_H #define __ASM_SH_LANDISK_GIO_H #include <linux/ioctl.h> /* version */ #define VERSION_STR "1.00" /* Driver name */ #define GIO_DRIVER_NAME "/dev/giodrv" /* Use 'k' as magic number */ #define GIODRV_IOC_MAGIC 'k' #define GIODRV_IOCRESET _IO(GIODRV_IOC_MAGIC, 0) /* * S means "Set" through a ptr, * T means "Tell" directly * G means "Get" (to a pointed var) * Q means "Query", response is on the return value * X means "eXchange": G and S atomically * H means "sHift": T and Q atomically */ #define GIODRV_IOCSGIODATA1 _IOW(GIODRV_IOC_MAGIC, 1, unsigned char *) #define GIODRV_IOCGGIODATA1 _IOR(GIODRV_IOC_MAGIC, 2, unsigned char *) #define GIODRV_IOCSGIODATA2 _IOW(GIODRV_IOC_MAGIC, 3, unsigned short *) #define GIODRV_IOCGGIODATA2 _IOR(GIODRV_IOC_MAGIC, 4, unsigned short *) #define GIODRV_IOCSGIODATA4 _IOW(GIODRV_IOC_MAGIC, 5, unsigned long *) #define GIODRV_IOCGGIODATA4 _IOR(GIODRV_IOC_MAGIC, 6, unsigned long *) #define GIODRV_IOCSGIOSETADDR _IOW(GIODRV_IOC_MAGIC, 7, unsigned long *) #define GIODRV_IOCHARDRESET _IO(GIODRV_IOC_MAGIC, 8) /* debugging tool */ #define GIODRV_IOC_MAXNR 8 #define GIO_READ 0x00000000 #define GIO_WRITE 0x00000001 #endif /* __ASM_SH_LANDISK_GIO_H */ PK ! �/�� � include/mach-se/mach/se.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HITACHI_SE_H #define __ASM_SH_HITACHI_SE_H /* * linux/include/asm-sh/hitachi_se.h * * Copyright (C) 2000 Kazumoto Kojima * * Hitachi SolutionEngine support */ #include <linux/sh_intc.h> /* Box specific addresses. */ #define PA_ROM 0x00000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0x01000000 /* EPROM */ #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_EXT1 0x04000000 #define PA_EXT1_SIZE 0x04000000 #define PA_EXT2 0x08000000 #define PA_EXT2_SIZE 0x04000000 #define PA_SDRAM 0x0c000000 #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0x12000000 #define PA_EXT4_SIZE 0x02000000 #define PA_EXT5 0x14000000 #define PA_EXT5_SIZE 0x04000000 #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ #define PA_83902 0xb0000000 /* DP83902A */ #define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ #define PA_83902_RST 0xb0080000 /* DP83902A reset port */ #define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ #define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ #define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ #define PA_LED 0xb0c00000 /* LED */ #if defined(CONFIG_CPU_SUBTYPE_SH7705) #define PA_BCR 0xb0e00000 #else #define PA_BCR 0xb1400000 /* FPGA */ #endif #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define BCR_ILCRA (PA_BCR + 0) #define BCR_ILCRB (PA_BCR + 2) #define BCR_ILCRC (PA_BCR + 4) #define BCR_ILCRD (PA_BCR + 6) #define BCR_ILCRE (PA_BCR + 8) #define BCR_ILCRF (PA_BCR + 10) #define BCR_ILCRG (PA_BCR + 12) #if defined(CONFIG_CPU_SUBTYPE_SH7709) #define INTC_IRR0 0xa4000004UL #define INTC_IRR1 0xa4000006UL #define INTC_IRR2 0xa4000008UL #define INTC_ICR0 0xfffffee0UL #define INTC_ICR1 0xa4000010UL #define INTC_ICR2 0xa4000012UL #define INTC_INTER 0xa4000014UL #define INTC_IPRC 0xa4000016UL #define INTC_IPRD 0xa4000018UL #define INTC_IPRE 0xa400001aUL #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #endif #if defined(CONFIG_CPU_SUBTYPE_SH7705) #define IRQ_STNIC evt2irq(0x380) #define IRQ_CFCARD evt2irq(0x3c0) #else #define IRQ_STNIC evt2irq(0x340) #define IRQ_CFCARD evt2irq(0x2e0) #endif /* SH Ether support (SH7710/SH7712) */ /* Base address */ #define SH_ETH0_BASE 0xA7000000 #define SH_ETH1_BASE 0xA7000400 #define SH_TSU_BASE 0xA7000800 /* PHY ID */ #if defined(CONFIG_CPU_SUBTYPE_SH7710) # define PHY_ID 0x00 #elif defined(CONFIG_CPU_SUBTYPE_SH7712) # define PHY_ID 0x01 #endif /* Ether IRQ */ #define SH_ETH0_IRQ evt2irq(0xc00) #define SH_ETH1_IRQ evt2irq(0xc20) #define SH_TSU_IRQ evt2irq(0xc40) void init_se_IRQ(void); #define __IO_PREFIX se #include <asm/io_generic.h> #endif /* __ASM_SH_HITACHI_SE_H */ PK ! L � � include/mach-se/mach/se7722.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7722_H #define __ASM_SH_SE7722_H /* * linux/include/asm-sh/se7722.h * * Copyright (C) 2007 Nobuhiro Iwamatsu * * Hitachi UL SolutionEngine 7722 Support. */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ #define PA_FROM 0xa1000000 /* Flash-ROM */ #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_PERIPHERAL 0xB0000000 #define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ #define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ /* GPIO */ #define FPGA_IN 0xb1840000UL #define FPGA_OUT 0xb1840004UL #define PORT_PECR 0xA4050108UL #define PORT_PJCR 0xA4050110UL #define PORT_PSELD 0xA4050154UL #define PORT_PSELB 0xA4050150UL #define PORT_PSELC 0xA4050152UL #define PORT_PKCR 0xA4050112UL #define PORT_PHCR 0xA405010EUL #define PORT_PLCR 0xA4050114UL #define PORT_PMCR 0xA4050116UL #define PORT_PRCR 0xA405011CUL #define PORT_PXCR 0xA4050148UL #define PORT_PSELA 0xA405014EUL #define PORT_PYCR 0xA405014AUL #define PORT_PZCR 0xA405014CUL #define PORT_HIZCRA 0xA4050158UL #define PORT_HIZCRC 0xA405015CUL /* IRQ */ #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ #define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ #define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ #define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ #define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ #define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ #define SE7722_FPGA_IRQ_NR 6 struct irq_domain; /* arch/sh/boards/se/7722/irq.c */ extern struct irq_domain *se7722_irq_domain; void init_se7722_IRQ(void); #define __IO_PREFIX se7722 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7722_H */ PK ! �!�Z Z include/mach-se/mach/se7780.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7780_H #define __ASM_SH_SE7780_H /* * linux/include/asm-sh/se7780.h * * Copyright (C) 2006,2007 Nobuhiro Iwamatsu * * Hitachi UL SolutionEngine 7780 Support. */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0xa1000000 /* Flash-ROM */ #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */ #define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */ #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ #define PA_SDRAM_SIZE 0x08000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */ #define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */ #define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */ #define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */ #define DISP_CHAR_RAM (7 << 3) #define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0) #define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1) #define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2) #define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3) #define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4) #define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5) #define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6) #define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7) #define DISP_UDC_RAM (5 << 3) #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ /* FPGA register address and bit */ #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */ #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */ #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */ #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */ #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */ #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */ #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */ #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */ #define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */ #define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */ #define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */ #define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */ #define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */ #define PA_LED FPGA_DBG_LED #define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */ #define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */ #define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */ /* FPGA INTSEL position */ /* INTSEL1 */ #define IRQPOS_SMC91CX (0 * 4) #define IRQPOS_SM501 (1 * 4) /* INTSEL2 */ #define IRQPOS_EXTINT1 (0 * 4) #define IRQPOS_EXTINT2 (1 * 4) #define IRQPOS_EXTINT3 (2 * 4) #define IRQPOS_EXTINT4 (3 * 4) /* INTSEL3 */ #define IRQPOS_PCCPW (0 * 4) /* IDE interrupt */ #define IRQ_IDE0 evt2irq(0xa60) /* iVDR */ /* SMC interrupt */ #define SMC_IRQ evt2irq(0x300) /* SM501 interrupt */ #define SM501_IRQ evt2irq(0x200) /* interrupt pin */ #define IRQPIN_EXTINT1 0 /* IRQ0 pin */ #define IRQPIN_EXTINT2 1 /* IRQ1 pin */ #define IRQPIN_EXTINT3 2 /* IRQ2 pin */ #define IRQPIN_SMC91CX 3 /* IRQ3 pin */ #define IRQPIN_EXTINT4 4 /* IRQ4 pin */ #define IRQPIN_PCC0 5 /* IRQ5 pin */ #define IRQPIN_PCC2 6 /* IRQ6 pin */ #define IRQPIN_SM501 7 /* IRQ7 pin */ #define IRQPIN_PCCPW 7 /* IRQ7 pin */ /* arch/sh/boards/se/7780/irq.c */ void init_se7780_IRQ(void); #define __IO_PREFIX se7780 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7780_H */ PK ! ��> include/mach-se/mach/mrshpc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_SE_MRSHPC_H #define __MACH_SE_MRSHPC_H #include <linux/io.h> static inline void __init mrshpc_setup_windows(void) { if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) return; /* Not detected */ if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ } else { __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ } /* * PC-Card window open * flag == COMMON/ATTRIBUTE/IO */ /* common window open */ __raw_writew(0x8a84, MRSHPC_MW0CR1); if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) /* common mode & bus width 16bit SWAP = 1*/ __raw_writew(0x0b00, MRSHPC_MW0CR2); else /* common mode & bus width 16bit SWAP = 0*/ __raw_writew(0x0300, MRSHPC_MW0CR2); /* attribute window open */ __raw_writew(0x8a85, MRSHPC_MW1CR1); if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) /* attribute mode & bus width 16bit SWAP = 1*/ __raw_writew(0x0a00, MRSHPC_MW1CR2); else /* attribute mode & bus width 16bit SWAP = 0*/ __raw_writew(0x0200, MRSHPC_MW1CR2); /* I/O window open */ __raw_writew(0x8a86, MRSHPC_IOWCR1); __raw_writew(0x0008, MRSHPC_CDCR); /* I/O card mode */ if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) __raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ else __raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ __raw_writew(0x2000, MRSHPC_ICR); __raw_writeb(0x00, PA_MRSHPC_MW2 + 0x206); __raw_writeb(0x42, PA_MRSHPC_MW2 + 0x200); } #endif /* __MACH_SE_MRSHPC_H */ PK ! ]%��� � include/mach-se/mach/se7721.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2008 Renesas Solutions Corp. * * Hitachi UL SolutionEngine 7721 Support. */ #ifndef __ASM_SH_SE7721_H #define __ASM_SH_SE7721_H #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 2 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ #define PA_FROM 0xa1000000 /* Flash-ROM */ #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */ #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_PERIPHERAL 0xB8000000 #define PA_PCIC PA_PERIPHERAL #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define PA_LED 0xB6800000 /* 8bit LED */ #define PA_FPGA 0xB7000000 /* FPGA base address */ #define MRSHPC_IRQ0 evt2irq(0x340) #define FPGA_ILSR1 (PA_FPGA + 0x02) #define FPGA_ILSR2 (PA_FPGA + 0x03) #define FPGA_ILSR3 (PA_FPGA + 0x04) #define FPGA_ILSR4 (PA_FPGA + 0x05) #define FPGA_ILSR5 (PA_FPGA + 0x06) #define FPGA_ILSR6 (PA_FPGA + 0x07) #define FPGA_ILSR7 (PA_FPGA + 0x08) #define FPGA_ILSR8 (PA_FPGA + 0x09) void init_se7721_IRQ(void); #define __IO_PREFIX se7721 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7721_H */ PK ! �(� � include/mach-se/mach/se7724.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7724_H #define __ASM_SH_SE7724_H /* * linux/include/asm-sh/se7724.h * * Copyright (C) 2009 Renesas Solutions Corp. * * Kuninori Morimoto <morimoto.kuninori@renesas.com> * * Hitachi UL SolutionEngine 7724 Support. * * Based on se7722.h * Copyright (C) 2007 Nobuhiro Iwamatsu */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* SH Eth */ #define SH_ETH_ADDR (0xA4600000) #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0) #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8) #define PA_LED (0xba203000) /* 8bit LED */ #define IRQ_MODE (0xba200010) #define IRQ0_SR (0xba200014) #define IRQ1_SR (0xba200018) #define IRQ2_SR (0xba20001c) #define IRQ0_MR (0xba200020) #define IRQ1_MR (0xba200024) #define IRQ2_MR (0xba200028) /* IRQ */ #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #define IRQ2_IRQ evt2irq(0x640) /* Bits in IRQ012 registers */ #define SE7724_FPGA_IRQ_BASE 220 /* IRQ0 */ #define IRQ0_BASE SE7724_FPGA_IRQ_BASE #define IRQ0_KEY (IRQ0_BASE + 12) #define IRQ0_RMII (IRQ0_BASE + 13) #define IRQ0_SMC (IRQ0_BASE + 14) #define IRQ0_MASK 0x7fff #define IRQ0_END IRQ0_SMC /* IRQ1 */ #define IRQ1_BASE (IRQ0_END + 1) #define IRQ1_TS (IRQ1_BASE + 0) #define IRQ1_MASK 0x0001 #define IRQ1_END IRQ1_TS /* IRQ2 */ #define IRQ2_BASE (IRQ1_END + 1) #define IRQ2_USB0 (IRQ1_BASE + 0) #define IRQ2_USB1 (IRQ1_BASE + 1) #define IRQ2_MASK 0x0003 #define IRQ2_END IRQ2_USB1 #define SE7724_FPGA_IRQ_NR (IRQ2_END - IRQ0_BASE) /* arch/sh/boards/se/7724/irq.c */ void init_se7724_IRQ(void); #define __IO_PREFIX se7724 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7724_H */ PK ! HX%9% % include/mach-se/mach/se7206.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7206_H #define __ASM_SH_SE7206_H #define PA_SMSC 0x30000000 #define PA_MRSHPC 0x34000000 #define PA_LED 0x31400000 void init_se7206_IRQ(void); #define __IO_PREFIX se7206 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7206_H */ PK ! ]��)l l include/mach-se/mach/se7343.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HITACHI_SE7343_H #define __ASM_SH_HITACHI_SE7343_H /* * include/asm-sh/se/se7343.h * * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> * * SH-Mobile SolutionEngine 7343 support */ #include <linux/sh_intc.h> /* Box specific addresses. */ /* Area 0 */ #define PA_ROM 0x00000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ #define PA_FROM 0x00400000 /* Flash ROM */ #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ #define PA_SRAM 0x00800000 /* SRAM */ #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ /* Area 1 */ #define PA_EXT1 0x04000000 #define PA_EXT1_SIZE 0x04000000 /* Area 2 */ #define PA_EXT2 0x08000000 #define PA_EXT2_SIZE 0x04000000 /* Area 3 */ #define PA_SDRAM 0x0c000000 #define PA_SDRAM_SIZE 0x04000000 /* Area 4 */ #define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ #define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define PA_LED 0xb0C00000 /* LED */ #define LED_SHIFT 0 #define PA_DIPSW 0xb0900000 /* Dip switch 31 */ /* Area 5 */ #define PA_EXT5 0x14000000 #define PA_EXT5_SIZE 0x04000000 /* Area 6 */ #define PA_LCD1 0xb8000000 #define PA_LCD2 0xb8800000 #define PORT_PACR 0xA4050100 #define PORT_PBCR 0xA4050102 #define PORT_PCCR 0xA4050104 #define PORT_PDCR 0xA4050106 #define PORT_PECR 0xA4050108 #define PORT_PFCR 0xA405010A #define PORT_PGCR 0xA405010C #define PORT_PHCR 0xA405010E #define PORT_PJCR 0xA4050110 #define PORT_PKCR 0xA4050112 #define PORT_PLCR 0xA4050114 #define PORT_PMCR 0xA4050116 #define PORT_PNCR 0xA4050118 #define PORT_PQCR 0xA405011A #define PORT_PRCR 0xA405011C #define PORT_PSCR 0xA405011E #define PORT_PTCR 0xA4050140 #define PORT_PUCR 0xA4050142 #define PORT_PVCR 0xA4050144 #define PORT_PWCR 0xA4050146 #define PORT_PYCR 0xA4050148 #define PORT_PZCR 0xA405014A #define PORT_PSELA 0xA405014C #define PORT_PSELB 0xA405014E #define PORT_PSELC 0xA4050150 #define PORT_PSELD 0xA4050152 #define PORT_PSELE 0xA4050154 #define PORT_HIZCRA 0xA4050156 #define PORT_HIZCRB 0xA4050158 #define PORT_HIZCRC 0xA405015C #define PORT_DRVCR 0xA4050180 #define PORT_PADR 0xA4050120 #define PORT_PBDR 0xA4050122 #define PORT_PCDR 0xA4050124 #define PORT_PDDR 0xA4050126 #define PORT_PEDR 0xA4050128 #define PORT_PFDR 0xA405012A #define PORT_PGDR 0xA405012C #define PORT_PHDR 0xA405012E #define PORT_PJDR 0xA4050130 #define PORT_PKDR 0xA4050132 #define PORT_PLDR 0xA4050134 #define PORT_PMDR 0xA4050136 #define PORT_PNDR 0xA4050138 #define PORT_PQDR 0xA405013A #define PORT_PRDR 0xA405013C #define PORT_PTDR 0xA4050160 #define PORT_PUDR 0xA4050162 #define PORT_PVDR 0xA4050164 #define PORT_PWDR 0xA4050166 #define PORT_PYDR 0xA4050168 #define FPGA_IN 0xb1400000 #define FPGA_OUT 0xb1400002 #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #define IRQ4_IRQ evt2irq(0x680) #define IRQ5_IRQ evt2irq(0x6a0) #define SE7343_FPGA_IRQ_MRSHPC0 0 #define SE7343_FPGA_IRQ_MRSHPC1 1 #define SE7343_FPGA_IRQ_MRSHPC2 2 #define SE7343_FPGA_IRQ_MRSHPC3 3 #define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */ #define SE7343_FPGA_IRQ_USB 8 #define SE7343_FPGA_IRQ_UARTA 10 #define SE7343_FPGA_IRQ_UARTB 11 #define SE7343_FPGA_IRQ_NR 12 struct irq_domain; /* arch/sh/boards/se/7343/irq.c */ extern struct irq_domain *se7343_irq_domain; void init_7343se_IRQ(void); #endif /* __ASM_SH_HITACHI_SE7343_H */ PK ! ���#' ' include/mach-se/mach/se7751.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HITACHI_7751SE_H #define __ASM_SH_HITACHI_7751SE_H /* * linux/include/asm-sh/hitachi_7751se.h * * Copyright (C) 2000 Kazumoto Kojima * * Hitachi SolutionEngine support * Modified for 7751 Solution Engine by * Ian da Silva and Jeremy Siegel, 2001. */ #include <linux/sh_intc.h> /* Box specific addresses. */ #define PA_ROM 0x00000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0x01000000 /* EPROM */ #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_EXT1 0x04000000 #define PA_EXT1_SIZE 0x04000000 #define PA_EXT2 0x08000000 #define PA_EXT2_SIZE 0x04000000 #define PA_SDRAM 0x0c000000 #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0x12000000 #define PA_EXT4_SIZE 0x02000000 #define PA_EXT5 0x14000000 #define PA_EXT5_SIZE 0x04000000 #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ #define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ #define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ #define PA_LED 0xba000000 /* LED */ #define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ #define MRSHPC_MODE (PA_MRSHPC + 4) #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define BCR_ILCRA (PA_BCR + 0) #define BCR_ILCRB (PA_BCR + 2) #define BCR_ILCRC (PA_BCR + 4) #define BCR_ILCRD (PA_BCR + 6) #define BCR_ILCRE (PA_BCR + 8) #define BCR_ILCRF (PA_BCR + 10) #define BCR_ILCRG (PA_BCR + 12) #define IRQ_79C973 evt2irq(0x3a0) void init_7751se_IRQ(void); #define __IO_PREFIX sh7751se #include <asm/io_generic.h> #endif /* __ASM_SH_HITACHI_7751SE_H */ PK ! U��n n include/cpu-sh3/cpu/cache.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh3/cache.h * * Copyright (C) 1999 Niibe Yutaka */ #ifndef __ASM_CPU_SH3_CACHE_H #define __ASM_CPU_SH3_CACHE_H #define L1_CACHE_SHIFT 4 #define SH_CACHE_VALID 1 #define SH_CACHE_UPDATED 2 #define SH_CACHE_COMBINED 4 #define SH_CACHE_ASSOC 8 #define SH_CCR 0xffffffec /* Address of Cache Control Register */ #define CCR_CACHE_CE 0x01 /* Cache Enable */ #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ #define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */ #define CCR_CACHE_CF 0x08 /* Cache Flush */ #define CCR_CACHE_ORA 0x20 /* RAM mode */ #define CACHE_OC_ADDRESS_ARRAY 0xf0000000 #define CACHE_PHYSADDR_MASK 0x1ffffc00 #define CCR_CACHE_ENABLE CCR_CACHE_CE #define CCR_CACHE_INVALIDATE CCR_CACHE_CF #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7710) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) #define CCR3_REG 0xa40000b4 #define CCR_CACHE_16KB 0x00010000 #define CCR_CACHE_32KB 0x00020000 #endif #endif /* __ASM_CPU_SH3_CACHE_H */ PK ! �4�W W " include/cpu-sh3/cpu/dma-register.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * SH3 CPU-specific DMA definitions, used by both DMA drivers * * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> */ #ifndef CPU_DMA_REGISTER_H #define CPU_DMA_REGISTER_H #define CHCR_TS_LOW_MASK 0x18 #define CHCR_TS_LOW_SHIFT 3 #define CHCR_TS_HIGH_MASK 0 #define CHCR_TS_HIGH_SHIFT 0 #define DMAOR_INIT DMAOR_DME /* * The SuperH DMAC supports a number of transmit sizes, we list them here, * with their respective values as they appear in the CHCR registers. */ enum { XMIT_SZ_8BIT, XMIT_SZ_16BIT, XMIT_SZ_32BIT, XMIT_SZ_128BIT, }; /* log2(size / 8) - used to calculate number of transfers */ #define TS_SHIFT { \ [XMIT_SZ_8BIT] = 0, \ [XMIT_SZ_16BIT] = 1, \ [XMIT_SZ_32BIT] = 2, \ [XMIT_SZ_128BIT] = 4, \ } #define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) #endif PK ! ��n� � include/cpu-sh3/cpu/freq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh3/freq.h * * Copyright (C) 2002, 2003 Paul Mundt */ #ifndef __ASM_CPU_SH3_FREQ_H #define __ASM_CPU_SH3_FREQ_H #ifdef CONFIG_CPU_SUBTYPE_SH7712 #define FRQCR 0xA415FF80 #else #define FRQCR 0xffffff80 #endif #define MIN_DIVISOR_NR 0 #define MAX_DIVISOR_NR 4 #define FRQCR_CKOEN 0x0100 #define FRQCR_PLLEN 0x0080 #define FRQCR_PSTBY 0x0040 #endif /* __ASM_CPU_SH3_FREQ_H */ PK ! ���) ) include/cpu-sh3/cpu/dac.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CPU_SH3_DAC_H #define __ASM_CPU_SH3_DAC_H /* * Copyright (C) 2003 Andriy Skulysh */ #define DADR0 0xa40000a0 #define DADR1 0xa40000a2 #define DACR 0xa40000a4 #define DACR_DAOE1 0x80 #define DACR_DAOE0 0x40 #define DACR_DAE 0x20 static __inline__ void sh_dac_enable(int channel) { unsigned char v; v = __raw_readb(DACR); if(channel) v |= DACR_DAOE1; else v |= DACR_DAOE0; __raw_writeb(v,DACR); } static __inline__ void sh_dac_disable(int channel) { unsigned char v; v = __raw_readb(DACR); if(channel) v &= ~DACR_DAOE1; else v &= ~DACR_DAOE0; __raw_writeb(v,DACR); } static __inline__ void sh_dac_output(u8 value, int channel) { if(channel) __raw_writeb(value,DADR1); else __raw_writeb(value,DADR0); } #endif /* __ASM_CPU_SH3_DAC_H */ PK ! �k<�< < include/cpu-sh3/cpu/gpio.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh3/gpio.h * * Copyright (C) 2007 Markus Brunner, Mark Jonas * * Addresses for the Pin Function Controller */ #ifndef _CPU_SH3_GPIO_H #define _CPU_SH3_GPIO_H #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) /* Control registers */ #define PORT_PACR 0xA4050100UL #define PORT_PBCR 0xA4050102UL #define PORT_PCCR 0xA4050104UL #define PORT_PDCR 0xA4050106UL #define PORT_PECR 0xA4050108UL #define PORT_PFCR 0xA405010AUL #define PORT_PGCR 0xA405010CUL #define PORT_PHCR 0xA405010EUL #define PORT_PJCR 0xA4050110UL #define PORT_PKCR 0xA4050112UL #define PORT_PLCR 0xA4050114UL #define PORT_PMCR 0xA4050116UL #define PORT_PPCR 0xA4050118UL #define PORT_PRCR 0xA405011AUL #define PORT_PSCR 0xA405011CUL #define PORT_PTCR 0xA405011EUL #define PORT_PUCR 0xA4050120UL #define PORT_PVCR 0xA4050122UL /* Data registers */ #define PORT_PADR 0xA4050140UL /* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */ #define PORT_PBDR 0xA4050142UL #define PORT_PCDR 0xA4050144UL #define PORT_PDDR 0xA4050146UL #define PORT_PEDR 0xA4050148UL #define PORT_PFDR 0xA405014AUL #define PORT_PGDR 0xA405014CUL #define PORT_PHDR 0xA405014EUL #define PORT_PJDR 0xA4050150UL #define PORT_PKDR 0xA4050152UL #define PORT_PLDR 0xA4050154UL #define PORT_PMDR 0xA4050156UL #define PORT_PPDR 0xA4050158UL #define PORT_PRDR 0xA405015AUL #define PORT_PSDR 0xA405015CUL #define PORT_PTDR 0xA405015EUL #define PORT_PUDR 0xA4050160UL #define PORT_PVDR 0xA4050162UL /* Pin Select Registers */ #define PORT_PSELA 0xA4050124UL #define PORT_PSELB 0xA4050126UL #define PORT_PSELC 0xA4050128UL #define PORT_PSELD 0xA405012AUL #elif defined(CONFIG_CPU_SUBTYPE_SH7709) /* Control registers */ #define PORT_PACR 0xa4000100UL #define PORT_PBCR 0xa4000102UL #define PORT_PCCR 0xa4000104UL #define PORT_PFCR 0xa400010aUL /* Data registers */ #define PORT_PADR 0xa4000120UL #define PORT_PBDR 0xa4000122UL #define PORT_PCDR 0xa4000124UL #define PORT_PFDR 0xa400012aUL #endif #endif PK ! H,� � � include/cpu-sh3/cpu/sh7720.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7720_H__ #define __ASM_SH7720_H__ enum { /* PTA */ GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, /* PTB */ GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, /* PTC */ GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4, GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0, /* PTD */ GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, /* PTE */ GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0, /* PTF */ GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, GPIO_PTG6, /* PTG */ GPIO_PTG5, GPIO_PTG4, GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, /* PTH */ GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, /* PTJ */ GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0, /* PTK */ GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, /* PTL */ GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, GPIO_PTL3, /* PTM */ GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, /* PTP */ GPIO_PTP4, GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0, /* PTR */ GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4, GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, /* PTS */ GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, /* PTT */ GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, /* PTU */ GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, /* PTV */ GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, /* BSC */ GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28, GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24, GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20, GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16, GPIO_FN_IOIS16, GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE, GPIO_FN_CS5B_CE1A, GPIO_FN_CS6B_CE1B, GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A0, GPIO_FN_REFOUT, GPIO_FN_IRQOUT, /* LCDC */ GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14, GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12, GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10, GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8, GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6, GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4, GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2, GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0, GPIO_FN_LCD_M_DISP, GPIO_FN_LCD_CL1, GPIO_FN_LCD_CL2, GPIO_FN_LCD_DON, GPIO_FN_LCD_FLM, GPIO_FN_LCD_VEPWC, GPIO_FN_LCD_VCPWC, /* AFEIF */ GPIO_FN_AFE_RXIN, GPIO_FN_AFE_RDET, GPIO_FN_AFE_FS, GPIO_FN_AFE_TXOUT, GPIO_FN_AFE_SCLK, GPIO_FN_AFE_RLYCNT, GPIO_FN_AFE_HC1, /* IIC */ GPIO_FN_IIC_SCL, GPIO_FN_IIC_SDA, /* DAC */ GPIO_FN_DA1, GPIO_FN_DA0, /* ADC */ GPIO_FN_AN3, GPIO_FN_AN2, GPIO_FN_AN1, GPIO_FN_AN0, GPIO_FN_ADTRG, /* USB */ GPIO_FN_USB1D_RCV, GPIO_FN_USB1D_TXSE0, GPIO_FN_USB1D_TXDPLS, GPIO_FN_USB1D_DMNS, GPIO_FN_USB1D_DPLS, GPIO_FN_USB1D_SPEED, GPIO_FN_USB1D_TXENL, GPIO_FN_USB2_PWR_EN, GPIO_FN_USB1_PWR_EN_USBF_UPLUP, GPIO_FN_USB1D_SUSPEND, /* INTC */ GPIO_FN_IRQ5, GPIO_FN_IRQ4, GPIO_FN_IRQ3_IRL3, GPIO_FN_IRQ2_IRL2, GPIO_FN_IRQ1_IRL1, GPIO_FN_IRQ0_IRL0, /* PCC */ GPIO_FN_PCC_REG, GPIO_FN_PCC_DRV, GPIO_FN_PCC_BVD2, GPIO_FN_PCC_BVD1, GPIO_FN_PCC_CD2, GPIO_FN_PCC_CD1, GPIO_FN_PCC_RESET, GPIO_FN_PCC_RDY, GPIO_FN_PCC_VS2, GPIO_FN_PCC_VS1, /* HUDI */ GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_ASEBRKAK, GPIO_FN_TRST, GPIO_FN_TMS, GPIO_FN_TDO, GPIO_FN_TDI, GPIO_FN_TCK, /* DMAC */ GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_TEND1, GPIO_FN_TEND0, /* SIOF0 */ GPIO_FN_SIOF0_SYNC, GPIO_FN_SIOF0_MCLK, GPIO_FN_SIOF0_TXD, GPIO_FN_SIOF0_RXD, GPIO_FN_SIOF0_SCK, /* SIOF1 */ GPIO_FN_SIOF1_SYNC, GPIO_FN_SIOF1_MCLK, GPIO_FN_SIOF1_TXD, GPIO_FN_SIOF1_RXD, GPIO_FN_SIOF1_SCK, /* SCIF0 */ GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_SCK, /* SCIF1 */ GPIO_FN_SCIF1_TXD, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_RTS, GPIO_FN_SCIF1_CTS, GPIO_FN_SCIF1_SCK, /* TPU */ GPIO_FN_TPU_TO1, GPIO_FN_TPU_TO0, GPIO_FN_TPU_TI3B, GPIO_FN_TPU_TI3A, GPIO_FN_TPU_TI2B, GPIO_FN_TPU_TI2A, GPIO_FN_TPU_TO3, GPIO_FN_TPU_TO2, /* SIM */ GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, /* MMC */ GPIO_FN_MMC_DAT, GPIO_FN_MMC_CMD, GPIO_FN_MMC_CLK, GPIO_FN_MMC_VDDON, GPIO_FN_MMC_ODMOD, /* SYSC */ GPIO_FN_STATUS0, GPIO_FN_STATUS1, }; #endif /* __ASM_SH7720_H__ */ PK ! �lȈ= = include/cpu-sh3/cpu/serial.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __CPU_SH3_SERIAL_H #define __CPU_SH3_SERIAL_H #include <linux/serial_sci.h> extern struct plat_sci_port_ops sh770x_sci_port_ops; extern struct plat_sci_port_ops sh7710_sci_port_ops; extern struct plat_sci_port_ops sh7720_sci_port_ops; #endif /* __CPU_SH3_SERIAL_H */ PK ! zf�W ! include/cpu-sh3/cpu/mmu_context.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh3/mmu_context.h * * Copyright (C) 1999 Niibe Yutaka */ #ifndef __ASM_CPU_SH3_MMU_CONTEXT_H #define __ASM_CPU_SH3_MMU_CONTEXT_H #define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */ #define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */ #define MMU_TTB 0xFFFFFFF8 /* Translation table base register */ #define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */ #define MMUCR 0xFFFFFFE0 /* MMU Control Register */ #define MMUCR_TI (1 << 2) /* TLB flush bit */ #define MMU_TLB_ADDRESS_ARRAY 0xF2000000 #define MMU_PAGE_ASSOC_BIT 0x80 #define MMU_NTLB_ENTRIES 128 /* for 7708 */ #define MMU_NTLB_WAYS 4 #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */ #define TRA 0xffffffd0 #define EXPEVT 0xffffffd4 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7706) || \ defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) || \ defined(CONFIG_CPU_SUBTYPE_SH7710) || \ defined(CONFIG_CPU_SUBTYPE_SH7712) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ #else #define INTEVT 0xffffffd8 #endif #endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */ PK ! w"#VF F include/cpu-sh3/cpu/adc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CPU_SH3_ADC_H #define __ASM_CPU_SH3_ADC_H /* * Copyright (C) 2004 Andriy Skulysh */ #define ADDRAH 0xa4000080 #define ADDRAL 0xa4000082 #define ADDRBH 0xa4000084 #define ADDRBL 0xa4000086 #define ADDRCH 0xa4000088 #define ADDRCL 0xa400008a #define ADDRDH 0xa400008c #define ADDRDL 0xa400008e #define ADCSR 0xa4000090 #define ADCSR_ADF 0x80 #define ADCSR_ADIE 0x40 #define ADCSR_ADST 0x20 #define ADCSR_MULTI 0x10 #define ADCSR_CKS 0x08 #define ADCSR_CH_MASK 0x07 #define ADCR 0xa4000092 #endif /* __ASM_CPU_SH3_ADC_H */ PK ! �k�s� � include/cpu-sh3/cpu/dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CPU_SH3_DMA_H #define __ASM_CPU_SH3_DMA_H #include <linux/sh_intc.h> #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) || \ defined(CONFIG_CPU_SUBTYPE_SH7710) || \ defined(CONFIG_CPU_SUBTYPE_SH7712) #define SH_DMAC_BASE0 0xa4010020 #else /* SH7705/06/07/09 */ #define SH_DMAC_BASE0 0xa4000020 #endif #define DMTE0_IRQ evt2irq(0x800) #define DMTE4_IRQ evt2irq(0xb80) #endif /* __ASM_CPU_SH3_DMA_H */ PK ! �˽� � include/cpu-sh3/cpu/watchdog.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh3/watchdog.h * * Copyright (C) 2002, 2003 Paul Mundt */ #ifndef __ASM_CPU_SH3_WATCHDOG_H #define __ASM_CPU_SH3_WATCHDOG_H /* Register definitions */ #define WTCNT 0xffffff84 #define WTCSR 0xffffff86 /* Bit definitions */ #define WTCSR_TME 0x80 #define WTCSR_WT 0x40 #define WTCSR_RSTS 0x20 #define WTCSR_WOVF 0x10 #define WTCSR_IOVF 0x08 #endif /* __ASM_CPU_SH3_WATCHDOG_H */ PK ! �c˥ � # include/mach-kfr2r09/mach/kfr2r09.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_KFR2R09_H #define __ASM_SH_KFR2R09_H #include <video/sh_mobile_lcdc.h> #if defined(CONFIG_FB_SH_MOBILE_LCDC) || defined(CONFIG_FB_SH_MOBILE_LCDC_MODULE) int kfr2r09_lcd_setup(void *sys_ops_handle, struct sh_mobile_lcdc_sys_bus_ops *sys_ops); void kfr2r09_lcd_start(void *sys_ops_handle, struct sh_mobile_lcdc_sys_bus_ops *sys_ops); #else static int kfr2r09_lcd_setup(void *sys_ops_handle, struct sh_mobile_lcdc_sys_bus_ops *sys_ops) { return -ENODEV; } static void kfr2r09_lcd_start(void *sys_ops_handle, struct sh_mobile_lcdc_sys_bus_ops *sys_ops) { } #endif #endif /* __ASM_SH_KFR2R09_H */ PK ! �-�8 8 $ include/mach-kfr2r09/mach/romimage.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifdef __ASSEMBLY__ /* kfr2r09 board specific boot code: * converts the "partner-jet-script.txt" script into assembly * the assembly code is the first code to be executed in the romImage */ #include <asm/romimage-macros.h> #include <mach/partner-jet-setup.txt> /* execute icbi after enabling cache */ mov.l 1f, r0 icbi @r0 /* jump to cached area */ mova 2f, r0 jmp @r0 nop .align 2 1: .long 0xa8000000 2: #else /* __ASSEMBLY__ */ static inline void mmcif_update_progress(int nr) { } #endif /* __ASSEMBLY__ */ PK ! 9PK�B B / include/mach-kfr2r09/mach/partner-jet-setup.txtnu �[��� LIST "SPDX-License-Identifier: GPL-2.0" LIST "partner-jet-setup.txt - 20090729 Magnus Damm" LIST "set up enough of the kfr2r09 hardware to boot the kernel" LIST "zImage (RAM boot)" LIST "This script can be used to boot the kernel from RAM via JTAG:" LIST "> < partner-jet-setup.txt" LIST "> RD zImage, 0xa8800000" LIST "> G=0xa8800000" LIST "romImage (Flash boot)" LIST "Use the following command to burn the zImage to flash via JTAG:" LIST "> RD romImage, 0" LIST "--------------------------------" LIST "disable watchdog" EW 0xa4520004, 0xa507 LIST "invalidate instruction cache" ED 0xff00001c, 0x00000800 LIST "invalidate TLBs" ED 0xff000010, 0x00000004 LIST "select mode for cs5 + cs6" ED 0xff800020, 0xa5a50001 ED 0xfec10000, 0x0000001b LIST "setup clocks" LIST "The PLL and FLL values are updated here for the optimal" LIST "RF frequency and improved reception sensitivity." ED 0xa4150004, 0x00000050 ED 0xa4150000, 0x91053508 WAIT 1 ED 0xa4150050, 0x00000340 ED 0xa4150024, 0x00005000 LIST "setup pins" EB 0xa4050120, 0x00 EB 0xa4050122, 0x00 EB 0xa4050124, 0x00 EB 0xa4050126, 0x00 EB 0xa4050128, 0xA0 EB 0xa405012A, 0x10 EB 0xa405012C, 0x00 EB 0xa405012E, 0x00 EB 0xa4050130, 0x00 EB 0xa4050132, 0x00 EB 0xa4050134, 0x01 EB 0xa4050136, 0x40 EB 0xa4050138, 0x00 EB 0xa405013A, 0x00 EB 0xa405013C, 0x00 EB 0xa405013E, 0x20 EB 0xa4050160, 0x00 EB 0xa4050162, 0x40 EB 0xa4050164, 0x03 EB 0xa4050166, 0x00 EB 0xa4050168, 0x00 EB 0xa405016A, 0x00 EB 0xa405016C, 0x00 EW 0xa405014E, 0x5660 EW 0xa4050150, 0x0145 EW 0xa4050152, 0x1550 EW 0xa4050154, 0x0200 EW 0xa4050156, 0x0040 EW 0xa4050158, 0x0000 EW 0xa405015a, 0x0000 EW 0xa405015c, 0x0000 EW 0xa405015e, 0x0000 EW 0xa4050180, 0x0000 EW 0xa4050182, 0x8002 EW 0xa4050184, 0x0000 EW 0xa405018a, 0x9991 EW 0xa405018c, 0x8011 EW 0xa405018e, 0x9550 EW 0xa4050100, 0x0000 EW 0xa4050102, 0x5540 EW 0xa4050104, 0x0000 EW 0xa4050106, 0x0000 EW 0xa4050108, 0x4550 EW 0xa405010a, 0x0130 EW 0xa405010c, 0x0555 EW 0xa405010e, 0x0000 EW 0xa4050110, 0x0000 EW 0xa4050112, 0xAAA8 EW 0xa4050114, 0x8305 EW 0xa4050116, 0x10F0 EW 0xa4050118, 0x0F50 EW 0xa405011a, 0x0000 EW 0xa405011c, 0x0000 EW 0xa405011e, 0x0555 EW 0xa4050140, 0x0000 EW 0xa4050142, 0x5141 EW 0xa4050144, 0x5005 EW 0xa4050146, 0xAAA9 EW 0xa4050148, 0xFAA9 EW 0xa405014a, 0x3000 EW 0xa405014c, 0x0000 LIST "setup sdram" ED 0xFD000108, 0x40000301 ED 0xFD000020, 0x011B0002 ED 0xFD000030, 0x03060E02 ED 0xFD000034, 0x01020102 ED 0xFD000038, 0x01090406 ED 0xFD000008, 0x00000004 ED 0xFD000040, 0x00000001 ED 0xFD000040, 0x00000000 ED 0xFD000018, 0x00000001 WAIT 1 ED 0xFD000014, 0x00000002 ED 0xFD000060, 0x00000032 ED 0xFD000060, 0x00020000 ED 0xFD000014, 0x00000004 ED 0xFD000014, 0x00000004 ED 0xFD000010, 0x00000001 ED 0xFD000044, 0x000004AF ED 0xFD000048, 0x20CF0037 LIST "read 16 bytes from sdram" DD 0xa8000000, 0xa8000000, 1 DD 0xa8000004, 0xa8000004, 1 DD 0xa8000008, 0xa8000008, 1 DD 0xa800000c, 0xa800000c, 1 ED 0xFD000014, 0x00000002 ED 0xFD000014, 0x00000004 ED 0xFD000108, 0x40000300 ED 0xFD000040, 0x00010000 LIST "write to internal ram" ED 0xfd8007fc, 0 LIST "setup cache" ED 0xff00001c, 0x0000090b PK ! �Y� include/cpu-sh4/cpu/cache.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh4/cache.h * * Copyright (C) 1999 Niibe Yutaka */ #ifndef __ASM_CPU_SH4_CACHE_H #define __ASM_CPU_SH4_CACHE_H #define L1_CACHE_SHIFT 5 #define SH_CACHE_VALID 1 #define SH_CACHE_UPDATED 2 #define SH_CACHE_COMBINED 4 #define SH_CACHE_ASSOC 8 #define SH_CCR 0xff00001c /* Address of Cache Control Register */ #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ #define CCR_CACHE_OCI 0x0008 /* OC Invalidate */ #define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */ #define CCR_CACHE_OIX 0x0080 /* OC Index Enable */ #define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */ #define CCR_CACHE_ICI 0x0800 /* IC Invalidate */ #define CCR_CACHE_IIX 0x8000 /* IC Index Enable */ #ifndef CONFIG_CPU_SH4A #define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */ #endif /* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */ #define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE) #define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI) #define CACHE_IC_ADDRESS_ARRAY 0xf0000000 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 #define RAMCR 0xFF000074 #endif /* __ASM_CPU_SH4_CACHE_H */ PK ! h��� � include/cpu-sh4/cpu/shx3.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __CPU_SHX3_H #define __CPU_SHX3_H enum { /* PA */ GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4, GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0, /* PB */ GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0, /* PC */ GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, /* PD */ GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, /* PE */ GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, /* PF */ GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, /* PG */ GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4, GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0, /* PH */ GPIO_PH5, GPIO_PH4, GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0, /* SCIF */ GPIO_FN_SCK3, GPIO_FN_TXD3, GPIO_FN_RXD3, GPIO_FN_SCK2, GPIO_FN_TXD2, GPIO_FN_RXD2, GPIO_FN_SCK1, GPIO_FN_TXD1, GPIO_FN_RXD1, GPIO_FN_SCK0, GPIO_FN_TXD0, GPIO_FN_RXD0, /* LBSC */ GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28, GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24, GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20, GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16, GPIO_FN_WE3, GPIO_FN_WE2, GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CLKOUTENB, GPIO_FN_BREQ, GPIO_FN_IOIS16, GPIO_FN_CE2B, GPIO_FN_CE2A, GPIO_FN_BACK, /* DMAC */ GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_DRAK0, GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DRAK1, GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DRAK2, GPIO_FN_DACK3, GPIO_FN_DREQ3, GPIO_FN_DRAK3, /* INTC */ GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0, GPIO_FN_IRL3, GPIO_FN_IRL2, GPIO_FN_IRL1, GPIO_FN_IRL0, GPIO_FN_IRQOUT, GPIO_FN_STATUS1, GPIO_FN_STATUS0, }; #endif /* __CPU_SHX3_H */ PK ! ��E�� � " include/cpu-sh4/cpu/dma-register.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * SH4 CPU-specific DMA definitions, used by both DMA drivers * * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> */ #ifndef CPU_DMA_REGISTER_H #define CPU_DMA_REGISTER_H /* SH7751/7760/7780 DMA IRQ sources */ #ifdef CONFIG_CPU_SH4A #define DMAOR_INIT DMAOR_DME #if defined(CONFIG_CPU_SUBTYPE_SH7343) #define CHCR_TS_LOW_MASK 0x00000018 #define CHCR_TS_LOW_SHIFT 3 #define CHCR_TS_HIGH_MASK 0 #define CHCR_TS_HIGH_SHIFT 0 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \ defined(CONFIG_CPU_SUBTYPE_SH7723) || \ defined(CONFIG_CPU_SUBTYPE_SH7724) || \ defined(CONFIG_CPU_SUBTYPE_SH7730) || \ defined(CONFIG_CPU_SUBTYPE_SH7786) #define CHCR_TS_LOW_MASK 0x00000018 #define CHCR_TS_LOW_SHIFT 3 #define CHCR_TS_HIGH_MASK 0x00300000 #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) #define CHCR_TS_LOW_MASK 0x00000018 #define CHCR_TS_LOW_SHIFT 3 #define CHCR_TS_HIGH_MASK 0x00100000 #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ #endif /* Transmit sizes and respective CHCR register values */ enum { XMIT_SZ_8BIT = 0, XMIT_SZ_16BIT = 1, XMIT_SZ_32BIT = 2, XMIT_SZ_64BIT = 7, XMIT_SZ_128BIT = 3, XMIT_SZ_256BIT = 4, XMIT_SZ_128BIT_BLK = 0xb, XMIT_SZ_256BIT_BLK = 0xc, }; /* log2(size / 8) - used to calculate number of transfers */ #define TS_SHIFT { \ [XMIT_SZ_8BIT] = 0, \ [XMIT_SZ_16BIT] = 1, \ [XMIT_SZ_32BIT] = 2, \ [XMIT_SZ_64BIT] = 3, \ [XMIT_SZ_128BIT] = 4, \ [XMIT_SZ_256BIT] = 5, \ [XMIT_SZ_128BIT_BLK] = 4, \ [XMIT_SZ_256BIT_BLK] = 5, \ } #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \ (((i) & 0xc) << CHCR_TS_HIGH_SHIFT)) #else /* CONFIG_CPU_SH4A */ #define DMAOR_INIT (0x8000 | DMAOR_DME) #define CHCR_TS_LOW_MASK 0x70 #define CHCR_TS_LOW_SHIFT 4 #define CHCR_TS_HIGH_MASK 0 #define CHCR_TS_HIGH_SHIFT 0 /* Transmit sizes and respective CHCR register values */ enum { XMIT_SZ_8BIT = 1, XMIT_SZ_16BIT = 2, XMIT_SZ_32BIT = 3, XMIT_SZ_64BIT = 0, XMIT_SZ_256BIT = 4, }; /* log2(size / 8) - used to calculate number of transfers */ #define TS_SHIFT { \ [XMIT_SZ_8BIT] = 0, \ [XMIT_SZ_16BIT] = 1, \ [XMIT_SZ_32BIT] = 2, \ [XMIT_SZ_64BIT] = 3, \ [XMIT_SZ_256BIT] = 5, \ } #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) #endif /* CONFIG_CPU_SH4A */ #endif PK ! ���� � include/cpu-sh4/cpu/freq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh4/freq.h * * Copyright (C) 2002, 2003 Paul Mundt */ #ifndef __ASM_CPU_SH4_FREQ_H #define __ASM_CPU_SH4_FREQ_H #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \ defined(CONFIG_CPU_SUBTYPE_SH7723) || \ defined(CONFIG_CPU_SUBTYPE_SH7343) || \ defined(CONFIG_CPU_SUBTYPE_SH7366) #define FRQCR 0xa4150000 #define VCLKCR 0xa4150004 #define SCLKACR 0xa4150008 #define SCLKBCR 0xa415000c #define IrDACLKCR 0xa4150010 #define MSTPCR0 0xa4150030 #define MSTPCR1 0xa4150034 #define MSTPCR2 0xa4150038 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) #define FRQCR 0xffc80000 #define OSCCR 0xffc80018 #define PLLCR 0xffc80024 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) #define FRQCR 0xffc80000 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) #define FRQCRA 0xa4150000 #define FRQCRB 0xa4150004 #define VCLKCR 0xa4150048 #define FCLKACR 0xa4150008 #define FCLKBCR 0xa415000c #define FRQCR FRQCRA #define SCLKACR FCLKACR #define SCLKBCR FCLKBCR #define FCLKACR 0xa4150008 #define FCLKBCR 0xa415000c #define IrDACLKCR 0xa4150018 #define MSTPCR0 0xa4150030 #define MSTPCR1 0xa4150034 #define MSTPCR2 0xa4150038 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) #define FRQCR0 0xffc80000 #define FRQCR2 0xffc80008 #define FRQMR1 0xffc80014 #define FRQMR2 0xffc80018 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) #define FRQCR0 0xffc80000 #define FRQCR1 0xffc80004 #define FRQMR1 0xffc80014 #elif defined(CONFIG_CPU_SUBTYPE_SH7786) #define FRQCR0 0xffc40000 #define FRQCR1 0xffc40004 #define FRQMR1 0xffc40014 #elif defined(CONFIG_CPU_SUBTYPE_SHX3) #define FRQCR0 0xffc00000 #define FRQCR1 0xffc00004 #define FRQMR1 0xffc00014 #else #define FRQCR 0xffc00000 #define FRQCR_PSTBY 0x0200 #define FRQCR_PLLEN 0x0400 #define FRQCR_CKOEN 0x0800 #endif #define MIN_DIVISOR_NR 0 #define MAX_DIVISOR_NR 3 #endif /* __ASM_CPU_SH4_FREQ_H */ PK ! 29��a a include/cpu-sh4/cpu/sh7785.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7785_H__ #define __ASM_SH7785_H__ /* Boot Mode Pins: * * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1] * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1] * MODE2: CPG - Reserved (L: Normal operation) * MODE3: CPG - Reserved (L: Normal operation) * MODE4: CPG - Initial PLL setting (72x/36x) * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8] * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9] * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3] * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31] * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30] * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal) * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave) * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU) * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit) * MODE14: Reserved (H: Normal operation) * * More information in sh7785 manual Rev.1.00, page 1628. */ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function * GPIO_Pxx - GPIO mapped to real I/O pin on CPU */ enum { /* PA */ GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4, GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0, /* PB */ GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0, /* PC */ GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, /* PD */ GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, /* PE */ GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, /* PF */ GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, /* PG */ GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4, GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0, /* PH */ GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4, GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0, /* PJ */ GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4, GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0, /* PK */ GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4, GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0, /* PL */ GPIO_PL7, GPIO_PL6, GPIO_PL5, GPIO_PL4, GPIO_PL3, GPIO_PL2, GPIO_PL1, GPIO_PL0, /* PM */ GPIO_PM1, GPIO_PM0, /* PN */ GPIO_PN7, GPIO_PN6, GPIO_PN5, GPIO_PN4, GPIO_PN3, GPIO_PN2, GPIO_PN1, GPIO_PN0, /* PP */ GPIO_PP5, GPIO_PP4, GPIO_PP3, GPIO_PP2, GPIO_PP1, GPIO_PP0, /* PQ */ GPIO_PQ4, GPIO_PQ3, GPIO_PQ2, GPIO_PQ1, GPIO_PQ0, /* PR */ GPIO_PR3, GPIO_PR2, GPIO_PR1, GPIO_PR0, GPIO_FN_D63_AD31, GPIO_FN_D62_AD30, GPIO_FN_D61_AD29, GPIO_FN_D60_AD28, GPIO_FN_D59_AD27, GPIO_FN_D58_AD26, GPIO_FN_D57_AD25, GPIO_FN_D56_AD24, GPIO_FN_D55_AD23, GPIO_FN_D54_AD22, GPIO_FN_D53_AD21, GPIO_FN_D52_AD20, GPIO_FN_D51_AD19, GPIO_FN_D50_AD18, GPIO_FN_D49_AD17_DB5, GPIO_FN_D48_AD16_DB4, GPIO_FN_D47_AD15_DB3, GPIO_FN_D46_AD14_DB2, GPIO_FN_D45_AD13_DB1, GPIO_FN_D44_AD12_DB0, GPIO_FN_D43_AD11_DG5, GPIO_FN_D42_AD10_DG4, GPIO_FN_D41_AD9_DG3, GPIO_FN_D40_AD8_DG2, GPIO_FN_D39_AD7_DG1, GPIO_FN_D38_AD6_DG0, GPIO_FN_D37_AD5_DR5, GPIO_FN_D36_AD4_DR4, GPIO_FN_D35_AD3_DR3, GPIO_FN_D34_AD2_DR2, GPIO_FN_D33_AD1_DR1, GPIO_FN_D32_AD0_DR0, GPIO_FN_REQ1, GPIO_FN_REQ2, GPIO_FN_REQ3, GPIO_FN_GNT1, GPIO_FN_GNT2, GPIO_FN_GNT3, GPIO_FN_MMCCLK, GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28, GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24, GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20, GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16, GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD, GPIO_FN_SCIF0_CTS, GPIO_FN_INTD, GPIO_FN_FCE, GPIO_FN_SCIF0_RTS, GPIO_FN_HSPI_CS, GPIO_FN_FSE, GPIO_FN_SCIF0_SCK, GPIO_FN_HSPI_CLK, GPIO_FN_FRE, GPIO_FN_SCIF0_RXD, GPIO_FN_HSPI_RX, GPIO_FN_FRB, GPIO_FN_SCIF0_TXD, GPIO_FN_HSPI_TX, GPIO_FN_FWE, GPIO_FN_SCIF5_TXD, GPIO_FN_HAC1_SYNC, GPIO_FN_SSI1_WS, GPIO_FN_SIOF_TXD_PJ, GPIO_FN_HAC0_SDOUT, GPIO_FN_SSI0_SDATA, GPIO_FN_SIOF_RXD_PJ, GPIO_FN_HAC0_SDIN, GPIO_FN_SSI0_SCK, GPIO_FN_SIOF_SYNC_PJ, GPIO_FN_HAC0_SYNC, GPIO_FN_SSI0_WS, GPIO_FN_SIOF_MCLK_PJ, GPIO_FN_HAC_RES, GPIO_FN_SIOF_SCK_PJ, GPIO_FN_HAC0_BITCLK, GPIO_FN_SSI0_CLK, GPIO_FN_HAC1_BITCLK, GPIO_FN_SSI1_CLK, GPIO_FN_TCLK, GPIO_FN_IOIS16, GPIO_FN_STATUS0, GPIO_FN_DRAK0_PK3, GPIO_FN_STATUS1, GPIO_FN_DRAK1_PK2, GPIO_FN_DACK2, GPIO_FN_SCIF2_TXD, GPIO_FN_MMCCMD, GPIO_FN_SIOF_TXD_PK, GPIO_FN_DACK3, GPIO_FN_SCIF2_SCK, GPIO_FN_MMCDAT, GPIO_FN_SIOF_SCK_PK, GPIO_FN_DREQ0, GPIO_FN_DREQ1, GPIO_FN_DRAK0_PK1, GPIO_FN_DRAK1_PK0, GPIO_FN_DREQ2, GPIO_FN_INTB, GPIO_FN_DREQ3, GPIO_FN_INTC, GPIO_FN_DRAK2, GPIO_FN_CE2A, GPIO_FN_IRL4, GPIO_FN_FD4, GPIO_FN_IRL5, GPIO_FN_FD5, GPIO_FN_IRL6, GPIO_FN_FD6, GPIO_FN_IRL7, GPIO_FN_FD7, GPIO_FN_DRAK3, GPIO_FN_CE2B, GPIO_FN_BREQ_BSACK, GPIO_FN_BACK_BSREQ, GPIO_FN_SCIF5_RXD, GPIO_FN_HAC1_SDIN, GPIO_FN_SSI1_SCK, GPIO_FN_SCIF5_SCK, GPIO_FN_HAC1_SDOUT, GPIO_FN_SSI1_SDATA, GPIO_FN_SCIF3_TXD, GPIO_FN_FCLE, GPIO_FN_SCIF3_RXD, GPIO_FN_FALE, GPIO_FN_SCIF3_SCK, GPIO_FN_FD0, GPIO_FN_SCIF4_TXD, GPIO_FN_FD1, GPIO_FN_SCIF4_RXD, GPIO_FN_FD2, GPIO_FN_SCIF4_SCK, GPIO_FN_FD3, GPIO_FN_DEVSEL_DCLKOUT, GPIO_FN_STOP_CDE, GPIO_FN_LOCK_ODDF, GPIO_FN_TRDY_DISPL, GPIO_FN_IRDY_HSYNC, GPIO_FN_PCIFRAME_VSYNC, GPIO_FN_INTA, GPIO_FN_GNT0_GNTIN, GPIO_FN_REQ0_REQOUT, GPIO_FN_PERR, GPIO_FN_SERR, GPIO_FN_WE7_CBE3, GPIO_FN_WE6_CBE2, GPIO_FN_WE5_CBE1, GPIO_FN_WE4_CBE0, GPIO_FN_SCIF2_RXD, GPIO_FN_SIOF_RXD, GPIO_FN_MRESETOUT, GPIO_FN_IRQOUT, }; #endif /* __ASM_SH7785_H__ */ PK ! �U� ! include/cpu-sh4/cpu/mmu_context.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh4/mmu_context.h * * Copyright (C) 1999 Niibe Yutaka */ #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H #define __ASM_CPU_SH4_MMU_CONTEXT_H #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ #define MMU_TTB 0xFF000008 /* Translation table base register */ #define MMU_TEA 0xFF00000C /* TLB Exception Address */ #define MMU_PTEA 0xFF000034 /* PTE assistance register */ #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ #define MMUCR 0xFF000010 /* MMU Control Register */ #define MMU_TLB_ENTRY_SHIFT 8 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 #define MMU_ITLB_DATA_ARRAY 0xF3000000 #define MMU_ITLB_DATA_ARRAY2 0xF3800000 #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 #define MMU_UTLB_DATA_ARRAY 0xF7000000 #define MMU_UTLB_DATA_ARRAY2 0xF7800000 #define MMU_PAGE_ASSOC_BIT 0x80 #ifdef CONFIG_MMU #define MMUCR_AT (1 << 0) #else #define MMUCR_AT (0) #endif #define MMUCR_TI (1 << 2) #define MMUCR_URB 0x00FC0000 #define MMUCR_URB_SHIFT 18 #define MMUCR_URB_NENTRIES 64 #define MMUCR_URC 0x0000FC00 #define MMUCR_URC_SHIFT 10 #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) #define MMUCR_SE (1 << 4) #else #define MMUCR_SE (0) #endif #ifdef CONFIG_CPU_HAS_PTEAEX #define MMUCR_AEX (1 << 6) #else #define MMUCR_AEX (0) #endif #ifdef CONFIG_X2TLB #define MMUCR_ME (1 << 7) #else #define MMUCR_ME (0) #endif #ifdef CONFIG_SH_STORE_QUEUES #define MMUCR_SQMD (1 << 9) #else #define MMUCR_SQMD (0) #endif #define MMU_NTLB_ENTRIES 64 #define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \ MMUCR_ME | MMUCR_SE | MMUCR_AEX) #define TRA 0xff000020 #define EXPEVT 0xff000024 #define INTEVT 0xff000028 #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ PK ! ����# �# include/cpu-sh4/cpu/sh7757.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7757_H__ #define __ASM_SH7757_H__ enum { /* PTA */ GPIO_PTA0, GPIO_PTA1, GPIO_PTA2, GPIO_PTA3, GPIO_PTA4, GPIO_PTA5, GPIO_PTA6, GPIO_PTA7, /* PTB */ GPIO_PTB0, GPIO_PTB1, GPIO_PTB2, GPIO_PTB3, GPIO_PTB4, GPIO_PTB5, GPIO_PTB6, GPIO_PTB7, /* PTC */ GPIO_PTC0, GPIO_PTC1, GPIO_PTC2, GPIO_PTC3, GPIO_PTC4, GPIO_PTC5, GPIO_PTC6, GPIO_PTC7, /* PTD */ GPIO_PTD0, GPIO_PTD1, GPIO_PTD2, GPIO_PTD3, GPIO_PTD4, GPIO_PTD5, GPIO_PTD6, GPIO_PTD7, /* PTE */ GPIO_PTE0, GPIO_PTE1, GPIO_PTE2, GPIO_PTE3, GPIO_PTE4, GPIO_PTE5, GPIO_PTE6, GPIO_PTE7, /* PTF */ GPIO_PTF0, GPIO_PTF1, GPIO_PTF2, GPIO_PTF3, GPIO_PTF4, GPIO_PTF5, GPIO_PTF6, GPIO_PTF7, /* PTG */ GPIO_PTG0, GPIO_PTG1, GPIO_PTG2, GPIO_PTG3, GPIO_PTG4, GPIO_PTG5, GPIO_PTG6, GPIO_PTG7, /* PTH */ GPIO_PTH0, GPIO_PTH1, GPIO_PTH2, GPIO_PTH3, GPIO_PTH4, GPIO_PTH5, GPIO_PTH6, GPIO_PTH7, /* PTI */ GPIO_PTI0, GPIO_PTI1, GPIO_PTI2, GPIO_PTI3, GPIO_PTI4, GPIO_PTI5, GPIO_PTI6, GPIO_PTI7, /* PTJ */ GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3, GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, /* PTK */ GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3, GPIO_PTK4, GPIO_PTK5, GPIO_PTK6, GPIO_PTK7, /* PTL */ GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3, GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, /* PTM */ GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3, GPIO_PTM4, GPIO_PTM5, GPIO_PTM6, GPIO_PTM7, /* PTN */ GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3, GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, /* PTO */ GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3, GPIO_PTO4, GPIO_PTO5, GPIO_PTO6, GPIO_PTO7, /* PTP */ GPIO_PTP0, GPIO_PTP1, GPIO_PTP2, GPIO_PTP3, GPIO_PTP4, GPIO_PTP5, GPIO_PTP6, GPIO_PTP7, /* PTQ */ GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3, GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, /* PTR */ GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3, GPIO_PTR4, GPIO_PTR5, GPIO_PTR6, GPIO_PTR7, /* PTS */ GPIO_PTS0, GPIO_PTS1, GPIO_PTS2, GPIO_PTS3, GPIO_PTS4, GPIO_PTS5, GPIO_PTS6, GPIO_PTS7, /* PTT */ GPIO_PTT0, GPIO_PTT1, GPIO_PTT2, GPIO_PTT3, GPIO_PTT4, GPIO_PTT5, GPIO_PTT6, GPIO_PTT7, /* PTU */ GPIO_PTU0, GPIO_PTU1, GPIO_PTU2, GPIO_PTU3, GPIO_PTU4, GPIO_PTU5, GPIO_PTU6, GPIO_PTU7, /* PTV */ GPIO_PTV0, GPIO_PTV1, GPIO_PTV2, GPIO_PTV3, GPIO_PTV4, GPIO_PTV5, GPIO_PTV6, GPIO_PTV7, /* PTW */ GPIO_PTW0, GPIO_PTW1, GPIO_PTW2, GPIO_PTW3, GPIO_PTW4, GPIO_PTW5, GPIO_PTW6, GPIO_PTW7, /* PTX */ GPIO_PTX0, GPIO_PTX1, GPIO_PTX2, GPIO_PTX3, GPIO_PTX4, GPIO_PTX5, GPIO_PTX6, GPIO_PTX7, /* PTY */ GPIO_PTY0, GPIO_PTY1, GPIO_PTY2, GPIO_PTY3, GPIO_PTY4, GPIO_PTY5, GPIO_PTY6, GPIO_PTY7, /* PTZ */ GPIO_PTZ0, GPIO_PTZ1, GPIO_PTZ2, GPIO_PTZ3, GPIO_PTZ4, GPIO_PTZ5, GPIO_PTZ6, GPIO_PTZ7, /* PTA (mobule: LBSC, RGMII) */ GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY, GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO, GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO, /* PTB (mobule: INTC, ONFI, TMU) */ GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12, GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8, GPIO_FN_ON_NRE, GPIO_FN_ON_NWE, GPIO_FN_ON_NWP, GPIO_FN_ON_NCE0, GPIO_FN_ON_R_B0, GPIO_FN_ON_ALE, GPIO_FN_ON_CLE, GPIO_FN_TCLK, /* PTC (mobule: IRQ, PWMU) */ GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4, GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0, GPIO_FN_PWMU0, GPIO_FN_PWMU1, GPIO_FN_PWMU2, GPIO_FN_PWMU3, GPIO_FN_PWMU4, GPIO_FN_PWMU5, /* PTD (mobule: SPI0, DMAC) */ GPIO_FN_SP0_MOSI, GPIO_FN_SP0_MISO, GPIO_FN_SP0_SCK, GPIO_FN_SP0_SCK_FB, GPIO_FN_SP0_SS0, GPIO_FN_SP0_SS1, GPIO_FN_SP0_SS2, GPIO_FN_SP0_SS3, GPIO_FN_DREQ0, GPIO_FN_DACK0, GPIO_FN_TEND0, /* PTE (mobule: RMII) */ GPIO_FN_RMII0_CRS_DV, GPIO_FN_RMII0_TXD1, GPIO_FN_RMII0_TXD0, GPIO_FN_RMII0_TXEN, GPIO_FN_RMII0_REFCLK, GPIO_FN_RMII0_RXD1, GPIO_FN_RMII0_RXD0, GPIO_FN_RMII0_RX_ER, /* PTF (mobule: RMII, SerMux) */ GPIO_FN_RMII1_CRS_DV, GPIO_FN_RMII1_TXD1, GPIO_FN_RMII1_TXD0, GPIO_FN_RMII1_TXEN, GPIO_FN_RMII1_REFCLK, GPIO_FN_RMII1_RXD1, GPIO_FN_RMII1_RXD0, GPIO_FN_RMII1_RX_ER, GPIO_FN_RAC_RI, /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ GPIO_FN_BOOTFMS, GPIO_FN_BOOTWP, GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_SERIRQ, GPIO_FN_WDTOVF, GPIO_FN_LPCPD, GPIO_FN_LDRQ, GPIO_FN_MMCCLK, GPIO_FN_MMCCMD, /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO, GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB, GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1, GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_TEND1, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0, /* PTI (mobule: LBSC, SDHI) */ GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD, GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0, /* PTJ (mobule: SCIF234) */ GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3, GPIO_FN_RTS4, GPIO_FN_RXD4, GPIO_FN_TXD4, /* PTK (mobule: SERMUX, LBSC, SCIF) */ GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS, GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR, GPIO_FN_COM2_DCD, GPIO_FN_CLKOUT, GPIO_FN_SCK2, GPIO_FN_SCK4, GPIO_FN_SCK3, /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ GPIO_FN_RAC_RXD, GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS, GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, GPIO_FN_RAC_DCD, GPIO_FN_RAC_TXD, GPIO_FN_RXD2, GPIO_FN_CS5, GPIO_FN_CS6, GPIO_FN_AUDSYNC, GPIO_FN_AUDCK, GPIO_FN_TXD2, /* PTM (mobule: LBSC, IIC) */ GPIO_FN_CS4, GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_CS0, GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7, /* PTN (mobule: USB, JMC, SGPIO, WDT) */ GPIO_FN_VBUS_EN, GPIO_FN_VBUS_OC, GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI, GPIO_FN_JMCTRST, GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO, GPIO_FN_SUB_CLKIN, /* PTO (mobule: SGPIO, SerMux) */ GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO, GPIO_FN_SGPIO2_CLK, GPIO_FN_SGPIO2_LOAD, GPIO_FN_SGPIO2_DI, GPIO_FN_SGPIO2_DO, GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD, GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS, /* PTQ (mobule: LPC) */ GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0, GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK, /* PTR (mobule: GRA, IIC) */ GPIO_FN_DDC3, GPIO_FN_DDC2, GPIO_FN_SDA2, GPIO_FN_SCL2, GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0, GPIO_FN_SDA8, GPIO_FN_SCL8, /* PTS (mobule: GRA, IIC) */ GPIO_FN_DDC1, GPIO_FN_DDC0, GPIO_FN_SDA5, GPIO_FN_SCL5, GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3, GPIO_FN_SDA9, GPIO_FN_SCL9, /* PTT (mobule: PWMX, AUD) */ GPIO_FN_PWMX7, GPIO_FN_PWMX6, GPIO_FN_PWMX5, GPIO_FN_PWMX4, GPIO_FN_PWMX3, GPIO_FN_PWMX2, GPIO_FN_PWMX1, GPIO_FN_PWMX0, GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, GPIO_FN_STATUS1, GPIO_FN_STATUS0, /* PTU (mobule: LPC, APM) */ GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4, GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0, GPIO_FN_APMONCTL_O, GPIO_FN_APMPWBTOUT_O, GPIO_FN_APMSCI_O, GPIO_FN_APMVDDON, GPIO_FN_APMSLPBTN, GPIO_FN_APMPWRBTN, GPIO_FN_APMS5N, GPIO_FN_APMS3N, /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, GPIO_FN_COM2_RI, GPIO_FN_R_SPI_MOSI, GPIO_FN_R_SPI_MISO, GPIO_FN_R_SPI_RSPCK, GPIO_FN_R_SPI_SSL0, GPIO_FN_R_SPI_SSL1, GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_VBIOS_DI, GPIO_FN_VBIOS_DO, GPIO_FN_VBIOS_CLK, GPIO_FN_VBIOS_CS, /* PTW (mobule: LBSC, EVC, SCIF) */ GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, GPIO_FN_EVENT5, GPIO_FN_EVENT4, GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0, GPIO_FN_CTS4, GPIO_FN_CTS2, /* PTX (mobule: LBSC, SCIF, SIM) */ GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, GPIO_FN_RTS2, GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, /* PTY (mobule: LBSC) */ GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, /* PTZ (mobule: eMMC, ONFI) */ GPIO_FN_MMCDAT7, GPIO_FN_MMCDAT6, GPIO_FN_MMCDAT5, GPIO_FN_MMCDAT4, GPIO_FN_MMCDAT3, GPIO_FN_MMCDAT2, GPIO_FN_MMCDAT1, GPIO_FN_MMCDAT0, GPIO_FN_ON_DQ7, GPIO_FN_ON_DQ6, GPIO_FN_ON_DQ5, GPIO_FN_ON_DQ4, GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, }; enum { SHDMA_SLAVE_INVALID, SHDMA_SLAVE_SDHI_TX, SHDMA_SLAVE_SDHI_RX, SHDMA_SLAVE_MMCIF_TX, SHDMA_SLAVE_MMCIF_RX, SHDMA_SLAVE_SCIF2_TX, SHDMA_SLAVE_SCIF2_RX, SHDMA_SLAVE_SCIF3_TX, SHDMA_SLAVE_SCIF3_RX, SHDMA_SLAVE_SCIF4_TX, SHDMA_SLAVE_SCIF4_RX, SHDMA_SLAVE_RIIC0_TX, SHDMA_SLAVE_RIIC0_RX, SHDMA_SLAVE_RIIC1_TX, SHDMA_SLAVE_RIIC1_RX, SHDMA_SLAVE_RIIC2_TX, SHDMA_SLAVE_RIIC2_RX, SHDMA_SLAVE_RIIC3_TX, SHDMA_SLAVE_RIIC3_RX, SHDMA_SLAVE_RIIC4_TX, SHDMA_SLAVE_RIIC4_RX, SHDMA_SLAVE_RIIC5_TX, SHDMA_SLAVE_RIIC5_RX, SHDMA_SLAVE_RIIC6_TX, SHDMA_SLAVE_RIIC6_RX, SHDMA_SLAVE_RIIC7_TX, SHDMA_SLAVE_RIIC7_RX, SHDMA_SLAVE_RIIC8_TX, SHDMA_SLAVE_RIIC8_RX, SHDMA_SLAVE_RIIC9_TX, SHDMA_SLAVE_RIIC9_RX, SHDMA_SLAVE_RSPI_TX, SHDMA_SLAVE_RSPI_RX, }; #endif /* __ASM_SH7757_H__ */ PK ! �d��g g include/cpu-sh4/cpu/sh7786.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * SH7786 Pinmux * * Copyright (C) 2008, 2009 Renesas Solutions Corp. * Kuninori Morimoto <morimoto.kuninori@renesas.com> * * Based on sh7785.h */ #ifndef __CPU_SH7786_H__ #define __CPU_SH7786_H__ #include <linux/io.h> enum { /* PA */ GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4, GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0, /* PB */ GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0, /* PC */ GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, /* PD */ GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, /* PE */ GPIO_PE7, GPIO_PE6, /* PF */ GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, /* PG */ GPIO_PG7, GPIO_PG6, GPIO_PG5, /* PH */ GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4, GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0, /* PJ */ GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4, GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, /* DU */ GPIO_FN_DCLKIN, GPIO_FN_DCLKOUT, GPIO_FN_ODDF, GPIO_FN_VSYNC, GPIO_FN_HSYNC, GPIO_FN_CDE, GPIO_FN_DISP, GPIO_FN_DR0, GPIO_FN_DG0, GPIO_FN_DB0, GPIO_FN_DR1, GPIO_FN_DG1, GPIO_FN_DB1, GPIO_FN_DR2, GPIO_FN_DG2, GPIO_FN_DB2, GPIO_FN_DR3, GPIO_FN_DG3, GPIO_FN_DB3, GPIO_FN_DR4, GPIO_FN_DG4, GPIO_FN_DB4, GPIO_FN_DR5, GPIO_FN_DG5, GPIO_FN_DB5, /* Eth */ GPIO_FN_ETH_MAGIC, GPIO_FN_ETH_LINK, GPIO_FN_ETH_TX_ER, GPIO_FN_ETH_TX_EN, GPIO_FN_ETH_MDIO, GPIO_FN_ETH_RX_CLK, GPIO_FN_ETH_MDC, GPIO_FN_ETH_COL, GPIO_FN_ETH_TX_CLK, GPIO_FN_ETH_CRS, GPIO_FN_ETH_RX_DV, GPIO_FN_ETH_RX_ER, GPIO_FN_ETH_TXD3, GPIO_FN_ETH_TXD2, GPIO_FN_ETH_TXD1, GPIO_FN_ETH_TXD0, GPIO_FN_ETH_RXD3, GPIO_FN_ETH_RXD2, GPIO_FN_ETH_RXD1, GPIO_FN_ETH_RXD0, /* HSPI */ GPIO_FN_HSPI_CLK, GPIO_FN_HSPI_CS, GPIO_FN_HSPI_RX, GPIO_FN_HSPI_TX, /* SCIF0 */ GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_SCK, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_TXD, /* SCIF1 */ GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD, /* SCIF3 */ GPIO_FN_SCIF3_SCK, GPIO_FN_SCIF3_RXD, GPIO_FN_SCIF3_TXD, /* SCIF4 */ GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD, /* SCIF5 */ GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD, /* LBSC */ GPIO_FN_BREQ, GPIO_FN_IOIS16, GPIO_FN_CE2B, GPIO_FN_CE2A, GPIO_FN_BACK, /* FLCTL */ GPIO_FN_FALE, GPIO_FN_FRB, GPIO_FN_FSTATUS, GPIO_FN_FSE, GPIO_FN_FCLE, /* DMAC */ GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_DRAK0, GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DRAK1, GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DRAK2, GPIO_FN_DACK3, GPIO_FN_DREQ3, GPIO_FN_DRAK3, /* USB */ GPIO_FN_USB_OVC0, GPIO_FN_USB_PENC0, GPIO_FN_USB_OVC1, GPIO_FN_USB_PENC1, /* HAC */ GPIO_FN_HAC_RES, GPIO_FN_HAC0_SDOUT, GPIO_FN_HAC0_SDIN, GPIO_FN_HAC0_SYNC, GPIO_FN_HAC0_BITCLK, GPIO_FN_HAC1_SDOUT, GPIO_FN_HAC1_SDIN, GPIO_FN_HAC1_SYNC, GPIO_FN_HAC1_BITCLK, /* SSI */ GPIO_FN_SSI0_SDATA, GPIO_FN_SSI0_SCK, GPIO_FN_SSI0_WS, GPIO_FN_SSI0_CLK, GPIO_FN_SSI1_SDATA, GPIO_FN_SSI1_SCK, GPIO_FN_SSI1_WS, GPIO_FN_SSI1_CLK, GPIO_FN_SSI2_SDATA, GPIO_FN_SSI2_SCK, GPIO_FN_SSI2_WS, GPIO_FN_SSI3_SDATA, GPIO_FN_SSI3_SCK, GPIO_FN_SSI3_WS, /* SDIF1 */ GPIO_FN_SDIF1CMD, GPIO_FN_SDIF1CD, GPIO_FN_SDIF1WP, GPIO_FN_SDIF1CLK, GPIO_FN_SDIF1D3, GPIO_FN_SDIF1D2, GPIO_FN_SDIF1D1, GPIO_FN_SDIF1D0, /* SDIF0 */ GPIO_FN_SDIF0CMD, GPIO_FN_SDIF0CD, GPIO_FN_SDIF0WP, GPIO_FN_SDIF0CLK, GPIO_FN_SDIF0D3, GPIO_FN_SDIF0D2, GPIO_FN_SDIF0D1, GPIO_FN_SDIF0D0, /* TMU */ GPIO_FN_TCLK, /* INTC */ GPIO_FN_IRL7, GPIO_FN_IRL6, GPIO_FN_IRL5, GPIO_FN_IRL4, }; static inline u32 sh7786_mm_sel(void) { return __raw_readl((const volatile void __iomem *)0xFC400020) & 0x7; } #endif /* __CPU_SH7786_H__ */ PK ! � �� � include/cpu-sh4/cpu/fpu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h * * Copyright (C) 2006 STMicroelectronics Limited * Author: Carl Shaw <carl.shaw@st.com> * * Definitions for SH4 FPU operations */ #ifndef __CPU_SH4_FPU_H #define __CPU_SH4_FPU_H #define FPSCR_ENABLE_MASK 0x00000f80UL #define FPSCR_FMOV_DOUBLE (1<<1) #define FPSCR_CAUSE_INEXACT (1<<12) #define FPSCR_CAUSE_UNDERFLOW (1<<13) #define FPSCR_CAUSE_OVERFLOW (1<<14) #define FPSCR_CAUSE_DIVZERO (1<<15) #define FPSCR_CAUSE_INVALID (1<<16) #define FPSCR_CAUSE_ERROR (1<<17) #define FPSCR_DBL_PRECISION (1<<19) #define FPSCR_ROUNDING_MODE(x) ((x >> 20) & 3) #define FPSCR_RM_NEAREST (0) #define FPSCR_RM_ZERO (1) #endif PK ! Ϋ|� % % include/cpu-sh4/cpu/sh7723.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7723_H__ #define __ASM_SH7723_H__ /* Boot Mode Pins: * * MD0: CPG - Clock Mode 0->3 * MD1: CPG - Clock Mode 0->3 * MD2: CPG - Reserved (L: Normal operation) * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10] * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3] * MD8: Test Mode */ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function * GPIO_Pxx - GPIO mapped to real I/O pin on CPU */ enum { /* PTA */ GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, /* PTB */ GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, /* PTC */ GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4, GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0, /* PTD */ GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, /* PTE */ GPIO_PTE5, GPIO_PTE4, GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0, /* PTF */ GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, /* PTG */ GPIO_PTG5, GPIO_PTG4, GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, /* PTH */ GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, /* PTJ */ GPIO_PTJ7, GPIO_PTJ5, GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0, /* PTK */ GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, /* PTL */ GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0, /* PTM */ GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, /* PTN */ GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4, GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, /* PTQ */ GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, /* PTR */ GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4, GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, /* PTS */ GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, /* PTT */ GPIO_PTT5, GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, /* PTU */ GPIO_PTU5, GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, /* PTV */ GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, /* PTW */ GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0, /* PTX */ GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0, /* PTY */ GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4, GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0, /* PTZ */ GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4, GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0, /* SCIF0 (SCIF: 3 pin PTT/PTU) */ GPIO_FN_SCIF0_PTT_TXD, GPIO_FN_SCIF0_PTT_RXD, GPIO_FN_SCIF0_PTT_SCK, GPIO_FN_SCIF0_PTU_TXD, GPIO_FN_SCIF0_PTU_RXD, GPIO_FN_SCIF0_PTU_SCK, /* SCIF1 (SCIF: 3 pin PTS/PTV) */ GPIO_FN_SCIF1_PTS_TXD, GPIO_FN_SCIF1_PTS_RXD, GPIO_FN_SCIF1_PTS_SCK, GPIO_FN_SCIF1_PTV_TXD, GPIO_FN_SCIF1_PTV_RXD, GPIO_FN_SCIF1_PTV_SCK, /* SCIF2 (SCIF: 3 pin PTT/PTU) */ GPIO_FN_SCIF2_PTT_TXD, GPIO_FN_SCIF2_PTT_RXD, GPIO_FN_SCIF2_PTT_SCK, GPIO_FN_SCIF2_PTU_TXD, GPIO_FN_SCIF2_PTU_RXD, GPIO_FN_SCIF2_PTU_SCK, /* SCIF3 (SCIFA: 5 pin PTS/PTV) */ GPIO_FN_SCIF3_PTS_TXD, GPIO_FN_SCIF3_PTS_RXD, GPIO_FN_SCIF3_PTS_SCK, GPIO_FN_SCIF3_PTS_RTS, GPIO_FN_SCIF3_PTS_CTS, GPIO_FN_SCIF3_PTV_TXD, GPIO_FN_SCIF3_PTV_RXD, GPIO_FN_SCIF3_PTV_SCK, GPIO_FN_SCIF3_PTV_RTS, GPIO_FN_SCIF3_PTV_CTS, /* SCIF4 (SCIFA: 3 pin PTE/PTN) */ GPIO_FN_SCIF4_PTE_TXD, GPIO_FN_SCIF4_PTE_RXD, GPIO_FN_SCIF4_PTE_SCK, GPIO_FN_SCIF4_PTN_TXD, GPIO_FN_SCIF4_PTN_RXD, GPIO_FN_SCIF4_PTN_SCK, /* SCIF5 (SCIFA: 3 pin PTE/PTN) */ GPIO_FN_SCIF5_PTE_TXD, GPIO_FN_SCIF5_PTE_RXD, GPIO_FN_SCIF5_PTE_SCK, GPIO_FN_SCIF5_PTN_TXD, GPIO_FN_SCIF5_PTN_RXD, GPIO_FN_SCIF5_PTN_SCK, /* CEU */ GPIO_FN_VIO_D15, GPIO_FN_VIO_D14, GPIO_FN_VIO_D13, GPIO_FN_VIO_D12, GPIO_FN_VIO_D11, GPIO_FN_VIO_D10, GPIO_FN_VIO_D9, GPIO_FN_VIO_D8, GPIO_FN_VIO_D7, GPIO_FN_VIO_D6, GPIO_FN_VIO_D5, GPIO_FN_VIO_D4, GPIO_FN_VIO_D3, GPIO_FN_VIO_D2, GPIO_FN_VIO_D1, GPIO_FN_VIO_D0, GPIO_FN_VIO_FLD, GPIO_FN_VIO_CKO, GPIO_FN_VIO_VD1, GPIO_FN_VIO_HD1, GPIO_FN_VIO_CLK1, GPIO_FN_VIO_VD2, GPIO_FN_VIO_HD2, GPIO_FN_VIO_CLK2, /* LCDC */ GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20, GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16, GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12, GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8, GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4, GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0, GPIO_FN_LCDLCLK_PTR, GPIO_FN_LCDLCLK_PTW, /* Main LCD */ GPIO_FN_LCDDON, GPIO_FN_LCDVCPWC, GPIO_FN_LCDVEPWC, GPIO_FN_LCDVSYN, /* Main LCD - RGB Mode */ GPIO_FN_LCDDCK, GPIO_FN_LCDHSYN, GPIO_FN_LCDDISP, /* Main LCD - SYS Mode */ GPIO_FN_LCDRS, GPIO_FN_LCDCS, GPIO_FN_LCDWR, GPIO_FN_LCDRD, /* IRQ */ GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3, GPIO_FN_IRQ4, GPIO_FN_IRQ5, GPIO_FN_IRQ6, GPIO_FN_IRQ7, /* AUD */ GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, /* SDHI0 (PTD) */ GPIO_FN_SDHI0CD_PTD, GPIO_FN_SDHI0WP_PTD, GPIO_FN_SDHI0D3_PTD, GPIO_FN_SDHI0D2_PTD, GPIO_FN_SDHI0D1_PTD, GPIO_FN_SDHI0D0_PTD, GPIO_FN_SDHI0CMD_PTD, GPIO_FN_SDHI0CLK_PTD, /* SDHI0 (PTS) */ GPIO_FN_SDHI0CD_PTS, GPIO_FN_SDHI0WP_PTS, GPIO_FN_SDHI0D3_PTS, GPIO_FN_SDHI0D2_PTS, GPIO_FN_SDHI0D1_PTS, GPIO_FN_SDHI0D0_PTS, GPIO_FN_SDHI0CMD_PTS, GPIO_FN_SDHI0CLK_PTS, /* SDHI1 */ GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2, GPIO_FN_SDHI1D1, GPIO_FN_SDHI1D0, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK, /* SIUA */ GPIO_FN_SIUAFCK, GPIO_FN_SIUAILR, GPIO_FN_SIUAIBT, GPIO_FN_SIUAISLD, GPIO_FN_SIUAOLR, GPIO_FN_SIUAOBT, GPIO_FN_SIUAOSLD, GPIO_FN_SIUAMCK, GPIO_FN_SIUAISPD, GPIO_FN_SIUAOSPD, /* SIUB */ GPIO_FN_SIUBFCK, GPIO_FN_SIUBILR, GPIO_FN_SIUBIBT, GPIO_FN_SIUBISLD, GPIO_FN_SIUBOLR, GPIO_FN_SIUBOBT, GPIO_FN_SIUBOSLD, GPIO_FN_SIUBMCK, /* IRDA */ GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, /* VOU */ GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_HSYNC, GPIO_FN_DV_VSYNC, GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12, GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8, GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4, GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0, /* KEYSC */ GPIO_FN_KEYIN0, GPIO_FN_KEYIN1, GPIO_FN_KEYIN2, GPIO_FN_KEYIN3, GPIO_FN_KEYIN4, GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5, /* MSIOF0 (PTF) */ GPIO_FN_MSIOF0_PTF_TXD, GPIO_FN_MSIOF0_PTF_RXD, GPIO_FN_MSIOF0_PTF_MCK, GPIO_FN_MSIOF0_PTF_TSYNC, GPIO_FN_MSIOF0_PTF_TSCK, GPIO_FN_MSIOF0_PTF_RSYNC, GPIO_FN_MSIOF0_PTF_RSCK, GPIO_FN_MSIOF0_PTF_SS1, GPIO_FN_MSIOF0_PTF_SS2, /* MSIOF0 (PTT+PTX) */ GPIO_FN_MSIOF0_PTT_TXD, GPIO_FN_MSIOF0_PTT_RXD, GPIO_FN_MSIOF0_PTX_MCK, GPIO_FN_MSIOF0_PTT_TSYNC, GPIO_FN_MSIOF0_PTT_TSCK, GPIO_FN_MSIOF0_PTT_RSYNC, GPIO_FN_MSIOF0_PTT_RSCK, GPIO_FN_MSIOF0_PTT_SS1, GPIO_FN_MSIOF0_PTT_SS2, /* MSIOF1 */ GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_RXD, GPIO_FN_MSIOF1_MCK, GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_TSCK, GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_SS1, GPIO_FN_MSIOF1_SS2, /* TSIF */ GPIO_FN_TS0_SDAT, GPIO_FN_TS0_SCK, GPIO_FN_TS0_SDEN, GPIO_FN_TS0_SPSYNC, /* FLCTL */ GPIO_FN_FCE, GPIO_FN_NAF7, GPIO_FN_NAF6, GPIO_FN_NAF5, GPIO_FN_NAF4, GPIO_FN_NAF3, GPIO_FN_NAF2, GPIO_FN_NAF1, GPIO_FN_NAF0, GPIO_FN_FCDE, GPIO_FN_FOE, GPIO_FN_FSC, GPIO_FN_FWE, GPIO_FN_FRB, /* DMAC */ GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DACK0, GPIO_FN_DREQ0, /* ADC */ GPIO_FN_AN3, GPIO_FN_AN2, GPIO_FN_AN1, GPIO_FN_AN0, GPIO_FN_ADTRG, /* CPG */ GPIO_FN_STATUS0, GPIO_FN_PDSTATUS, /* TPU */ GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0, /* BSC */ GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28, GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24, GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20, GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16, GPIO_FN_IOIS16, GPIO_FN_WAIT, GPIO_FN_BS, GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_CS6B_CE1B, GPIO_FN_CS6A_CE2B, GPIO_FN_CS5B_CE1A, GPIO_FN_CS5A_CE2A, GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD, /* ATAPI */ GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12, GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9, GPIO_FN_IDED8, GPIO_FN_IDED7, GPIO_FN_IDED6, GPIO_FN_IDED5, GPIO_FN_IDED4, GPIO_FN_IDED3, GPIO_FN_IDED2, GPIO_FN_IDED1, GPIO_FN_IDED0, GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK, GPIO_FN_IODREQ, GPIO_FN_IDEIORDY, GPIO_FN_IDEINT, GPIO_FN_IDEIOWR, GPIO_FN_IDEIORD, GPIO_FN_IDECS1, GPIO_FN_IDECS0, GPIO_FN_IDEA2, GPIO_FN_IDEA1, GPIO_FN_IDEA0, }; enum { HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_L2C, HWBLK_ILMEM, HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, HWBLK_HUDI, HWBLK_UBC, HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, HWBLK_FLCTL, HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3, HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1, HWBLK_MERAM, HWBLK_IIC, HWBLK_RTC, HWBLK_ATAPI, HWBLK_ADC, HWBLK_TPU, HWBLK_IRDA, HWBLK_TSIF, HWBLK_ICB, HWBLK_SDHI0, HWBLK_SDHI1, HWBLK_KEYSC, HWBLK_USB, HWBLK_2DG, HWBLK_SIU, HWBLK_VEU2H1, HWBLK_VOU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU2H0, HWBLK_VPU, HWBLK_LCDC, HWBLK_NR, }; #endif /* __ASM_SH7723_H__ */ PK ! ;W�� include/cpu-sh4/cpu/sigcontext.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CPU_SH4_SIGCONTEXT_H #define __ASM_CPU_SH4_SIGCONTEXT_H struct sigcontext { unsigned long oldmask; /* CPU registers */ unsigned long sc_regs[16]; unsigned long sc_pc; unsigned long sc_pr; unsigned long sc_sr; unsigned long sc_gbr; unsigned long sc_mach; unsigned long sc_macl; /* FPU registers */ unsigned long sc_fpregs[16]; unsigned long sc_xfpregs[16]; unsigned int sc_fpscr; unsigned int sc_fpul; unsigned int sc_ownedfp; }; #endif /* __ASM_CPU_SH4_SIGCONTEXT_H */ PK ! �J�(� � include/cpu-sh4/cpu/rtc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CPU_SH4_RTC_H #define __ASM_SH_CPU_SH4_RTC_H #if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7723) #define rtc_reg_size sizeof(u16) #else #define rtc_reg_size sizeof(u32) #endif #define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */ #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR #endif /* __ASM_SH_CPU_SH4_RTC_H */ PK ! Ő� � � include/cpu-sh4/cpu/dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_CPU_SH4_DMA_H #define __ASM_CPU_SH4_DMA_H #include <linux/sh_intc.h> /* * SH7750/SH7751/SH7760 */ #define DMTE0_IRQ evt2irq(0x640) #define DMTE4_IRQ evt2irq(0x780) #define DMTE6_IRQ evt2irq(0x7c0) #define DMAE0_IRQ evt2irq(0x6c0) #define SH_DMAC_BASE0 0xffa00000 #define SH_DMAC_BASE1 0xffa00070 #endif /* __ASM_CPU_SH4_DMA_H */ PK ! B�?C6 6 include/cpu-sh4/cpu/sq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh4/sq.h * * Copyright (C) 2001, 2002, 2003 Paul Mundt * Copyright (C) 2001, 2002 M. R. Brown */ #ifndef __ASM_CPU_SH4_SQ_H #define __ASM_CPU_SH4_SQ_H #include <asm/addrspace.h> #include <asm/page.h> /* * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be * mapped to any physical address space. Since data is written (and aligned) * to 32-byte boundaries, we need to be sure that all allocations are aligned. */ #define SQ_SIZE 32 #define SQ_ALIGN_MASK (~(SQ_SIZE - 1)) #define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK) #define SQ_QACR0 (P4SEG_REG_BASE + 0x38) #define SQ_QACR1 (P4SEG_REG_BASE + 0x3c) #define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000) /* arch/sh/kernel/cpu/sh4/sq.c */ unsigned long sq_remap(unsigned long phys, unsigned int size, const char *name, pgprot_t prot); void sq_unmap(unsigned long vaddr); void sq_flush_range(unsigned long start, unsigned int len); #endif /* __ASM_CPU_SH4_SQ_H */ PK ! �B�( �( include/cpu-sh4/cpu/sh7724.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7724_H__ #define __ASM_SH7724_H__ /* Boot Mode Pins: * * MD0: CPG - Clock Mode 0->7 * MD1: CPG - Clock Mode 0->7 * MD2: CPG - Clock Mode 0->7 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10] * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3] * MD8: Test Mode * BOOT: FBR - Boot Mode (L: MMCIF, H: Area0) */ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function * GPIO_Pxx - GPIO mapped to real I/O pin on CPU */ enum { /* PTA */ GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, /* PTB */ GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, /* PTC */ GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4, GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0, /* PTD */ GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, /* PTE */ GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0, /* PTF */ GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, /* PTG */ GPIO_PTG5, GPIO_PTG4, GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, /* PTH */ GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, /* PTJ */ GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0, /* PTK */ GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, /* PTL */ GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0, /* PTM */ GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, /* PTN */ GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4, GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, /* PTQ */ GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, /* PTR */ GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4, GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, /* PTS */ GPIO_PTS6, GPIO_PTS5, GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, /* PTT */ GPIO_PTT7, GPIO_PTT6, GPIO_PTT5, GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, /* PTU */ GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, /* PTV */ GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, /* PTW */ GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0, /* PTX */ GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0, /* PTY */ GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4, GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0, /* PTZ */ GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4, GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0, /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */ GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28, GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24, GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20, GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16, GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_CS6B_CE1B, GPIO_FN_CS6A_CE2B, GPIO_FN_CS5B_CE1A, GPIO_FN_CS5A_CE2A, GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD, GPIO_FN_IOIS16, GPIO_FN_WAIT, GPIO_FN_BS, /* KEYSC (PTA/PTB)*/ GPIO_FN_KEYOUT5_IN5, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYIN4, GPIO_FN_KEYIN3, GPIO_FN_KEYIN2, GPIO_FN_KEYIN1, GPIO_FN_KEYIN0, GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT0, /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */ GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12, GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9, GPIO_FN_IDED8, GPIO_FN_IDED7, GPIO_FN_IDED6, GPIO_FN_IDED5, GPIO_FN_IDED4, GPIO_FN_IDED3, GPIO_FN_IDED2, GPIO_FN_IDED1, GPIO_FN_IDED0, GPIO_FN_IDEA2, GPIO_FN_IDEA1, GPIO_FN_IDEA0, GPIO_FN_IDEIOWR, GPIO_FN_IODREQ, GPIO_FN_IDECS0, GPIO_FN_IDECS1, GPIO_FN_IDEIORD, GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK, GPIO_FN_IDEINT, GPIO_FN_IDEIORDY, /* TPU (PTB/PTR/PTS) */ GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0, GPIO_FN_TPUTI3, GPIO_FN_TPUTI2, /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */ GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20, GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16, GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12, GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8, GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4, GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0, GPIO_FN_LCDVSYN, GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDDON, GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_LCDVEPWC, GPIO_FN_LCDVCPWC, GPIO_FN_LCDRD, GPIO_FN_LCDLCLK, /* SCIF0 (PTF/PTM) */ GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_SCK, /* SCIF1 (PTL) */ GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD, /* SCIF2 (PTE/PTF/PTN) with LCDC, VOU */ GPIO_FN_SCIF2_L_TXD, GPIO_FN_SCIF2_L_SCK, GPIO_FN_SCIF2_L_RXD, GPIO_FN_SCIF2_V_TXD, GPIO_FN_SCIF2_V_SCK, GPIO_FN_SCIF2_V_RXD, /* SCIF3 (PTL/PTN/PTZ) with VOU, IRQ */ GPIO_FN_SCIF3_V_SCK, GPIO_FN_SCIF3_V_RXD, GPIO_FN_SCIF3_V_TXD, GPIO_FN_SCIF3_V_CTS, GPIO_FN_SCIF3_V_RTS, GPIO_FN_SCIF3_I_SCK, GPIO_FN_SCIF3_I_RXD, GPIO_FN_SCIF3_I_TXD, GPIO_FN_SCIF3_I_CTS, GPIO_FN_SCIF3_I_RTS, /* SCIF4 (PTE) */ GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD, /* SCIF5 (PTS) */ GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD, /* FSI (PTE/PTU/PTV) */ GPIO_FN_FSIMCKB, GPIO_FN_FSIMCKA, GPIO_FN_FSIOASD, GPIO_FN_FSIIABCK, GPIO_FN_FSIIALRCK, GPIO_FN_FSIOABCK, GPIO_FN_FSIOALRCK, GPIO_FN_CLKAUDIOAO, GPIO_FN_FSIIBSD, GPIO_FN_FSIOBSD, GPIO_FN_FSIIBBCK, GPIO_FN_FSIIBLRCK, GPIO_FN_FSIOBBCK, GPIO_FN_FSIOBLRCK, GPIO_FN_CLKAUDIOBO, GPIO_FN_FSIIASD, /* AUD (PTG) */ GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, /* VIO (PTS) (common?) */ GPIO_FN_VIO_CKO, /* VIO0 (PTH/PTK) */ GPIO_FN_VIO0_D15, GPIO_FN_VIO0_D14, GPIO_FN_VIO0_D13, GPIO_FN_VIO0_D12, GPIO_FN_VIO0_D11, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D8, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D5, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D2, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D0, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FLD, GPIO_FN_VIO0_HD, /* VIO1 (PTK/PTS) */ GPIO_FN_VIO1_D7, GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D5, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D2, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D0, GPIO_FN_VIO1_FLD, GPIO_FN_VIO1_HD, GPIO_FN_VIO1_VD, GPIO_FN_VIO1_CLK, /* Eth (PTL/PTN/PTX) */ GPIO_FN_RMII_RXD0, GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TXD0, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_REF_CLK, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_CRS_DV, GPIO_FN_LNKSTA, GPIO_FN_MDIO, GPIO_FN_MDC, /* System (PTJ) */ GPIO_FN_PDSTATUS, GPIO_FN_STATUS2, GPIO_FN_STATUS0, /* VOU (PTL/PTM/PTN*/ GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12, GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8, GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4, GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0, GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC, /* MSIOF0 (PTL/PTM) */ GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, GPIO_FN_MSIOF0_MCK, GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_RSCK, GPIO_FN_MSIOF0_RSYNC, /* MSIOF1 (PTV) */ GPIO_FN_MSIOF1_RXD, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_MCK, GPIO_FN_MSIOF1_TSCK, GPIO_FN_MSIOF1_SS1, GPIO_FN_MSIOF1_SS2, GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, /* DMAC (PTU/PTX) */ GPIO_FN_DMAC_DACK0, GPIO_FN_DMAC_DREQ0, GPIO_FN_DMAC_DACK1, GPIO_FN_DMAC_DREQ1, /* SDHI0 (PTY) */ GPIO_FN_SDHI0CD, GPIO_FN_SDHI0WP, GPIO_FN_SDHI0CMD, GPIO_FN_SDHI0CLK, GPIO_FN_SDHI0D3, GPIO_FN_SDHI0D2, GPIO_FN_SDHI0D1, GPIO_FN_SDHI0D0, /* SDHI1 (PTW) */ GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK, GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2, GPIO_FN_SDHI1D1, GPIO_FN_SDHI1D0, /* MMC (PTW/PTX)*/ GPIO_FN_MMC_D7, GPIO_FN_MMC_D6, GPIO_FN_MMC_D5, GPIO_FN_MMC_D4, GPIO_FN_MMC_D3, GPIO_FN_MMC_D2, GPIO_FN_MMC_D1, GPIO_FN_MMC_D0, GPIO_FN_MMC_CLK, GPIO_FN_MMC_CMD, /* IrDA (PTX) */ GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN, /* TSIF (PTX) */ GPIO_FN_TSIF_TS0_SDAT, GPIO_FN_TSIF_TS0_SCK, GPIO_FN_TSIF_TS0_SDEN, GPIO_FN_TSIF_TS0_SPSYNC, /* IRQ (PTZ) */ GPIO_FN_INTC_IRQ7, GPIO_FN_INTC_IRQ6, GPIO_FN_INTC_IRQ5, GPIO_FN_INTC_IRQ4, GPIO_FN_INTC_IRQ3, GPIO_FN_INTC_IRQ2, GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0, }; enum { HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_RSMEM, HWBLK_ILMEM, HWBLK_L2C, HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, HWBLK_HUDI, HWBLK_UBC, HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3, HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1, HWBLK_KEYSC, HWBLK_RTC, HWBLK_IIC0, HWBLK_IIC1, HWBLK_MMC, HWBLK_ETHER, HWBLK_ATAPI, HWBLK_TPU, HWBLK_IRDA, HWBLK_TSIF, HWBLK_USB1, HWBLK_USB0, HWBLK_2DG, HWBLK_SDHI0, HWBLK_SDHI1, HWBLK_VEU1, HWBLK_CEU1, HWBLK_BEU1, HWBLK_2DDMAC, HWBLK_SPU, HWBLK_JPU, HWBLK_VOU, HWBLK_BEU0, HWBLK_CEU0, HWBLK_VEU0, HWBLK_VPU, HWBLK_LCDC, HWBLK_NR, }; enum { SHDMA_SLAVE_INVALID, SHDMA_SLAVE_SCIF0_TX, SHDMA_SLAVE_SCIF0_RX, SHDMA_SLAVE_SCIF1_TX, SHDMA_SLAVE_SCIF1_RX, SHDMA_SLAVE_SCIF2_TX, SHDMA_SLAVE_SCIF2_RX, SHDMA_SLAVE_SCIF3_TX, SHDMA_SLAVE_SCIF3_RX, SHDMA_SLAVE_SCIF4_TX, SHDMA_SLAVE_SCIF4_RX, SHDMA_SLAVE_SCIF5_TX, SHDMA_SLAVE_SCIF5_RX, SHDMA_SLAVE_USB0D0_TX, SHDMA_SLAVE_USB0D0_RX, SHDMA_SLAVE_USB0D1_TX, SHDMA_SLAVE_USB0D1_RX, SHDMA_SLAVE_USB1D0_TX, SHDMA_SLAVE_USB1D0_RX, SHDMA_SLAVE_USB1D1_TX, SHDMA_SLAVE_USB1D1_RX, SHDMA_SLAVE_SDHI0_TX, SHDMA_SLAVE_SDHI0_RX, SHDMA_SLAVE_SDHI1_TX, SHDMA_SLAVE_SDHI1_RX, }; extern struct clk sh7724_fsimcka_clk; extern struct clk sh7724_fsimckb_clk; extern struct clk sh7724_dv_clki; #endif /* __ASM_SH7724_H__ */ PK ! �\9�6 6 include/cpu-sh4/cpu/sh7734.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7734_H__ #define __ASM_SH7734_H__ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU */ enum { GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31, GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, GPIO_FN_CLKOUT, GPIO_FN_BS, GPIO_FN_CS0, GPIO_FN_EX_CS0, GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_WE1, GPIO_FN_SCL0, GPIO_FN_PENC0, GPIO_FN_USB_OVC0, GPIO_FN_IRQ2_B, GPIO_FN_IRQ3_B, /* IPSR0 */ GPIO_FN_A15, GPIO_FN_ST0_VCO_CLKIN, GPIO_FN_LCD_DATA15_A, GPIO_FN_TIOC3D_C, GPIO_FN_A14, GPIO_FN_LCD_DATA14_A, GPIO_FN_TIOC3C_C, GPIO_FN_A13, GPIO_FN_LCD_DATA13_A, GPIO_FN_TIOC3B_C, GPIO_FN_A12, GPIO_FN_LCD_DATA12_A, GPIO_FN_TIOC3A_C, GPIO_FN_A11, GPIO_FN_ST0_D7, GPIO_FN_LCD_DATA11_A, GPIO_FN_TIOC2B_C, GPIO_FN_A10, GPIO_FN_ST0_D6, GPIO_FN_LCD_DATA10_A, GPIO_FN_TIOC2A_C, GPIO_FN_A9, GPIO_FN_ST0_D5, GPIO_FN_LCD_DATA9_A, GPIO_FN_TIOC1B_C, GPIO_FN_A8, GPIO_FN_ST0_D4, GPIO_FN_LCD_DATA8_A, GPIO_FN_TIOC1A_C, GPIO_FN_A7, GPIO_FN_ST0_D3, GPIO_FN_LCD_DATA7_A, GPIO_FN_TIOC0D_C, GPIO_FN_A6, GPIO_FN_ST0_D2, GPIO_FN_LCD_DATA6_A, GPIO_FN_TIOC0C_C, GPIO_FN_A5, GPIO_FN_ST0_D1, GPIO_FN_LCD_DATA5_A, GPIO_FN_TIOC0B_C, GPIO_FN_A4, GPIO_FN_ST0_D0, GPIO_FN_LCD_DATA4_A, GPIO_FN_TIOC0A_C, GPIO_FN_A3, GPIO_FN_ST0_VLD, GPIO_FN_LCD_DATA3_A, GPIO_FN_TCLKD_C, GPIO_FN_A2, GPIO_FN_ST0_SYC, GPIO_FN_LCD_DATA2_A, GPIO_FN_TCLKC_C, GPIO_FN_A1, GPIO_FN_ST0_REQ, GPIO_FN_LCD_DATA1_A, GPIO_FN_TCLKB_C, GPIO_FN_A0, GPIO_FN_ST0_CLKIN, GPIO_FN_LCD_DATA0_A, GPIO_FN_TCLKA_C, /* IPSR1 */ GPIO_FN_D3, GPIO_FN_SD0_DAT3_A, GPIO_FN_MMC_D3_A, GPIO_FN_ST1_D6, GPIO_FN_FD3_A, GPIO_FN_D2, GPIO_FN_SD0_DAT2_A, GPIO_FN_MMC_D2_A, GPIO_FN_ST1_D5, GPIO_FN_FD2_A, GPIO_FN_D1, GPIO_FN_SD0_DAT1_A, GPIO_FN_MMC_D1_A, GPIO_FN_ST1_D4, GPIO_FN_FD1_A, GPIO_FN_D0, GPIO_FN_SD0_DAT0_A, GPIO_FN_MMC_D0_A, GPIO_FN_ST1_D3, GPIO_FN_FD0_A, GPIO_FN_A25, GPIO_FN_TX2_D, GPIO_FN_ST1_D2, GPIO_FN_A24, GPIO_FN_RX2_D, GPIO_FN_ST1_D1, GPIO_FN_A23, GPIO_FN_ST1_D0, GPIO_FN_LCD_M_DISP_A, GPIO_FN_A22, GPIO_FN_ST1_VLD, GPIO_FN_LCD_VEPWC_A, GPIO_FN_A21, GPIO_FN_ST1_SYC, GPIO_FN_LCD_VCPWC_A, GPIO_FN_A20, GPIO_FN_ST1_REQ, GPIO_FN_LCD_FLM_A, GPIO_FN_A19, GPIO_FN_ST1_CLKIN, GPIO_FN_LCD_CLK_A, GPIO_FN_TIOC4D_C, GPIO_FN_A18, GPIO_FN_ST1_PWM, GPIO_FN_LCD_CL2_A, GPIO_FN_TIOC4C_C, GPIO_FN_A17, GPIO_FN_ST1_VCO_CLKIN, GPIO_FN_LCD_CL1_A, GPIO_FN_TIOC4B_C, GPIO_FN_A16, GPIO_FN_ST0_PWM, GPIO_FN_LCD_DON_A, GPIO_FN_TIOC4A_C, /* IPSR2 */ GPIO_FN_D14, GPIO_FN_TX2_B, GPIO_FN_FSE_A, GPIO_FN_ET0_TX_CLK_B, GPIO_FN_D13, GPIO_FN_RX2_B, GPIO_FN_FRB_A, GPIO_FN_ET0_ETXD6_B, GPIO_FN_D12, GPIO_FN_FWE_A, GPIO_FN_ET0_ETXD5_B, GPIO_FN_D11, GPIO_FN_RSPI_MISO_A, GPIO_FN_QMI_QIO1_A, GPIO_FN_FRE_A, GPIO_FN_ET0_ETXD3_B, GPIO_FN_D10, GPIO_FN_RSPI_MOSI_A, GPIO_FN_QMO_QIO0_A, GPIO_FN_FALE_A, GPIO_FN_ET0_ETXD2_B, GPIO_FN_D9, GPIO_FN_SD0_CMD_A, GPIO_FN_MMC_CMD_A, GPIO_FN_QIO3_A, GPIO_FN_FCLE_A, GPIO_FN_ET0_ETXD1_B, GPIO_FN_D8, GPIO_FN_SD0_CLK_A, GPIO_FN_MMC_CLK_A, GPIO_FN_QIO2_A, GPIO_FN_FCE_A, GPIO_FN_ET0_GTX_CLK_B, GPIO_FN_D7, GPIO_FN_RSPI_SSL_A, GPIO_FN_MMC_D7_A, GPIO_FN_QSSL_A, GPIO_FN_FD7_A, GPIO_FN_D6, GPIO_FN_RSPI_RSPCK_A, GPIO_FN_MMC_D6_A, GPIO_FN_QSPCLK_A, GPIO_FN_FD6_A, GPIO_FN_D5, GPIO_FN_SD0_WP_A, GPIO_FN_MMC_D5_A, GPIO_FN_FD5_A, GPIO_FN_D4, GPIO_FN_SD0_CD_A, GPIO_FN_MMC_D4_A, GPIO_FN_ST1_D7, GPIO_FN_FD4_A, /* IPSR3 */ GPIO_FN_DRACK0, GPIO_FN_SD1_DAT2_A, GPIO_FN_ATAG, GPIO_FN_TCLK1_A, GPIO_FN_ET0_ETXD7, GPIO_FN_EX_WAIT2, GPIO_FN_SD1_DAT1_A, GPIO_FN_DACK2, GPIO_FN_CAN1_RX_C, GPIO_FN_ET0_MAGIC_C, GPIO_FN_ET0_ETXD6_A, GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C, GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A, GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B, GPIO_FN_RD_WR, GPIO_FN_TCLK0, GPIO_FN_CAN_CLK_B, GPIO_FN_ET0_ETXD4, GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B, GPIO_FN_ET0_ETXD3_A, GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B, GPIO_FN_ET0_ETXD2_A, GPIO_FN_EX_CS3, GPIO_FN_SD1_CD_A, GPIO_FN_ATARD, GPIO_FN_QMO_QIO0_B, GPIO_FN_ET0_ETXD1_A, GPIO_FN_EX_CS2, GPIO_FN_TX3_B, GPIO_FN_ATACS1, GPIO_FN_QSPCLK_B, GPIO_FN_ET0_GTX_CLK_A, GPIO_FN_EX_CS1, GPIO_FN_RX3_B, GPIO_FN_ATACS0, GPIO_FN_QIO2_B, GPIO_FN_ET0_ETXD0, GPIO_FN_CS1_A26, GPIO_FN_QIO3_B, GPIO_FN_D15, GPIO_FN_SCK2_B, /* IPSR4 */ GPIO_FN_SCK2_A, GPIO_FN_VI0_G3, GPIO_FN_RTS1_B, GPIO_FN_VI0_G2, GPIO_FN_CTS1_B, GPIO_FN_VI0_DATA7_VI0_G1, GPIO_FN_TX1_B, GPIO_FN_VI0_DATA6_VI0_G0, GPIO_FN_ET0_PHY_INT_A, GPIO_FN_RX1_B, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_ET0_MAGIC_A, GPIO_FN_SCK1_B, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ET0_LINK_A, GPIO_FN_RTS0_B, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ET0_MDIO_A, GPIO_FN_CTS0_B, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_RMII0_MDIO_A, GPIO_FN_ET0_MDC, GPIO_FN_HTX0_A, GPIO_FN_TX1_A, GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_RMII0_MDC_A, GPIO_FN_ET0_COL, GPIO_FN_HRX0_A, GPIO_FN_RX1_A, GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_RMII0_CRS_DV_A, GPIO_FN_ET0_CRS, GPIO_FN_HSCK0_A, GPIO_FN_SCK1_A, GPIO_FN_VI0_VSYNC, GPIO_FN_RMII0_RX_ER_A, GPIO_FN_ET0_RX_ER, GPIO_FN_HRTS0_A, GPIO_FN_RTS1_A, GPIO_FN_VI0_HSYNC, GPIO_FN_RMII0_TXD_EN_A, GPIO_FN_ET0_RX_DV, GPIO_FN_HCTS0_A, GPIO_FN_CTS1_A, GPIO_FN_VI0_FIELD, GPIO_FN_RMII0_RXD1_A, GPIO_FN_ET0_ERXD7, /* IPSR5 */ GPIO_FN_SD2_CLK_A, GPIO_FN_RX2_A, GPIO_FN_VI0_G4, GPIO_FN_ET0_RX_CLK_B, GPIO_FN_SD2_CMD_A, GPIO_FN_TX2_A, GPIO_FN_VI0_G5, GPIO_FN_ET0_ERXD2_B, GPIO_FN_SD2_DAT0_A, GPIO_FN_RX3_A, GPIO_FN_VI0_R0, GPIO_FN_ET0_ERXD3_B, GPIO_FN_SD2_DAT1_A, GPIO_FN_TX3_A, GPIO_FN_VI0_R1, GPIO_FN_ET0_MDIO_B, GPIO_FN_SD2_DAT2_A, GPIO_FN_RX4_A, GPIO_FN_VI0_R2, GPIO_FN_ET0_LINK_B, GPIO_FN_SD2_DAT3_A, GPIO_FN_TX4_A, GPIO_FN_VI0_R3, GPIO_FN_ET0_MAGIC_B, GPIO_FN_SD2_CD_A, GPIO_FN_RX5_A, GPIO_FN_VI0_R4, GPIO_FN_ET0_PHY_INT_B, GPIO_FN_SD2_WP_A, GPIO_FN_TX5_A, GPIO_FN_VI0_R5, GPIO_FN_REF125CK, GPIO_FN_ADTRG, GPIO_FN_RX5_C, GPIO_FN_REF50CK, GPIO_FN_CTS1_E, GPIO_FN_HCTS0_D, /* IPSR6 */ GPIO_FN_DU0_DR0, GPIO_FN_SCIF_CLK_B, GPIO_FN_HRX0_D, GPIO_FN_IETX_A, GPIO_FN_TCLKA_A, GPIO_FN_HIFD00, GPIO_FN_DU0_DR1, GPIO_FN_SCK0_B, GPIO_FN_HTX0_D, GPIO_FN_IERX_A, GPIO_FN_TCLKB_A, GPIO_FN_HIFD01, GPIO_FN_DU0_DR2, GPIO_FN_RX0_B, GPIO_FN_TCLKC_A, GPIO_FN_HIFD02, GPIO_FN_DU0_DR3, GPIO_FN_TX0_B, GPIO_FN_TCLKD_A, GPIO_FN_HIFD03, GPIO_FN_DU0_DR4, GPIO_FN_CTS0_C, GPIO_FN_TIOC0A_A, GPIO_FN_HIFD04, GPIO_FN_DU0_DR5, GPIO_FN_RTS0_C, GPIO_FN_TIOC0B_A, GPIO_FN_HIFD05, GPIO_FN_DU0_DR6, GPIO_FN_SCK1_C, GPIO_FN_TIOC0C_A, GPIO_FN_HIFD06, GPIO_FN_DU0_DR7, GPIO_FN_RX1_C, GPIO_FN_TIOC0D_A, GPIO_FN_HIFD07, GPIO_FN_DU0_DG0, GPIO_FN_TX1_C, GPIO_FN_HSCK0_D, GPIO_FN_IECLK_A, GPIO_FN_TIOC1A_A, GPIO_FN_HIFD08, GPIO_FN_DU0_DG1, GPIO_FN_CTS1_C, GPIO_FN_HRTS0_D, GPIO_FN_TIOC1B_A, GPIO_FN_HIFD09, /* IPSR7 */ GPIO_FN_DU0_DG2, GPIO_FN_RTS1_C, GPIO_FN_RMII0_MDC_B, GPIO_FN_TIOC2A_A, GPIO_FN_HIFD10, GPIO_FN_DU0_DG3, GPIO_FN_SCK2_C, GPIO_FN_RMII0_MDIO_B, GPIO_FN_TIOC2B_A, GPIO_FN_HIFD11, GPIO_FN_DU0_DG4, GPIO_FN_RX2_C, GPIO_FN_RMII0_CRS_DV_B, GPIO_FN_TIOC3A_A, GPIO_FN_HIFD12, GPIO_FN_DU0_DG5, GPIO_FN_TX2_C, GPIO_FN_RMII0_RX_ER_B, GPIO_FN_TIOC3B_A, GPIO_FN_HIFD13, GPIO_FN_DU0_DG6, GPIO_FN_RX3_C, GPIO_FN_RMII0_RXD0_B, GPIO_FN_TIOC3C_A, GPIO_FN_HIFD14, GPIO_FN_DU0_DG7, GPIO_FN_TX3_C, GPIO_FN_RMII0_RXD1_B, GPIO_FN_TIOC3D_A, GPIO_FN_HIFD15, GPIO_FN_DU0_DB0, GPIO_FN_RX4_C, GPIO_FN_RMII0_TXD_EN_B, GPIO_FN_TIOC4A_A, GPIO_FN_HIFCS, GPIO_FN_DU0_DB1, GPIO_FN_TX4_C, GPIO_FN_RMII0_TXD0_B, GPIO_FN_TIOC4B_A, GPIO_FN_HIFRS, GPIO_FN_DU0_DB2, GPIO_FN_RX5_B, GPIO_FN_RMII0_TXD1_B, GPIO_FN_TIOC4C_A, GPIO_FN_HIFWR, GPIO_FN_DU0_DB3, GPIO_FN_TX5_B, GPIO_FN_TIOC4D_A, GPIO_FN_HIFRD, GPIO_FN_DU0_DB4, GPIO_FN_HIFINT, /* IPSR8 */ GPIO_FN_DU0_DB5, GPIO_FN_HIFDREQ, GPIO_FN_DU0_DB6, GPIO_FN_HIFRDY, GPIO_FN_DU0_DB7, GPIO_FN_SSI_SCK0_B, GPIO_FN_HIFEBL_B, GPIO_FN_DU0_DOTCLKIN, GPIO_FN_HSPI_CS0_C, GPIO_FN_SSI_WS0_B, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_HSPI_CLK0_C, GPIO_FN_SSI_SDATA0_B, GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_HSPI_TX0_C, GPIO_FN_SSI_SCK1_B, GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_HSPI_RX0_C, GPIO_FN_SSI_WS1_B, GPIO_FN_DU0_EXODDF_DU0_ODDF, GPIO_FN_CAN0_RX_B, GPIO_FN_HSCK0_B, GPIO_FN_SSI_SDATA1_B, GPIO_FN_DU0_DISP, GPIO_FN_CAN0_TX_B, GPIO_FN_HRX0_B, GPIO_FN_AUDIO_CLKA_B, GPIO_FN_DU0_CDE, GPIO_FN_HTX0_B, GPIO_FN_AUDIO_CLKB_B, GPIO_FN_LCD_VCPWC_B, GPIO_FN_IRQ0_A, GPIO_FN_HSPI_TX_B, GPIO_FN_RX3_E, GPIO_FN_ET0_ERXD0, GPIO_FN_IRQ1_A, GPIO_FN_HSPI_RX_B, GPIO_FN_TX3_E, GPIO_FN_ET0_ERXD1, GPIO_FN_IRQ2_A, GPIO_FN_CTS0_A, GPIO_FN_HCTS0_B, GPIO_FN_ET0_ERXD2_A, GPIO_FN_IRQ3_A, GPIO_FN_RTS0_A, GPIO_FN_HRTS0_B, GPIO_FN_ET0_ERXD3_A, /* IPSR9 */ GPIO_FN_VI1_CLK_A, GPIO_FN_FD0_B, GPIO_FN_LCD_DATA0_B, GPIO_FN_VI1_0_A, GPIO_FN_FD1_B, GPIO_FN_LCD_DATA1_B, GPIO_FN_VI1_1_A, GPIO_FN_FD2_B, GPIO_FN_LCD_DATA2_B, GPIO_FN_VI1_2_A, GPIO_FN_FD3_B, GPIO_FN_LCD_DATA3_B, GPIO_FN_VI1_3_A, GPIO_FN_FD4_B, GPIO_FN_LCD_DATA4_B, GPIO_FN_VI1_4_A, GPIO_FN_FD5_B, GPIO_FN_LCD_DATA5_B, GPIO_FN_VI1_5_A, GPIO_FN_FD6_B, GPIO_FN_LCD_DATA6_B, GPIO_FN_VI1_6_A, GPIO_FN_FD7_B, GPIO_FN_LCD_DATA7_B, GPIO_FN_VI1_7_A, GPIO_FN_FCE_B, GPIO_FN_LCD_DATA8_B, GPIO_FN_SSI_SCK0_A, GPIO_FN_TIOC1A_B, GPIO_FN_LCD_DATA9_B, GPIO_FN_SSI_WS0_A, GPIO_FN_TIOC1B_B, GPIO_FN_LCD_DATA10_B, GPIO_FN_SSI_SDATA0_A, GPIO_FN_VI1_0_B, GPIO_FN_TIOC2A_B, GPIO_FN_LCD_DATA11_B, GPIO_FN_SSI_SCK1_A, GPIO_FN_VI1_1_B, GPIO_FN_TIOC2B_B, GPIO_FN_LCD_DATA12_B, GPIO_FN_SSI_WS1_A, GPIO_FN_VI1_2_B, GPIO_FN_LCD_DATA13_B, GPIO_FN_SSI_SDATA1_A, GPIO_FN_VI1_3_B, GPIO_FN_LCD_DATA14_B, /* IPSR10 */ GPIO_FN_SSI_SCK23, GPIO_FN_VI1_4_B, GPIO_FN_RX1_D, GPIO_FN_FCLE_B, GPIO_FN_LCD_DATA15_B, GPIO_FN_SSI_WS23, GPIO_FN_VI1_5_B, GPIO_FN_TX1_D, GPIO_FN_HSCK0_C, GPIO_FN_FALE_B, GPIO_FN_LCD_DON_B, GPIO_FN_SSI_SDATA2, GPIO_FN_VI1_6_B, GPIO_FN_HRX0_C, GPIO_FN_FRE_B, GPIO_FN_LCD_CL1_B, GPIO_FN_SSI_SDATA3, GPIO_FN_VI1_7_B, GPIO_FN_HTX0_C, GPIO_FN_FWE_B, GPIO_FN_LCD_CL2_B, GPIO_FN_AUDIO_CLKA_A, GPIO_FN_VI1_CLK_B, GPIO_FN_SCK1_D, GPIO_FN_IECLK_B, GPIO_FN_LCD_FLM_B, GPIO_FN_AUDIO_CLKB_A, GPIO_FN_LCD_CLK_B, GPIO_FN_AUDIO_CLKC, GPIO_FN_SCK1_E, GPIO_FN_HCTS0_C, GPIO_FN_FRB_B, GPIO_FN_LCD_VEPWC_B, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_TX1_E, GPIO_FN_HRTS0_C, GPIO_FN_FSE_B, GPIO_FN_LCD_M_DISP_B, GPIO_FN_CAN_CLK_A, GPIO_FN_RX4_D, GPIO_FN_CAN0_TX_A, GPIO_FN_TX4_D, GPIO_FN_MLB_CLK, GPIO_FN_CAN1_RX_A, GPIO_FN_IRQ1_B, GPIO_FN_CAN0_RX_A, GPIO_FN_IRQ0_B, GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_A, GPIO_FN_TX5_C, GPIO_FN_MLB_DAT, /* IPSR11 */ GPIO_FN_SCL1, GPIO_FN_SCIF_CLK_C, GPIO_FN_SDA1, GPIO_FN_RX1_E, GPIO_FN_SDA0, GPIO_FN_HIFEBL_A, GPIO_FN_SDSELF, GPIO_FN_RTS1_E, GPIO_FN_SCIF_CLK_A, GPIO_FN_HSPI_CLK_A, GPIO_FN_VI0_CLK, GPIO_FN_RMII0_TXD0_A, GPIO_FN_ET0_ERXD4, GPIO_FN_SCK0_A, GPIO_FN_HSPI_CS_A, GPIO_FN_VI0_CLKENB, GPIO_FN_RMII0_TXD1_A, GPIO_FN_ET0_ERXD5, GPIO_FN_RX0_A, GPIO_FN_HSPI_RX_A, GPIO_FN_RMII0_RXD0_A, GPIO_FN_ET0_ERXD6, GPIO_FN_TX0_A, GPIO_FN_HSPI_TX_A, GPIO_FN_PENC1, GPIO_FN_TX3_D, GPIO_FN_CAN1_TX_B, GPIO_FN_TX5_D, GPIO_FN_IETX_B, GPIO_FN_USB_OVC1, GPIO_FN_RX3_D, GPIO_FN_CAN1_RX_B, GPIO_FN_RX5_D, GPIO_FN_IERX_B, GPIO_FN_DREQ0, GPIO_FN_SD1_CLK_A, GPIO_FN_ET0_TX_EN, GPIO_FN_DACK0, GPIO_FN_SD1_DAT3_A, GPIO_FN_ET0_TX_ER, GPIO_FN_DREQ1, GPIO_FN_HSPI_CLK_B, GPIO_FN_RX4_B, GPIO_FN_ET0_PHY_INT_C, GPIO_FN_ET0_TX_CLK_A, GPIO_FN_DACK1, GPIO_FN_HSPI_CS_B, GPIO_FN_TX4_B, GPIO_FN_ET0_RX_CLK_A, GPIO_FN_PRESETOUT, GPIO_FN_ST_CLKOUT, }; #endif /* __ASM_SH7734_H__ */ PK ! �NX� include/cpu-sh4/cpu/sh7722.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH7722_H__ #define __ASM_SH7722_H__ /* Boot Mode Pins: * * MD0: CPG - Clock Mode 0->3 * MD1: CPG - Clock Mode 0->3 * MD2: CPG - Reserved (L: Normal operation) * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10] * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3] * MD8: Test Mode */ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function * GPIO_Pxx - GPIO mapped to real I/O pin on CPU */ enum { /* PTA */ GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, /* PTB */ GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, /* PTC */ GPIO_PTC7, GPIO_PTC5, GPIO_PTC4, GPIO_PTC3, GPIO_PTC2, GPIO_PTC0, /* PTD */ GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, /* PTE */ GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, GPIO_PTE1, GPIO_PTE0, /* PTF */ GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, /* PTG */ GPIO_PTG4, GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, /* PTH */ GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, /* PTJ */ GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ1, GPIO_PTJ0, /* PTK */ GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, /* PTL */ GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0, /* PTM */ GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, /* PTN */ GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4, GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, /* PTQ */ GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, /* PTR */ GPIO_PTR4, GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, /* PTS */ GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, /* PTT */ GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, /* PTU */ GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, /* PTV */ GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, /* PTW */ GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0, /* PTX */ GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0, /* PTY */ GPIO_PTY5, GPIO_PTY4, GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0, /* PTZ */ GPIO_PTZ5, GPIO_PTZ4, GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, /* SCIF0 */ GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_SCK, /* SCIF1 */ GPIO_FN_SCIF1_TXD, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_RTS, GPIO_FN_SCIF1_CTS, GPIO_FN_SCIF1_SCK, /* SCIF2 */ GPIO_FN_SCIF2_TXD, GPIO_FN_SCIF2_RXD, GPIO_FN_SCIF2_RTS, GPIO_FN_SCIF2_CTS, GPIO_FN_SCIF2_SCK, /* SIO */ GPIO_FN_SIOTXD, GPIO_FN_SIORXD, GPIO_FN_SIOD, GPIO_FN_SIOSTRB0, GPIO_FN_SIOSTRB1, GPIO_FN_SIOSCK, GPIO_FN_SIOMCK, /* CEU */ GPIO_FN_VIO_D15, GPIO_FN_VIO_D14, GPIO_FN_VIO_D13, GPIO_FN_VIO_D12, GPIO_FN_VIO_D11, GPIO_FN_VIO_D10, GPIO_FN_VIO_D9, GPIO_FN_VIO_D8, GPIO_FN_VIO_D7, GPIO_FN_VIO_D6, GPIO_FN_VIO_D5, GPIO_FN_VIO_D4, GPIO_FN_VIO_D3, GPIO_FN_VIO_D2, GPIO_FN_VIO_D1, GPIO_FN_VIO_D0, GPIO_FN_VIO_FLD, GPIO_FN_VIO_CKO, GPIO_FN_VIO_STEX, GPIO_FN_VIO_STEM, GPIO_FN_VIO_VD, GPIO_FN_VIO_HD, GPIO_FN_VIO_CLK, GPIO_FN_VIO_VD2, GPIO_FN_VIO_HD2, GPIO_FN_VIO_CLK2, /* LCDC */ GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20, GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16, GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12, GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8, GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4, GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0, GPIO_FN_LCDLCLK, /* Main LCD */ GPIO_FN_LCDDON, GPIO_FN_LCDVCPWC, GPIO_FN_LCDVEPWC, GPIO_FN_LCDVSYN, /* Main LCD - RGB Mode */ GPIO_FN_LCDDCK, GPIO_FN_LCDHSYN, GPIO_FN_LCDDISP, /* Main LCD - SYS Mode */ GPIO_FN_LCDRS, GPIO_FN_LCDCS, GPIO_FN_LCDWR, GPIO_FN_LCDRD, /* Sub LCD - SYS Mode */ GPIO_FN_LCDDON2, GPIO_FN_LCDVCPWC2, GPIO_FN_LCDVEPWC2, GPIO_FN_LCDVSYN2, GPIO_FN_LCDCS2, /* BSC */ GPIO_FN_IOIS16, GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_BS, GPIO_FN_CS6B_CE1B, GPIO_FN_WAIT, GPIO_FN_CS6A_CE2B, /* SBSC */ GPIO_FN_HPD63, GPIO_FN_HPD62, GPIO_FN_HPD61, GPIO_FN_HPD60, GPIO_FN_HPD59, GPIO_FN_HPD58, GPIO_FN_HPD57, GPIO_FN_HPD56, GPIO_FN_HPD55, GPIO_FN_HPD54, GPIO_FN_HPD53, GPIO_FN_HPD52, GPIO_FN_HPD51, GPIO_FN_HPD50, GPIO_FN_HPD49, GPIO_FN_HPD48, GPIO_FN_HPDQM7, GPIO_FN_HPDQM6, GPIO_FN_HPDQM5, GPIO_FN_HPDQM4, /* IRQ */ GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3, GPIO_FN_IRQ4, GPIO_FN_IRQ5, GPIO_FN_IRQ6, GPIO_FN_IRQ7, /* SDHI */ GPIO_FN_SDHICD, GPIO_FN_SDHIWP, GPIO_FN_SDHID3, GPIO_FN_SDHID2, GPIO_FN_SDHID1, GPIO_FN_SDHID0, GPIO_FN_SDHICMD, GPIO_FN_SDHICLK, /* SIU - Port A */ GPIO_FN_SIUAOLR, GPIO_FN_SIUAOBT, GPIO_FN_SIUAISLD, GPIO_FN_SIUAILR, GPIO_FN_SIUAIBT, GPIO_FN_SIUAOSLD, GPIO_FN_SIUMCKA, GPIO_FN_SIUFCKA, /* SIU - Port B */ GPIO_FN_SIUBOLR, GPIO_FN_SIUBOBT, GPIO_FN_SIUBISLD, GPIO_FN_SIUBILR, GPIO_FN_SIUBIBT, GPIO_FN_SIUBOSLD, GPIO_FN_SIUMCKB, GPIO_FN_SIUFCKB, /* AUD */ GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, /* DMAC */ GPIO_FN_DACK, GPIO_FN_DREQ0, /* VOU */ GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_HSYNC, GPIO_FN_DV_VSYNC, GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12, GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8, GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4, GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0, /* CPG */ GPIO_FN_STATUS0, GPIO_FN_PDSTATUS, /* SIOF0 */ GPIO_FN_SIOF0_MCK, GPIO_FN_SIOF0_SCK, GPIO_FN_SIOF0_SYNC, GPIO_FN_SIOF0_SS1, GPIO_FN_SIOF0_SS2, GPIO_FN_SIOF0_TXD, GPIO_FN_SIOF0_RXD, /* SIOF1 */ GPIO_FN_SIOF1_MCK, GPIO_FN_SIOF1_SCK, GPIO_FN_SIOF1_SYNC, GPIO_FN_SIOF1_SS1, GPIO_FN_SIOF1_SS2, GPIO_FN_SIOF1_TXD, GPIO_FN_SIOF1_RXD, /* SIM */ GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, /* TSIF */ GPIO_FN_TS_SDAT, GPIO_FN_TS_SCK, GPIO_FN_TS_SDEN, GPIO_FN_TS_SPSYNC, /* IRDA */ GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, /* TPU */ GPIO_FN_TPUTO, /* FLCTL */ GPIO_FN_FCE, GPIO_FN_NAF7, GPIO_FN_NAF6, GPIO_FN_NAF5, GPIO_FN_NAF4, GPIO_FN_NAF3, GPIO_FN_NAF2, GPIO_FN_NAF1, GPIO_FN_NAF0, GPIO_FN_FCDE, GPIO_FN_FOE, GPIO_FN_FSC, GPIO_FN_FWE, GPIO_FN_FRB, /* KEYSC */ GPIO_FN_KEYIN0, GPIO_FN_KEYIN1, GPIO_FN_KEYIN2, GPIO_FN_KEYIN3, GPIO_FN_KEYIN4, GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5, }; enum { HWBLK_URAM, HWBLK_XYMEM, HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL, HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_IIC, HWBLK_RTC, HWBLK_SDHI, HWBLK_KEYSC, HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU, HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU, HWBLK_LCDC, HWBLK_NR, }; enum { SHDMA_SLAVE_INVALID, SHDMA_SLAVE_SCIF0_TX, SHDMA_SLAVE_SCIF0_RX, SHDMA_SLAVE_SCIF1_TX, SHDMA_SLAVE_SCIF1_RX, SHDMA_SLAVE_SCIF2_TX, SHDMA_SLAVE_SCIF2_RX, SHDMA_SLAVE_SIUA_TX, SHDMA_SLAVE_SIUA_RX, SHDMA_SLAVE_SIUB_TX, SHDMA_SLAVE_SIUB_RX, SHDMA_SLAVE_SDHI0_TX, SHDMA_SLAVE_SDHI0_RX, }; #endif /* __ASM_SH7722_H__ */ PK ! ���- - include/cpu-sh4/cpu/addrspace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 1999 by Kaz Kojima * * Defitions for the address spaces of the SH-4 CPUs. */ #ifndef __ASM_CPU_SH4_ADDRSPACE_H #define __ASM_CPU_SH4_ADDRSPACE_H #define P0SEG 0x00000000 #define P1SEG 0x80000000 #define P2SEG 0xa0000000 #define P3SEG 0xc0000000 #define P4SEG 0xe0000000 /* Detailed P4SEG */ #define P4SEG_STORE_QUE (P4SEG) #define P4SEG_IC_ADDR 0xf0000000 #define P4SEG_IC_DATA 0xf1000000 #define P4SEG_ITLB_ADDR 0xf2000000 #define P4SEG_ITLB_DATA 0xf3000000 #define P4SEG_OC_ADDR 0xf4000000 #define P4SEG_OC_DATA 0xf5000000 #define P4SEG_TLB_ADDR 0xf6000000 #define P4SEG_TLB_DATA 0xf7000000 #define P4SEG_REG_BASE 0xff000000 #define PA_AREA0 0x00000000 #define PA_AREA1 0x04000000 #define PA_AREA2 0x08000000 #define PA_AREA3 0x0c000000 #define PA_AREA4 0x10000000 #define PA_AREA5 0x14000000 #define PA_AREA6 0x18000000 #define PA_AREA7 0x1c000000 #define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */ #define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */ #endif /* __ASM_CPU_SH4_ADDRSPACE_H */ PK ! h� ! ! include/cpu-sh4/cpu/watchdog.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/cpu-sh4/watchdog.h * * Copyright (C) 2002, 2003 Paul Mundt * Copyright (C) 2009 Siemens AG * Copyright (C) 2009 Sitdikov Valentin */ #ifndef __ASM_CPU_SH4_WATCHDOG_H #define __ASM_CPU_SH4_WATCHDOG_H #if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780) /* Prefix definition */ #define WTBST_HIGH 0x55 /* Register definitions */ #define WTCNT_R 0xffcc0010 /*WDTCNT*/ #define WTCSR 0xffcc0004 /*WDTCSR*/ #define WTCNT 0xffcc0000 /*WDTST*/ #define WTST WTCNT #define WTBST 0xffcc0008 /*WDTBST*/ /* Register definitions */ #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \ defined(CONFIG_CPU_SUBTYPE_SH7723) || \ defined(CONFIG_CPU_SUBTYPE_SH7724) #define WTCNT 0xa4520000 #define WTCSR 0xa4520004 #else /* Register definitions */ #define WTCNT 0xffc00008 #define WTCSR 0xffc0000c #endif /* Bit definitions */ #define WTCSR_TME 0x80 #define WTCSR_WT 0x40 #define WTCSR_RSTS 0x20 #define WTCSR_WOVF 0x10 #define WTCSR_IOVF 0x08 #endif /* __ASM_CPU_SH4_WATCHDOG_H */ PK ! o]�#� � include/asm/mmu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MMU_H #define __MMU_H /* * Privileged Space Mapping Buffer (PMB) definitions */ #define PMB_PASCR 0xff000070 #define PMB_IRMCR 0xff000078 #define PASCR_SE 0x80000000 #define PMB_ADDR 0xf6100000 #define PMB_DATA 0xf7100000 #define NR_PMB_ENTRIES 16 #define PMB_E_MASK 0x0000000f #define PMB_E_SHIFT 8 #define PMB_PFN_MASK 0xff000000 #define PMB_SZ_16M 0x00000000 #define PMB_SZ_64M 0x00000010 #define PMB_SZ_128M 0x00000080 #define PMB_SZ_512M 0x00000090 #define PMB_SZ_MASK PMB_SZ_512M #define PMB_C 0x00000008 #define PMB_WT 0x00000001 #define PMB_UB 0x00000200 #define PMB_CACHE_MASK (PMB_C | PMB_WT | PMB_UB) #define PMB_V 0x00000100 #define PMB_NO_ENTRY (-1) #ifndef __ASSEMBLY__ #include <linux/errno.h> #include <linux/threads.h> #include <asm/page.h> /* Default "unsigned long" context */ typedef unsigned long mm_context_id_t[NR_CPUS]; typedef struct { #ifdef CONFIG_MMU mm_context_id_t id; void *vdso; #else unsigned long end_brk; #endif #ifdef CONFIG_BINFMT_ELF_FDPIC unsigned long exec_fdpic_loadmap; unsigned long interp_fdpic_loadmap; #endif } mm_context_t; #ifdef CONFIG_PMB /* arch/sh/mm/pmb.c */ bool __in_29bit_mode(void); void pmb_init(void); int pmb_bolt_mapping(unsigned long virt, phys_addr_t phys, unsigned long size, pgprot_t prot); void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size, pgprot_t prot, void *caller); int pmb_unmap(void __iomem *addr); #else static inline int pmb_bolt_mapping(unsigned long virt, phys_addr_t phys, unsigned long size, pgprot_t prot) { return -EINVAL; } static inline void __iomem * pmb_remap_caller(phys_addr_t phys, unsigned long size, pgprot_t prot, void *caller) { return NULL; } static inline int pmb_unmap(void __iomem *addr) { return -EINVAL; } #define pmb_init(addr) do { } while (0) #ifdef CONFIG_29BIT #define __in_29bit_mode() (1) #else #define __in_29bit_mode() (0) #endif #endif /* CONFIG_PMB */ static inline void __iomem * pmb_remap(phys_addr_t phys, unsigned long size, pgprot_t prot) { return pmb_remap_caller(phys, size, prot, __builtin_return_address(0)); } #endif /* __ASSEMBLY__ */ #endif /* __MMU_H */ PK ! %�+f f include/asm/futex-llsc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_FUTEX_LLSC_H #define __ASM_SH_FUTEX_LLSC_H static inline int atomic_futex_op_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { int err = 0; __asm__ __volatile__( "synco\n" "1:\n\t" "movli.l @%2, r0\n\t" "mov r0, %1\n\t" "cmp/eq %1, %4\n\t" "bf 2f\n\t" "mov %5, r0\n\t" "movco.l r0, @%2\n\t" "bf 1b\n" "2:\n\t" "synco\n\t" #ifdef CONFIG_MMU ".section .fixup,\"ax\"\n" "3:\n\t" "mov.l 4f, %0\n\t" "jmp @%0\n\t" " mov %3, %0\n\t" ".balign 4\n" "4: .long 2b\n\t" ".previous\n" ".section __ex_table,\"a\"\n\t" ".long 1b, 3b\n\t" ".previous" #endif :"+r" (err), "=&r" (*uval) :"r" (uaddr), "i" (-EFAULT), "r" (oldval), "r" (newval) :"t", "memory", "r0"); if (err) return err; return 0; } #endif /* __ASM_SH_FUTEX_LLSC_H */ PK ! ��i�� � include/asm/siu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * platform header for the SIU ASoC driver * * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> */ #ifndef ASM_SIU_H #define ASM_SIU_H struct device; struct siu_platform { unsigned int dma_slave_tx_a; unsigned int dma_slave_rx_a; unsigned int dma_slave_tx_b; unsigned int dma_slave_rx_b; }; #endif /* ASM_SIU_H */ PK ! �� �" " include/asm/seccomp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SECCOMP_H #include <linux/unistd.h> #define __NR_seccomp_read __NR_read #define __NR_seccomp_write __NR_write #define __NR_seccomp_exit __NR_exit #define __NR_seccomp_sigreturn __NR_rt_sigreturn #ifdef CONFIG_CPU_LITTLE_ENDIAN #define __SECCOMP_ARCH_LE __AUDIT_ARCH_LE #else #define __SECCOMP_ARCH_LE 0 #endif #define SECCOMP_ARCH_NATIVE (AUDIT_ARCH_SH | __SECCOMP_ARCH_LE) #define SECCOMP_ARCH_NATIVE_NR NR_syscalls #define SECCOMP_ARCH_NATIVE_NAME "sh" #endif /* __ASM_SECCOMP_H */ PK ! fb� � include/asm/pci.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PCI_H #define __ASM_SH_PCI_H /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */ #define pcibios_assign_all_busses() 1 /* * A board can define one or more PCI channels that represent built-in (or * external) PCI controllers. */ struct pci_channel { struct pci_channel *next; struct pci_bus *bus; struct pci_ops *pci_ops; struct resource *resources; unsigned int nr_resources; unsigned long io_offset; unsigned long mem_offset; unsigned long reg_base; unsigned long io_map_base; unsigned int index; unsigned int need_domain_info; /* Optional error handling */ struct timer_list err_timer, serr_timer; unsigned int err_irq, serr_irq; }; /* arch/sh/drivers/pci/pci.c */ extern raw_spinlock_t pci_config_lock; extern int register_pci_controller(struct pci_channel *hose); extern void pcibios_report_status(unsigned int status_mask, int warn); /* arch/sh/drivers/pci/common.c */ extern int early_read_config_byte(struct pci_channel *hose, int top_bus, int bus, int devfn, int offset, u8 *value); extern int early_read_config_word(struct pci_channel *hose, int top_bus, int bus, int devfn, int offset, u16 *value); extern int early_read_config_dword(struct pci_channel *hose, int top_bus, int bus, int devfn, int offset, u32 *value); extern int early_write_config_byte(struct pci_channel *hose, int top_bus, int bus, int devfn, int offset, u8 value); extern int early_write_config_word(struct pci_channel *hose, int top_bus, int bus, int devfn, int offset, u16 value); extern int early_write_config_dword(struct pci_channel *hose, int top_bus, int bus, int devfn, int offset, u32 value); extern void pcibios_enable_timers(struct pci_channel *hose); extern unsigned int pcibios_handle_status_errors(unsigned long addr, unsigned int status, struct pci_channel *hose); extern int pci_is_66mhz_capable(struct pci_channel *hose, int top_bus, int current_bus); extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM; #define HAVE_PCI_MMAP #define ARCH_GENERIC_PCI_MMAP_RESOURCE /* Dynamic DMA mapping stuff. * SuperH has everything mapped statically like x86. */ #ifdef CONFIG_PCI /* * None of the SH PCI controllers support MWI, it is always treated as a * direct memory write. */ #define PCI_DISABLE_MWI #endif /* Board-specific fixup routines. */ int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin); #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) { struct pci_channel *hose = bus->sysdata; return hose->need_domain_info; } /* Chances are this interrupt is wired PC-style ... */ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return channel ? 15 : 14; } #endif /* __ASM_SH_PCI_H */ PK ! ~��Y� � include/asm/hw_breakpoint.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HW_BREAKPOINT_H #define __ASM_SH_HW_BREAKPOINT_H #include <uapi/asm/hw_breakpoint.h> #define __ARCH_HW_BREAKPOINT_H #include <linux/kdebug.h> #include <linux/types.h> struct arch_hw_breakpoint { unsigned long address; u16 len; u16 type; }; enum { SH_BREAKPOINT_READ = (1 << 1), SH_BREAKPOINT_WRITE = (1 << 2), SH_BREAKPOINT_RW = SH_BREAKPOINT_READ | SH_BREAKPOINT_WRITE, SH_BREAKPOINT_LEN_1 = (1 << 12), SH_BREAKPOINT_LEN_2 = (1 << 13), SH_BREAKPOINT_LEN_4 = SH_BREAKPOINT_LEN_1 | SH_BREAKPOINT_LEN_2, SH_BREAKPOINT_LEN_8 = (1 << 14), }; struct sh_ubc { const char *name; unsigned int num_events; unsigned int trap_nr; void (*enable)(struct arch_hw_breakpoint *, int); void (*disable)(struct arch_hw_breakpoint *, int); void (*enable_all)(unsigned long); void (*disable_all)(void); unsigned long (*active_mask)(void); unsigned long (*triggered_mask)(void); void (*clear_triggered_mask)(unsigned long); struct clk *clk; /* optional interface clock / MSTP bit */ }; struct perf_event_attr; struct perf_event; struct task_struct; struct pmu; /* Maximum number of UBC channels */ #define HBP_NUM 2 static inline int hw_breakpoint_slots(int type) { return HBP_NUM; } /* arch/sh/kernel/hw_breakpoint.c */ extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw); extern int hw_breakpoint_arch_parse(struct perf_event *bp, const struct perf_event_attr *attr, struct arch_hw_breakpoint *hw); extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, unsigned long val, void *data); int arch_install_hw_breakpoint(struct perf_event *bp); void arch_uninstall_hw_breakpoint(struct perf_event *bp); void hw_breakpoint_pmu_read(struct perf_event *bp); extern void arch_fill_perf_breakpoint(struct perf_event *bp); extern int register_sh_ubc(struct sh_ubc *); extern struct pmu perf_ops_bp; #endif /* __ASM_SH_HW_BREAKPOINT_H */ PK ! v���i i include/asm/entry-macros.Snu �[��� ! SPDX-License-Identifier: GPL-2.0 ! entry.S macro define .macro cli stc sr, r0 or #0xf0, r0 ldc r0, sr .endm .macro sti mov #0xfffffff0, r11 extu.b r11, r11 not r11, r11 stc sr, r10 and r11, r10 #ifdef CONFIG_CPU_HAS_SR_RB stc k_g_imask, r11 or r11, r10 #endif ldc r10, sr .endm .macro get_current_thread_info, ti, tmp #ifdef CONFIG_CPU_HAS_SR_RB stc r7_bank, \ti #else mov #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp shll8 \tmp shll2 \tmp mov r15, \ti and \tmp, \ti #endif .endm #ifdef CONFIG_TRACE_IRQFLAGS .macro TRACE_IRQS_ON mov.l r0, @-r15 mov.l r1, @-r15 mov.l r2, @-r15 mov.l r3, @-r15 mov.l r4, @-r15 mov.l r5, @-r15 mov.l r6, @-r15 mov.l r7, @-r15 mov.l 7834f, r0 jsr @r0 nop mov.l @r15+, r7 mov.l @r15+, r6 mov.l @r15+, r5 mov.l @r15+, r4 mov.l @r15+, r3 mov.l @r15+, r2 mov.l @r15+, r1 mov.l @r15+, r0 mov.l 7834f, r0 bra 7835f nop .balign 4 7834: .long trace_hardirqs_on 7835: .endm .macro TRACE_IRQS_OFF mov.l r0, @-r15 mov.l r1, @-r15 mov.l r2, @-r15 mov.l r3, @-r15 mov.l r4, @-r15 mov.l r5, @-r15 mov.l r6, @-r15 mov.l r7, @-r15 mov.l 7834f, r0 jsr @r0 nop mov.l @r15+, r7 mov.l @r15+, r6 mov.l @r15+, r5 mov.l @r15+, r4 mov.l @r15+, r3 mov.l @r15+, r2 mov.l @r15+, r1 mov.l @r15+, r0 mov.l 7834f, r0 bra 7835f nop .balign 4 7834: .long trace_hardirqs_off 7835: .endm #else .macro TRACE_IRQS_ON .endm .macro TRACE_IRQS_OFF .endm #endif #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) # define PREF(x) pref @x #else # define PREF(x) nop #endif /* * Macro for use within assembly. Because the DWARF unwinder * needs to use the frame register to unwind the stack, we * need to setup r14 with the value of the stack pointer as * the return address is usually on the stack somewhere. */ .macro setup_frame_reg #ifdef CONFIG_DWARF_UNWINDER mov r15, r14 #endif .endm PK ! �� � � include/asm/string_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_STRING_H #define __ASM_SH_STRING_H /* * Copyright (C) 1999 Niibe Yutaka * But consider these trivial functions to be public domain. */ #define __HAVE_ARCH_STRCPY static inline char *strcpy(char *__dest, const char *__src) { register char *__xdest = __dest; unsigned long __dummy; __asm__ __volatile__("1:\n\t" "mov.b @%1+, %2\n\t" "mov.b %2, @%0\n\t" "cmp/eq #0, %2\n\t" "bf/s 1b\n\t" " add #1, %0\n\t" : "=r" (__dest), "=r" (__src), "=&z" (__dummy) : "0" (__dest), "1" (__src) : "memory", "t"); return __xdest; } #define __HAVE_ARCH_STRCMP static inline int strcmp(const char *__cs, const char *__ct) { register int __res; unsigned long __dummy; __asm__ __volatile__( "mov.b @%1+, %3\n" "1:\n\t" "mov.b @%0+, %2\n\t" "cmp/eq #0, %3\n\t" "bt 2f\n\t" "cmp/eq %2, %3\n\t" "bt/s 1b\n\t" " mov.b @%1+, %3\n\t" "add #-2, %1\n\t" "mov.b @%1, %3\n\t" "sub %3, %2\n" "2:" : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) : "0" (__cs), "1" (__ct) : "t"); return __res; } #define __HAVE_ARCH_STRNCMP static inline int strncmp(const char *__cs, const char *__ct, size_t __n) { register int __res; unsigned long __dummy; if (__n == 0) return 0; __asm__ __volatile__( "mov.b @%1+, %3\n" "1:\n\t" "mov.b @%0+, %2\n\t" "cmp/eq %6, %0\n\t" "bt/s 2f\n\t" " cmp/eq #0, %3\n\t" "bt/s 3f\n\t" " cmp/eq %3, %2\n\t" "bt/s 1b\n\t" " mov.b @%1+, %3\n\t" "add #-2, %1\n\t" "mov.b @%1, %3\n" "2:\n\t" "sub %3, %2\n" "3:" :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) : "0" (__cs), "1" (__ct), "r" (__cs+__n) : "t"); return __res; } #define __HAVE_ARCH_MEMSET extern void *memset(void *__s, int __c, size_t __count); #define __HAVE_ARCH_MEMCPY extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #define __HAVE_ARCH_MEMMOVE extern void *memmove(void *__dest, __const__ void *__src, size_t __n); #define __HAVE_ARCH_MEMCHR extern void *memchr(const void *__s, int __c, size_t __n); #define __HAVE_ARCH_STRLEN extern size_t strlen(const char *); #endif /* __ASM_SH_STRING_H */ PK ! j�� � include/asm/vmlinux.lds.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_VMLINUX_LDS_H #define __ASM_SH_VMLINUX_LDS_H #include <asm-generic/vmlinux.lds.h> #ifdef CONFIG_DWARF_UNWINDER #define DWARF_EH_FRAME \ .eh_frame : AT(ADDR(.eh_frame) - LOAD_OFFSET) { \ __start_eh_frame = .; \ *(.eh_frame) \ __stop_eh_frame = .; \ } #else #define DWARF_EH_FRAME #endif #endif /* __ASM_SH_VMLINUX_LDS_H */ PK ! '5q�� � include/asm/cache.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $ * * include/asm-sh/cache.h * * Copyright 1999 (C) Niibe Yutaka * Copyright 2002, 2003 (C) Paul Mundt */ #ifndef __ASM_SH_CACHE_H #define __ASM_SH_CACHE_H #include <linux/init.h> #include <cpu/cache.h> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define __read_mostly __section(".data..read_mostly") #ifndef __ASSEMBLY__ struct cache_info { unsigned int ways; /* Number of cache ways */ unsigned int sets; /* Number of cache sets */ unsigned int linesz; /* Cache line size (bytes) */ unsigned int way_size; /* sets * line size */ /* * way_incr is the address offset for accessing the next way * in memory mapped cache array ops. */ unsigned int way_incr; unsigned int entry_shift; unsigned int entry_mask; /* * Compute a mask which selects the address bits which overlap between * 1. those used to select the cache set during indexing * 2. those in the physical page number. */ unsigned int alias_mask; unsigned int n_aliases; /* Number of aliases */ unsigned long flags; }; #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_CACHE_H */ PK ! ��]� � include/asm/sram.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SRAM_H #define __ASM_SRAM_H #ifdef CONFIG_HAVE_SRAM_POOL #include <linux/spinlock.h> #include <linux/genalloc.h> /* arch/sh/mm/sram.c */ extern struct gen_pool *sram_pool; static inline unsigned long sram_alloc(size_t len) { if (!sram_pool) return 0UL; return gen_pool_alloc(sram_pool, len); } static inline void sram_free(unsigned long addr, size_t len) { return gen_pool_free(sram_pool, addr, len); } #else static inline unsigned long sram_alloc(size_t len) { return 0; } static inline void sram_free(unsigned long addr, size_t len) { } #endif /* CONFIG_HAVE_SRAM_POOL */ #endif /* __ASM_SRAM_H */ PK ! �:��� � include/asm/unistd.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <asm/unistd_32.h> #define NR_syscalls __NR_syscalls # define __ARCH_WANT_NEW_STAT # define __ARCH_WANT_OLD_READDIR # define __ARCH_WANT_OLD_STAT # define __ARCH_WANT_STAT64 # define __ARCH_WANT_SYS_ALARM # define __ARCH_WANT_SYS_GETHOSTNAME # define __ARCH_WANT_SYS_IPC # define __ARCH_WANT_SYS_PAUSE # define __ARCH_WANT_SYS_SIGNAL # define __ARCH_WANT_SYS_TIME32 # define __ARCH_WANT_SYS_UTIME32 # define __ARCH_WANT_SYS_WAITPID # define __ARCH_WANT_SYS_SOCKETCALL # define __ARCH_WANT_SYS_FADVISE64 # define __ARCH_WANT_SYS_GETPGRP # define __ARCH_WANT_SYS_NICE # define __ARCH_WANT_SYS_OLD_GETRLIMIT # define __ARCH_WANT_SYS_OLD_UNAME # define __ARCH_WANT_SYS_OLDUMOUNT # define __ARCH_WANT_SYS_SIGPENDING # define __ARCH_WANT_SYS_SIGPROCMASK # define __ARCH_WANT_SYS_FORK # define __ARCH_WANT_SYS_VFORK # define __ARCH_WANT_SYS_CLONE #include <uapi/asm/unistd.h> PK ! ��� � include/asm/setup.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _SH_SETUP_H #define _SH_SETUP_H #include <uapi/asm/setup.h> /* * This is set up by the setup-routine at boot-time */ #define PARAM ((unsigned char *)empty_zero_page) #define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000)) #define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004)) #define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008)) #define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c)) #define INITRD_START (*(unsigned long *) (PARAM+0x010)) #define INITRD_SIZE (*(unsigned long *) (PARAM+0x014)) /* ... */ #define COMMAND_LINE ((char *) (PARAM+0x100)) void sh_mv_setup(void); void check_for_initrd(void); void per_cpu_trap_init(void); #endif /* _SH_SETUP_H */ PK ! ��"ч � include/asm/extable.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_EXTABLE_H #define __ASM_SH_EXTABLE_H #include <asm-generic/extable.h> #endif PK ! r��� � include/asm/atomic-irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_ATOMIC_IRQ_H #define __ASM_SH_ATOMIC_IRQ_H #include <linux/irqflags.h> /* * To get proper branch prediction for the main line, we must branch * forward to code at the end of this object's .text section, then * branch back to restart the operation. */ #define ATOMIC_OP(op, c_op) \ static inline void arch_atomic_##op(int i, atomic_t *v) \ { \ unsigned long flags; \ \ raw_local_irq_save(flags); \ v->counter c_op i; \ raw_local_irq_restore(flags); \ } #define ATOMIC_OP_RETURN(op, c_op) \ static inline int arch_atomic_##op##_return(int i, atomic_t *v) \ { \ unsigned long temp, flags; \ \ raw_local_irq_save(flags); \ temp = v->counter; \ temp c_op i; \ v->counter = temp; \ raw_local_irq_restore(flags); \ \ return temp; \ } #define ATOMIC_FETCH_OP(op, c_op) \ static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \ { \ unsigned long temp, flags; \ \ raw_local_irq_save(flags); \ temp = v->counter; \ v->counter c_op i; \ raw_local_irq_restore(flags); \ \ return temp; \ } #define ATOMIC_OPS(op, c_op) \ ATOMIC_OP(op, c_op) \ ATOMIC_OP_RETURN(op, c_op) \ ATOMIC_FETCH_OP(op, c_op) ATOMIC_OPS(add, +=) ATOMIC_OPS(sub, -=) #undef ATOMIC_OPS #define ATOMIC_OPS(op, c_op) \ ATOMIC_OP(op, c_op) \ ATOMIC_FETCH_OP(op, c_op) ATOMIC_OPS(and, &=) ATOMIC_OPS(or, |=) ATOMIC_OPS(xor, ^=) #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN #undef ATOMIC_OP #endif /* __ASM_SH_ATOMIC_IRQ_H */ PK ! ����� � include/asm/fb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_FB_H_ #define _ASM_FB_H_ #include <linux/fb.h> #include <linux/fs.h> #include <asm/page.h> static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, unsigned long off) { vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); } static inline int fb_is_primary_device(struct fb_info *info) { return 0; } #endif /* _ASM_FB_H_ */ PK ! ��B\ \ include/asm/uncached.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_UNCACHED_H #define __ASM_SH_UNCACHED_H #include <linux/bug.h> #ifdef CONFIG_UNCACHED_MAPPING extern unsigned long cached_to_uncached; extern unsigned long uncached_size; extern unsigned long uncached_start, uncached_end; extern int virt_addr_uncached(unsigned long kaddr); extern void uncached_init(void); extern void uncached_resize(unsigned long size); /* * Jump to uncached area. * When handling TLB or caches, we need to do it from an uncached area. */ #define jump_to_uncached() \ do { \ unsigned long __dummy; \ \ __asm__ __volatile__( \ "mova 1f, %0\n\t" \ "add %1, %0\n\t" \ "jmp @%0\n\t" \ " nop\n\t" \ ".balign 4\n" \ "1:" \ : "=&z" (__dummy) \ : "r" (cached_to_uncached)); \ } while (0) /* * Back to cached area. */ #define back_to_cached() \ do { \ unsigned long __dummy; \ ctrl_barrier(); \ __asm__ __volatile__( \ "mov.l 1f, %0\n\t" \ "jmp @%0\n\t" \ " nop\n\t" \ ".balign 4\n" \ "1: .long 2f\n" \ "2:" \ : "=&r" (__dummy)); \ } while (0) #else #define virt_addr_uncached(kaddr) (0) #define uncached_init() do { } while (0) #define uncached_resize(size) BUG() #define jump_to_uncached() do { } while (0) #define back_to_cached() do { } while (0) #endif #endif /* __ASM_SH_UNCACHED_H */ PK ! xb�� � include/asm/dma-register.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Common header for the legacy SH DMA driver and the new dmaengine driver * * extracted from arch/sh/include/asm/dma-sh.h: * * Copyright (C) 2000 Takashi YOSHII * Copyright (C) 2003 Paul Mundt */ #ifndef DMA_REGISTER_H #define DMA_REGISTER_H /* DMA registers */ #define SAR 0x00 /* Source Address Register */ #define DAR 0x04 /* Destination Address Register */ #define TCR 0x08 /* Transfer Count Register */ #define CHCR 0x0C /* Channel Control Register */ #define DMAOR 0x40 /* DMA Operation Register */ /* DMAOR definitions */ #define DMAOR_AE 0x00000004 /* Address Error Flag */ #define DMAOR_NMIF 0x00000002 #define DMAOR_DME 0x00000001 /* DMA Master Enable */ /* Definitions for the SuperH DMAC */ #define REQ_L 0x00000000 #define REQ_E 0x00080000 #define RACK_H 0x00000000 #define RACK_L 0x00040000 #define ACK_R 0x00000000 #define ACK_W 0x00020000 #define ACK_H 0x00000000 #define ACK_L 0x00010000 #define DM_INC 0x00004000 /* Destination addresses are incremented */ #define DM_DEC 0x00008000 /* Destination addresses are decremented */ #define DM_FIX 0x0000c000 /* Destination address is fixed */ #define SM_INC 0x00001000 /* Source addresses are incremented */ #define SM_DEC 0x00002000 /* Source addresses are decremented */ #define SM_FIX 0x00003000 /* Source address is fixed */ #define RS_IN 0x00000200 #define RS_OUT 0x00000300 #define RS_AUTO 0x00000400 /* Auto Request */ #define RS_ERS 0x00000800 /* DMA extended resource selector */ #define TS_BLK 0x00000040 #define TM_BUR 0x00000020 #define CHCR_DE 0x00000001 /* DMA Enable */ #define CHCR_TE 0x00000002 /* Transfer End Flag */ #define CHCR_IE 0x00000004 /* Interrupt Enable */ #endif PK ! 8�u') ) include/asm/word-at-a-time.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_WORD_AT_A_TIME_H #define __ASM_SH_WORD_AT_A_TIME_H #ifdef CONFIG_CPU_BIG_ENDIAN # include <asm-generic/word-at-a-time.h> #else /* * Little-endian version cribbed from x86. */ struct word_at_a_time { const unsigned long one_bits, high_bits; }; #define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) } /* Carl Chatfield / Jan Achrenius G+ version for 32-bit */ static inline long count_masked_bytes(long mask) { /* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */ long a = (0x0ff0001+mask) >> 23; /* Fix the 1 for 00 case */ return a & mask; } /* Return nonzero if it has a zero */ static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c) { unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; *bits = mask; return mask; } static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c) { return bits; } static inline unsigned long create_zero_mask(unsigned long bits) { bits = (bits - 1) & ~bits; return bits >> 7; } /* The mask we created is directly usable as a bytemask */ #define zero_bytemask(mask) (mask) static inline unsigned long find_zero(unsigned long mask) { return count_masked_bytes(mask); } #endif #endif PK ! G"&�� � include/asm/Kbuildnu �[��� # SPDX-License-Identifier: GPL-2.0 generated-y += syscall_table.h generic-y += kvm_para.h generic-y += mcs_spinlock.h generic-y += parport.h PK ! )D� � include/asm/freq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0+ * * include/asm-sh/freq.h * * Copyright (C) 2002, 2003 Paul Mundt */ #ifndef __ASM_SH_FREQ_H #define __ASM_SH_FREQ_H #include <cpu/freq.h> #endif /* __ASM_SH_FREQ_H */ PK ! ��� � include/asm/shmparam.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/shmparam.h * * Copyright (C) 1999 Niibe Yutaka * Copyright (C) 2006 Paul Mundt */ #ifndef __ASM_SH_SHMPARAM_H #define __ASM_SH_SHMPARAM_H /* * SH-4 and SH-3 7705 have an aliasing dcache. Bump this up to a sensible value * for everyone, and work out the specifics from the probed cache descriptor. */ #define SHMLBA 0x4000 /* attach addr a multiple of this */ #define __ARCH_FORCE_SHMLBA #endif /* __ASM_SH_SHMPARAM_H */ PK ! ��# include/asm/cmpxchg.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CMPXCHG_H #define __ASM_SH_CMPXCHG_H /* * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. */ #include <linux/compiler.h> #include <linux/types.h> #if defined(CONFIG_GUSA_RB) #include <asm/cmpxchg-grb.h> #elif defined(CONFIG_CPU_SH4A) #include <asm/cmpxchg-llsc.h> #elif defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) #include <asm/cmpxchg-cas.h> #else #include <asm/cmpxchg-irq.h> #endif extern void __xchg_called_with_bad_pointer(void); #define __xchg(ptr, x, size) \ ({ \ unsigned long __xchg__res; \ volatile void *__xchg_ptr = (ptr); \ switch (size) { \ case 4: \ __xchg__res = xchg_u32(__xchg_ptr, x); \ break; \ case 2: \ __xchg__res = xchg_u16(__xchg_ptr, x); \ break; \ case 1: \ __xchg__res = xchg_u8(__xchg_ptr, x); \ break; \ default: \ __xchg_called_with_bad_pointer(); \ __xchg__res = x; \ break; \ } \ \ __xchg__res; \ }) #define arch_xchg(ptr,x) \ ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) /* This function doesn't exist, so you'll get a linker error * if something tries to do an invalid cmpxchg(). */ extern void __cmpxchg_called_with_bad_pointer(void); static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, unsigned long new, int size) { switch (size) { case 4: return __cmpxchg_u32(ptr, old, new); } __cmpxchg_called_with_bad_pointer(); return old; } #define arch_cmpxchg(ptr,o,n) \ ({ \ __typeof__(*(ptr)) _o_ = (o); \ __typeof__(*(ptr)) _n_ = (n); \ (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ (unsigned long)_n_, sizeof(*(ptr))); \ }) #endif /* __ASM_SH_CMPXCHG_H */ PK ! �� 7 7 include/asm/sections.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SECTIONS_H #define __ASM_SH_SECTIONS_H #include <asm-generic/sections.h> extern char __machvec_start[], __machvec_end[]; extern char __uncached_start, __uncached_end; extern char __start_eh_frame[], __stop_eh_frame[]; #endif /* __ASM_SH_SECTIONS_H */ PK ! ��� � include/asm/cacheflush.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CACHEFLUSH_H #define __ASM_SH_CACHEFLUSH_H #include <linux/mm.h> /* * Cache flushing: * * - flush_cache_all() flushes entire cache * - flush_cache_mm(mm) flushes the specified mm context's cache lines * - flush_cache_dup mm(mm) handles cache flushing when forking * - flush_cache_page(mm, vmaddr, pfn) flushes a single page * - flush_cache_range(vma, start, end) flushes a range of pages * * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache * - flush_icache_range(start, end) flushes(invalidates) a range for icache * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache * - flush_cache_sigtramp(vaddr) flushes the signal trampoline */ extern void (*local_flush_cache_all)(void *args); extern void (*local_flush_cache_mm)(void *args); extern void (*local_flush_cache_dup_mm)(void *args); extern void (*local_flush_cache_page)(void *args); extern void (*local_flush_cache_range)(void *args); extern void (*local_flush_dcache_page)(void *args); extern void (*local_flush_icache_range)(void *args); extern void (*local_flush_icache_page)(void *args); extern void (*local_flush_cache_sigtramp)(void *args); static inline void cache_noop(void *args) { } extern void (*__flush_wback_region)(void *start, int size); extern void (*__flush_purge_region)(void *start, int size); extern void (*__flush_invalidate_region)(void *start, int size); extern void flush_cache_all(void); extern void flush_cache_mm(struct mm_struct *mm); extern void flush_cache_dup_mm(struct mm_struct *mm); extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn); extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 extern void flush_dcache_page(struct page *page); extern void flush_icache_range(unsigned long start, unsigned long end); #define flush_icache_user_range flush_icache_range extern void flush_icache_page(struct vm_area_struct *vma, struct page *page); extern void flush_cache_sigtramp(unsigned long address); struct flusher_data { struct vm_area_struct *vma; unsigned long addr1, addr2; }; #define ARCH_HAS_FLUSH_ANON_PAGE extern void __flush_anon_page(struct page *page, unsigned long); static inline void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) { if (boot_cpu_data.dcache.n_aliases && PageAnon(page)) __flush_anon_page(page, vmaddr); } #define ARCH_IMPLEMENTS_FLUSH_KERNEL_VMAP_RANGE 1 static inline void flush_kernel_vmap_range(void *addr, int size) { __flush_wback_region(addr, size); } static inline void invalidate_kernel_vmap_range(void *addr, int size) { __flush_invalidate_region(addr, size); } extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, const void *src, unsigned long len); extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, const void *src, unsigned long len); #define flush_cache_vmap(start, end) local_flush_cache_all(NULL) #define flush_cache_vunmap(start, end) local_flush_cache_all(NULL) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) void kmap_coherent_init(void); void *kmap_coherent(struct page *page, unsigned long addr); void kunmap_coherent(void *kvaddr); #define PG_dcache_clean PG_arch_1 void cpu_cache_init(void); static inline void *sh_cacheop_vaddr(void *vaddr) { if (__in_29bit_mode()) vaddr = (void *)CAC_ADDR((unsigned long)vaddr); return vaddr; } #endif /* __ASM_SH_CACHEFLUSH_H */ PK ! �L�T T include/asm/vmalloc.hnu �[��� #ifndef _ASM_SH_VMALLOC_H #define _ASM_SH_VMALLOC_H #endif /* _ASM_SH_VMALLOC_H */ PK ! ~۹� � include/asm/io_noioport.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_IO_NOIOPORT_H #define __ASM_SH_IO_NOIOPORT_H static inline u8 inb(unsigned long addr) { BUG(); return -1; } static inline u16 inw(unsigned long addr) { BUG(); return -1; } static inline u32 inl(unsigned long addr) { BUG(); return -1; } static inline void outb(unsigned char x, unsigned long port) { BUG(); } static inline void outw(unsigned short x, unsigned long port) { BUG(); } static inline void outl(unsigned int x, unsigned long port) { BUG(); } static inline void __iomem *ioport_map(unsigned long port, unsigned int size) { BUG(); return NULL; } static inline void ioport_unmap(void __iomem *addr) { BUG(); } #define inb_p(addr) inb(addr) #define inw_p(addr) inw(addr) #define inl_p(addr) inl(addr) #define outb_p(x, addr) outb((x), (addr)) #define outw_p(x, addr) outw((x), (addr)) #define outl_p(x, addr) outl((x), (addr)) static inline void insb(unsigned long port, void *dst, unsigned long count) { BUG(); } static inline void insw(unsigned long port, void *dst, unsigned long count) { BUG(); } static inline void insl(unsigned long port, void *dst, unsigned long count) { BUG(); } static inline void outsb(unsigned long port, const void *src, unsigned long count) { BUG(); } static inline void outsw(unsigned long port, const void *src, unsigned long count) { BUG(); } static inline void outsl(unsigned long port, const void *src, unsigned long count) { BUG(); } #endif /* __ASM_SH_IO_NOIOPORT_H */ PK ! ��TG� � include/asm/alignment.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_ALIGNMENT_H #define __ASM_SH_ALIGNMENT_H #include <linux/types.h> extern void inc_unaligned_byte_access(void); extern void inc_unaligned_word_access(void); extern void inc_unaligned_dword_access(void); extern void inc_unaligned_multi_access(void); extern void inc_unaligned_user_access(void); extern void inc_unaligned_kernel_access(void); #define UM_WARN (1 << 0) #define UM_FIXUP (1 << 1) #define UM_SIGNAL (1 << 2) extern unsigned int unaligned_user_action(void); extern void unaligned_fixups_notify(struct task_struct *, insn_size_t, struct pt_regs *); #endif /* __ASM_SH_ALIGNMENT_H */ PK ! ��=X� � include/asm/traps.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_TRAPS_H #define __ASM_SH_TRAPS_H #include <linux/compiler.h> # include <asm/traps_32.h> BUILD_TRAP_HANDLER(address_error); BUILD_TRAP_HANDLER(debug); BUILD_TRAP_HANDLER(bug); BUILD_TRAP_HANDLER(breakpoint); BUILD_TRAP_HANDLER(singlestep); BUILD_TRAP_HANDLER(fpu_error); BUILD_TRAP_HANDLER(fpu_state_restore); BUILD_TRAP_HANDLER(nmi); #endif /* __ASM_SH_TRAPS_H */ PK ! >34�+ + include/asm/page.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PAGE_H #define __ASM_SH_PAGE_H /* * Copyright (C) 1999 Niibe Yutaka */ #include <linux/const.h> /* PAGE_SHIFT determines the page size */ #if defined(CONFIG_PAGE_SIZE_4KB) # define PAGE_SHIFT 12 #elif defined(CONFIG_PAGE_SIZE_8KB) # define PAGE_SHIFT 13 #elif defined(CONFIG_PAGE_SIZE_16KB) # define PAGE_SHIFT 14 #elif defined(CONFIG_PAGE_SIZE_64KB) # define PAGE_SHIFT 16 #else # error "Bogus kernel page size?" #endif #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) #define PTE_MASK PAGE_MASK #if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) #define HPAGE_SHIFT 16 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K) #define HPAGE_SHIFT 18 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) #define HPAGE_SHIFT 20 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) #define HPAGE_SHIFT 22 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB) #define HPAGE_SHIFT 26 #endif #ifdef CONFIG_HUGETLB_PAGE #define HPAGE_SIZE (1UL << HPAGE_SHIFT) #define HPAGE_MASK (~(HPAGE_SIZE-1)) #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT-PAGE_SHIFT) #endif #ifndef __ASSEMBLY__ #include <asm/uncached.h> extern unsigned long shm_align_mask; extern unsigned long max_low_pfn, min_low_pfn; extern unsigned long memory_start, memory_end, memory_limit; static inline unsigned long pages_do_alias(unsigned long addr1, unsigned long addr2) { return (addr1 ^ addr2) & shm_align_mask; } #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) extern void copy_page(void *to, void *from); #define copy_user_page(to, from, vaddr, pg) __copy_user(to, from, PAGE_SIZE) struct page; struct vm_area_struct; extern void copy_user_highpage(struct page *to, struct page *from, unsigned long vaddr, struct vm_area_struct *vma); #define __HAVE_ARCH_COPY_USER_HIGHPAGE extern void clear_user_highpage(struct page *page, unsigned long vaddr); #define clear_user_highpage clear_user_highpage /* * These are used to make use of C type-checking.. */ #ifdef CONFIG_X2TLB typedef struct { unsigned long pte_low, pte_high; } pte_t; typedef struct { unsigned long long pgprot; } pgprot_t; typedef struct { unsigned long long pgd; } pgd_t; #define pte_val(x) \ ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) #define __pte(x) \ ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; }) #else typedef struct { unsigned long pte_low; } pte_t; typedef struct { unsigned long pgprot; } pgprot_t; typedef struct { unsigned long pgd; } pgd_t; #define pte_val(x) ((x).pte_low) #define __pte(x) ((pte_t) { (x) } ) #endif #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) typedef struct page *pgtable_t; #define pte_pgprot(x) __pgprot(pte_val(x) & PTE_FLAGS_MASK) #endif /* !__ASSEMBLY__ */ /* * __MEMORY_START and SIZE are the physical addresses and size of RAM. */ #define __MEMORY_START CONFIG_MEMORY_START #define __MEMORY_SIZE CONFIG_MEMORY_SIZE /* * PHYSICAL_OFFSET is the offset in physical memory where the base * of the kernel is loaded. */ #ifdef CONFIG_PHYSICAL_START #define PHYSICAL_OFFSET (CONFIG_PHYSICAL_START - __MEMORY_START) #else #define PHYSICAL_OFFSET 0 #endif /* * PAGE_OFFSET is the virtual address of the start of kernel address * space. */ #define PAGE_OFFSET CONFIG_PAGE_OFFSET /* * Virtual to physical RAM address translation. * * In 29 bit mode, the physical offset of RAM from address 0 is visible in * the kernel virtual address space, and thus we don't have to take * this into account when translating. However in 32 bit mode this offset * is not visible (it is part of the PMB mapping) and so needs to be * added or subtracted as required. */ #ifdef CONFIG_PMB #define ___pa(x) ((x)-PAGE_OFFSET+__MEMORY_START) #define ___va(x) ((x)+PAGE_OFFSET-__MEMORY_START) #else #define ___pa(x) ((x)-PAGE_OFFSET) #define ___va(x) ((x)+PAGE_OFFSET) #endif #ifndef __ASSEMBLY__ #define __pa(x) ___pa((unsigned long)x) #define __va(x) (void *)___va((unsigned long)x) #endif /* !__ASSEMBLY__ */ #ifdef CONFIG_UNCACHED_MAPPING #if defined(CONFIG_29BIT) #define UNCAC_ADDR(addr) P2SEGADDR(addr) #define CAC_ADDR(addr) P1SEGADDR(addr) #else #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + uncached_start) #define CAC_ADDR(addr) ((addr) - uncached_start + PAGE_OFFSET) #endif #else #define UNCAC_ADDR(addr) ((addr)) #define CAC_ADDR(addr) ((addr)) #endif #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) /* * PFN = physical frame number (ie PFN 0 == physical address 0) * PFN_START is the PFN of the first page of RAM. By defining this we * don't have struct page entries for the portion of address space * between physical address 0 and the start of RAM. */ #define PFN_START (__MEMORY_START >> PAGE_SHIFT) #define ARCH_PFN_OFFSET (PFN_START) #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #ifdef CONFIG_FLATMEM #define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn) #endif #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) #include <asm-generic/memory_model.h> #include <asm-generic/getorder.h> /* * Some drivers need to perform DMA into kmalloc'ed buffers * and so we have to increase the kmalloc minalign for this. */ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES #endif /* __ASM_SH_PAGE_H */ PK ! �-�37 7 include/asm/smp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SMP_H #define __ASM_SH_SMP_H #include <linux/bitops.h> #include <linux/cpumask.h> #include <asm/smp-ops.h> #ifdef CONFIG_SMP #include <linux/atomic.h> #include <asm/current.h> #include <asm/percpu.h> #define raw_smp_processor_id() (current_thread_info()->cpu) /* Map from cpu id to sequential logical cpu number. */ extern int __cpu_number_map[NR_CPUS]; #define cpu_number_map(cpu) __cpu_number_map[cpu] /* The reverse map from sequential logical cpu number to cpu id. */ extern int __cpu_logical_map[NR_CPUS]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] enum { SMP_MSG_FUNCTION, SMP_MSG_RESCHEDULE, SMP_MSG_FUNCTION_SINGLE, SMP_MSG_TIMER, SMP_MSG_NR, /* must be last */ }; DECLARE_PER_CPU(int, cpu_state); void smp_message_recv(unsigned int msg); void arch_send_call_function_single_ipi(int cpu); void arch_send_call_function_ipi_mask(const struct cpumask *mask); void native_play_dead(void); void native_cpu_die(unsigned int cpu); int native_cpu_disable(unsigned int cpu); #ifdef CONFIG_HOTPLUG_CPU void play_dead_common(void); extern int __cpu_disable(void); static inline void __cpu_die(unsigned int cpu) { extern struct plat_smp_ops *mp_ops; /* private */ mp_ops->cpu_die(cpu); } #endif static inline int hard_smp_processor_id(void) { extern struct plat_smp_ops *mp_ops; /* private */ if (!mp_ops) return 0; /* boot CPU */ return mp_ops->smp_processor_id(); } struct of_cpu_method { const char *method; struct plat_smp_ops *ops; }; #define CPU_METHOD_OF_DECLARE(name, _method, _ops) \ static const struct of_cpu_method __cpu_method_of_table_##name \ __used __section("__cpu_method_of_table") \ = { .method = _method, .ops = _ops } #else #define hard_smp_processor_id() (0) #endif /* CONFIG_SMP */ #endif /* __ASM_SH_SMP_H */ PK ! �s�8X X include/asm/unwinder.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _LINUX_UNWINDER_H #define _LINUX_UNWINDER_H #include <asm/stacktrace.h> struct unwinder { const char *name; struct list_head list; int rating; void (*dump)(struct task_struct *, struct pt_regs *, unsigned long *, const struct stacktrace_ops *, void *); }; extern int unwinder_init(void); extern int unwinder_register(struct unwinder *); extern void unwind_stack(struct task_struct *, struct pt_regs *, unsigned long *, const struct stacktrace_ops *, void *); extern void stack_reader_dump(struct task_struct *, struct pt_regs *, unsigned long *, const struct stacktrace_ops *, void *); /* * Used by fault handling code to signal to the unwinder code that it * should switch to a different unwinder. */ extern int unwinder_faulted; #endif /* _LINUX_UNWINDER_H */ PK ! e�|˖ � include/asm/i2c-sh7760.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * MMIO/IRQ and platform data for SH7760 I2C channels */ #ifndef _I2C_SH7760_H_ #define _I2C_SH7760_H_ #define SH7760_I2C_DEVNAME "sh7760-i2c" #define SH7760_I2C0_MMIO 0xFE140000 #define SH7760_I2C0_MMIOEND 0xFE14003B #define SH7760_I2C1_MMIO 0xFE150000 #define SH7760_I2C1_MMIOEND 0xFE15003B struct sh7760_i2c_platdata { unsigned int speed_khz; }; #endif PK ! ��x include/asm/tlbflush.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_TLBFLUSH_H #define __ASM_SH_TLBFLUSH_H /* * TLB flushing: * * - flush_tlb_all() flushes all processes TLBs * - flush_tlb_mm(mm) flushes the specified mm context TLB's * - flush_tlb_page(vma, vmaddr) flushes one page * - flush_tlb_range(vma, start, end) flushes a range of pages * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages */ extern void local_flush_tlb_all(void); extern void local_flush_tlb_mm(struct mm_struct *mm); extern void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); extern void local_flush_tlb_kernel_range(unsigned long start, unsigned long end); extern void local_flush_tlb_one(unsigned long asid, unsigned long page); extern void __flush_tlb_global(void); #ifdef CONFIG_SMP extern void flush_tlb_all(void); extern void flush_tlb_mm(struct mm_struct *mm); extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page); extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); extern void flush_tlb_one(unsigned long asid, unsigned long page); #else #define flush_tlb_all() local_flush_tlb_all() #define flush_tlb_mm(mm) local_flush_tlb_mm(mm) #define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page) #define flush_tlb_one(asid, page) local_flush_tlb_one(asid, page) #define flush_tlb_range(vma, start, end) \ local_flush_tlb_range(vma, start, end) #define flush_tlb_kernel_range(start, end) \ local_flush_tlb_kernel_range(start, end) #endif /* CONFIG_SMP */ #endif /* __ASM_SH_TLBFLUSH_H */ PK ! �<3� � include/asm/stackprotector.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_STACKPROTECTOR_H #define __ASM_SH_STACKPROTECTOR_H #include <linux/random.h> #include <linux/version.h> extern unsigned long __stack_chk_guard; /* * Initialize the stackprotector canary value. * * NOTE: this must only be called from functions that never return, * and it must always be inlined. */ static __always_inline void boot_init_stack_canary(void) { unsigned long canary; /* Try to get a semi random initial value. */ get_random_bytes(&canary, sizeof(canary)); canary ^= LINUX_VERSION_CODE; canary &= CANARY_MASK; current->stack_canary = canary; __stack_chk_guard = current->stack_canary; } #endif /* __ASM_SH_STACKPROTECTOR_H */ PK ! �C�wB B include/asm/smc37c93x.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SMC37C93X_H #define __ASM_SH_SMC37C93X_H /* * linux/include/asm-sh/smc37c93x.h * * Copyright (C) 2000 Kazumoto Kojima * * SMSC 37C93x Super IO Chip support */ /* Default base I/O address */ #define FDC_PRIMARY_BASE 0x3f0 #define IDE1_PRIMARY_BASE 0x1f0 #define IDE1_SECONDARY_BASE 0x170 #define PARPORT_PRIMARY_BASE 0x378 #define COM1_PRIMARY_BASE 0x2f8 #define COM2_PRIMARY_BASE 0x3f8 #define RTC_PRIMARY_BASE 0x070 #define KBC_PRIMARY_BASE 0x060 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */ /* Logical device number */ #define LDN_FDC 0 #define LDN_IDE1 1 #define LDN_IDE2 2 #define LDN_PARPORT 3 #define LDN_COM1 4 #define LDN_COM2 5 #define LDN_RTC 6 #define LDN_KBC 7 #define LDN_AUXIO 8 /* Configuration port and key */ #define CONFIG_PORT 0x3f0 #define INDEX_PORT CONFIG_PORT #define DATA_PORT 0x3f1 #define CONFIG_ENTER 0x55 #define CONFIG_EXIT 0xaa /* Configuration index */ #define CURRENT_LDN_INDEX 0x07 #define POWER_CONTROL_INDEX 0x22 #define ACTIVATE_INDEX 0x30 #define IO_BASE_HI_INDEX 0x60 #define IO_BASE_LO_INDEX 0x61 #define IRQ_SELECT_INDEX 0x70 #define DMA_SELECT_INDEX 0x74 #define GPIO46_INDEX 0xc6 #define GPIO47_INDEX 0xc7 /* UART stuff. Only for debugging. */ /* UART Register */ #define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */ #define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */ #define UART_IER 0x2 /* Interrupt Enable Register */ #define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */ #define UART_FCR 0x4 /* FIFO Control Register (Write Only) */ #define UART_LCR 0x6 /* Line Control Register */ #define UART_MCR 0x8 /* MODEM Control Register */ #define UART_LSR 0xa /* Line Status Register */ #define UART_MSR 0xc /* MODEM Status Register */ #define UART_SCR 0xe /* Scratch Register */ #define UART_DLL 0x0 /* Divisor Latch (LS) */ #define UART_DLM 0x2 /* Divisor Latch (MS) */ #ifndef __ASSEMBLY__ typedef struct uart_reg { volatile __u16 rbr; volatile __u16 ier; volatile __u16 iir; volatile __u16 lcr; volatile __u16 mcr; volatile __u16 lsr; volatile __u16 msr; volatile __u16 scr; } uart_reg; #endif /* ! __ASSEMBLY__ */ /* Alias for Write Only Register */ #define thr rbr #define tcr iir /* Alias for Divisor Latch Register */ #define dll rbr #define dlm ier #define fcr iir /* Interrupt Enable Register */ #define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */ #define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */ #define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */ #define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */ /* Interrupt Ident Register */ #define IIR_IP 0x0100 /* "0" if Interrupt Pending */ #define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */ #define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */ #define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */ #define IIR_FIFO 0xc000 /* FIFOs enabled */ /* FIFO Control Register */ #define FCR_FEN 0x0100 /* FIFO enable */ #define FCR_RFRES 0x0200 /* Receiver FIFO reset */ #define FCR_TFRES 0x0400 /* Transmitter FIFO reset */ #define FCR_DMA 0x0800 /* DMA mode select */ #define FCR_RTL 0x4000 /* Receiver trigger (LSB) */ #define FCR_RTM 0x8000 /* Receiver trigger (MSB) */ /* Line Control Register */ #define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */ #define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */ #define LCR_STB 0x0400 /* Number of Stop Bits */ #define LCR_PEN 0x0800 /* Parity Enable */ #define LCR_EPS 0x1000 /* Even Parity Select */ #define LCR_SP 0x2000 /* Stick Parity */ #define LCR_SB 0x4000 /* Set Break */ #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */ /* MODEM Control Register */ #define MCR_DTR 0x0100 /* Data Terminal Ready */ #define MCR_RTS 0x0200 /* Request to Send */ #define MCR_OUT1 0x0400 /* Out 1 */ #define MCR_IRQEN 0x0800 /* IRQ Enable */ #define MCR_LOOP 0x1000 /* Loop */ /* Line Status Register */ #define LSR_DR 0x0100 /* Data Ready */ #define LSR_OE 0x0200 /* Overrun Error */ #define LSR_PE 0x0400 /* Parity Error */ #define LSR_FE 0x0800 /* Framing Error */ #define LSR_BI 0x1000 /* Break Interrupt */ #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */ #define LSR_TEMT 0x4000 /* Transmitter Empty */ #define LSR_FIFOE 0x8000 /* Receiver FIFO error */ /* MODEM Status Register */ #define MSR_DCTS 0x0100 /* Delta Clear to Send */ #define MSR_DDSR 0x0200 /* Delta Data Set Ready */ #define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */ #define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */ #define MSR_CTS 0x1000 /* Clear to Send */ #define MSR_DSR 0x2000 /* Data Set Ready */ #define MSR_RI 0x4000 /* Ring Indicator */ #define MSR_DCD 0x8000 /* Data Carrier Detect */ /* Baud Rate Divisor */ #define UART_CLK (1843200) /* 1.8432 MHz */ #define UART_BAUD(x) (UART_CLK / (16 * (x))) /* RTC register definition */ #define RTC_SECONDS 0 #define RTC_SECONDS_ALARM 1 #define RTC_MINUTES 2 #define RTC_MINUTES_ALARM 3 #define RTC_HOURS 4 #define RTC_HOURS_ALARM 5 #define RTC_DAY_OF_WEEK 6 #define RTC_DAY_OF_MONTH 7 #define RTC_MONTH 8 #define RTC_YEAR 9 #define RTC_FREQ_SELECT 10 # define RTC_UIP 0x80 # define RTC_DIV_CTL 0x70 /* This RTC can work under 32.768KHz clock only. */ # define RTC_OSC_ENABLE 0x20 # define RTC_OSC_DISABLE 0x00 #define RTC_CONTROL 11 # define RTC_SET 0x80 # define RTC_PIE 0x40 # define RTC_AIE 0x20 # define RTC_UIE 0x10 # define RTC_SQWE 0x08 # define RTC_DM_BINARY 0x04 # define RTC_24H 0x02 # define RTC_DST_EN 0x01 #endif /* __ASM_SH_SMC37C93X_H */ PK ! �E��q q include/asm/tlb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_TLB_H #define __ASM_SH_TLB_H #ifndef __ASSEMBLY__ #include <linux/pagemap.h> #include <asm-generic/tlb.h> #ifdef CONFIG_MMU #include <linux/swap.h> #if defined(CONFIG_CPU_SH4) extern void tlb_wire_entry(struct vm_area_struct *, unsigned long, pte_t); extern void tlb_unwire_entry(void); #else static inline void tlb_wire_entry(struct vm_area_struct *vma , unsigned long addr, pte_t pte) { BUG(); } static inline void tlb_unwire_entry(void) { BUG(); } #endif /* CONFIG_CPU_SH4 */ #endif /* CONFIG_MMU */ #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_TLB_H */ PK ! G�6�S S include/asm/gpio.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/gpio.h * * Generic GPIO API and pinmux table support for SuperH. * * Copyright (c) 2008 Magnus Damm */ #ifndef __ASM_SH_GPIO_H #define __ASM_SH_GPIO_H #include <linux/kernel.h> #include <linux/errno.h> #if defined(CONFIG_CPU_SH3) #include <cpu/gpio.h> #endif #include <asm-generic/gpio.h> #ifdef CONFIG_GPIOLIB static inline int gpio_get_value(unsigned gpio) { return __gpio_get_value(gpio); } static inline void gpio_set_value(unsigned gpio, int value) { __gpio_set_value(gpio, value); } static inline int gpio_cansleep(unsigned gpio) { return __gpio_cansleep(gpio); } static inline int gpio_to_irq(unsigned gpio) { return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned int irq) { return -ENOSYS; } #endif /* CONFIG_GPIOLIB */ #endif /* __ASM_SH_GPIO_H */ PK ! V�9�� � include/asm/thread_info.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_THREAD_INFO_H #define __ASM_SH_THREAD_INFO_H /* SuperH version * Copyright (C) 2002 Niibe Yutaka * * The copyright of original i386 version is: * * Copyright (C) 2002 David Howells (dhowells@redhat.com) * - Incorporating suggestions made by Linus Torvalds and Dave Miller */ #include <asm/page.h> /* * Page fault error code bits */ #define FAULT_CODE_WRITE (1 << 0) /* write access */ #define FAULT_CODE_INITIAL (1 << 1) /* initial page write */ #define FAULT_CODE_ITLB (1 << 2) /* ITLB miss */ #define FAULT_CODE_PROT (1 << 3) /* protection fault */ #define FAULT_CODE_USER (1 << 4) /* user-mode access */ #ifndef __ASSEMBLY__ #include <asm/processor.h> struct thread_info { struct task_struct *task; /* main task structure */ unsigned long flags; /* low level flags */ __u32 status; /* thread synchronous flags */ __u32 cpu; int preempt_count; /* 0 => preemptable, <0 => BUG */ mm_segment_t addr_limit; /* thread address space */ unsigned long previous_sp; /* sp of previous stack in case of nested IRQ stacks */ __u8 supervisor_stack[0]; }; #endif #if defined(CONFIG_4KSTACKS) #define THREAD_SHIFT 12 #else #define THREAD_SHIFT 13 #endif #define THREAD_SIZE (1 << THREAD_SHIFT) #define STACK_WARN (THREAD_SIZE >> 3) /* * macros/functions for gaining access to the thread information structure */ #ifndef __ASSEMBLY__ #define INIT_THREAD_INFO(tsk) \ { \ .task = &tsk, \ .flags = 0, \ .status = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ .addr_limit = KERNEL_DS, \ } /* how to get the current stack pointer from C */ register unsigned long current_stack_pointer asm("r15") __used; /* how to get the thread information struct from C */ static inline struct thread_info *current_thread_info(void) { struct thread_info *ti; #if defined(CONFIG_CPU_HAS_SR_RB) __asm__ __volatile__ ("stc r7_bank, %0" : "=r" (ti)); #else unsigned long __dummy; __asm__ __volatile__ ( "mov r15, %0\n\t" "and %1, %0\n\t" : "=&r" (ti), "=r" (__dummy) : "1" (~(THREAD_SIZE - 1)) : "memory"); #endif return ti; } #define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT) extern void arch_task_cache_init(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); extern void arch_release_task_struct(struct task_struct *tsk); extern void init_thread_xstate(void); #endif /* __ASSEMBLY__ */ /* * Thread information flags * * - Limited to 24 bits, upper byte used for fault code encoding. * * - _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or * we blow the tst immediate size constraints and need to fix up * arch/sh/kernel/entry-common.S. */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_SIGPENDING 1 /* signal pending */ #define TIF_NEED_RESCHED 2 /* rescheduling necessary */ #define TIF_NOTIFY_SIGNAL 3 /* signal notifications exist */ #define TIF_SINGLESTEP 4 /* singlestepping active */ #define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ #define TIF_SECCOMP 6 /* secure computing */ #define TIF_NOTIFY_RESUME 7 /* callback before returning to user */ #define TIF_SYSCALL_TRACEPOINT 8 /* for ftrace syscall instrumentation */ #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) #define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) /* work to do in syscall trace */ #define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \ _TIF_SYSCALL_TRACEPOINT) /* work to do on any return to u-space */ #define _TIF_ALLWORK_MASK (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING | \ _TIF_NEED_RESCHED | _TIF_SYSCALL_AUDIT | \ _TIF_SINGLESTEP | _TIF_NOTIFY_RESUME | \ _TIF_SYSCALL_TRACEPOINT | _TIF_NOTIFY_SIGNAL) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \ _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP)) /* * Thread-synchronous status. * * This is different from the flags in that nobody else * ever touches our thread-synchronous status, so we don't * have to worry about atomic accesses. */ #define TS_USEDFPU 0x0002 /* FPU used by this task this quantum */ #ifndef __ASSEMBLY__ #define TI_FLAG_FAULT_CODE_SHIFT 24 /* * Additional thread flag encoding */ static inline void set_thread_fault_code(unsigned int val) { struct thread_info *ti = current_thread_info(); ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT))) | (val << TI_FLAG_FAULT_CODE_SHIFT); } static inline unsigned int get_thread_fault_code(void) { struct thread_info *ti = current_thread_info(); return ti->flags >> TI_FLAG_FAULT_CODE_SHIFT; } #endif /* !__ASSEMBLY__ */ #endif /* __ASM_SH_THREAD_INFO_H */ PK ! j[��$/ $/ include/asm/hd64461.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HD64461 #define __ASM_SH_HD64461 /* * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> * Copyright (C) 2004 Paul Mundt * Copyright (C) 2000 YAEGASHI Takeshi * * Hitachi HD64461 companion chip support * (please note manual reference 0x10000000 = 0xb0000000) */ /* Constants for PCMCIA mappings */ #define HD64461_PCC_WINDOW 0x01000000 /* Area 6 - Slot 0 - memory and/or IO card */ #define HD64461_IOBASE 0xb0000000 #define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x)) #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000) #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ /* Area 5 - Slot 1 - memory card only */ #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000) #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ /* Standby Control Register for HD64461 */ #define HD64461_STBCR HD64461_IO_OFFSET(0x00000000) #define HD64461_STBCR_CKIO_STBY 0x2000 #define HD64461_STBCR_SAFECKE_IST 0x1000 #define HD64461_STBCR_SLCKE_IST 0x0800 #define HD64461_STBCR_SAFECKE_OST 0x0400 #define HD64461_STBCR_SLCKE_OST 0x0200 #define HD64461_STBCR_SMIAST 0x0100 #define HD64461_STBCR_SLCDST 0x0080 #define HD64461_STBCR_SPC0ST 0x0040 #define HD64461_STBCR_SPC1ST 0x0020 #define HD64461_STBCR_SAFEST 0x0010 #define HD64461_STBCR_STM0ST 0x0008 #define HD64461_STBCR_STM1ST 0x0004 #define HD64461_STBCR_SIRST 0x0002 #define HD64461_STBCR_SURTST 0x0001 /* System Configuration Register */ #define HD64461_SYSCR HD64461_IO_OFFSET(0x02) /* CPU Data Bus Control Register */ #define HD64461_SCPUCR HD64461_IO_OFFSET(0x04) /* Base Address Register */ #define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000) /* Line increment address */ #define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002) /* Controls LCD controller */ #define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004) /* LCCDR control bits */ #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ /* Controls LCD (1) */ #define HD64461_LDR1 HD64461_IO_OFFSET(0x1010) #define HD64461_LDR1_DON 0x01 /* Display On */ #define HD64461_LDR1_DINV 0x80 /* Display Invert */ /* Controls LCD (2) */ #define HD64461_LDR2 HD64461_IO_OFFSET(0x1012) #define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */ #define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */ #define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */ #define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */ #define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */ /* Controls LCD (3) */ #define HD64461_LDR3 HD64461_IO_OFFSET(0x101e) /* Palette Registers */ #define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */ #define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */ #define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */ #define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */ #define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */ #define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */ #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */ #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ /* Line Drawing Registers */ #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */ #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */ #define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */ #define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */ #define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */ #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */ #define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */ /* BitBLT Registers */ #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */ #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */ #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */ #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */ #define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */ #define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */ #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */ #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */ #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */ #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */ #define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */ #define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */ /* PC Card Controller Registers */ /* Maps to Physical Area 6 */ #define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */ #define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */ #define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */ #define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */ #define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */ /* Maps to Physical Area 5 */ #define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */ #define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */ #define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */ #define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */ #define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */ /* PCC Interface Status Register */ #define HD64461_PCCISR_READY 0x80 /* card ready */ #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ /* PCC General Control Register */ #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ /* PCC Card Status Change Register */ #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ #define HD64461_PCCCSCR_RC 0x04 /* READY change */ #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ /* PCC Card Status Change Interrupt Enable Register */ #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ /* PCC Software Control Register */ #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ #define HD64461_PCCSCR_SWP 0x01 /* write protect */ /* PCC0 Output Pins Control Register */ #define HD64461_P0OCR HD64461_IO_OFFSET(0x202a) /* PCC1 Output Pins Control Register */ #define HD64461_P1OCR HD64461_IO_OFFSET(0x202c) /* PC Card General Control Register */ #define HD64461_PGCR HD64461_IO_OFFSET(0x202e) /* Port Control Registers */ #define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */ #define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */ #define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */ #define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */ /* Port Control Data Registers */ #define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */ #define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */ #define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */ #define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */ /* Interrupt Control Registers */ #define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */ #define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */ #define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */ #define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */ /* Interrupt Status Registers */ #define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */ #define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */ #define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */ #define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */ /* Interrupt Request Register & Interrupt Mask Register */ #define HD64461_NIRR HD64461_IO_OFFSET(0x5000) #define HD64461_NIMR HD64461_IO_OFFSET(0x5002) #define HD64461_IRQBASE OFFCHIP_IRQ_BASE #define OFFCHIP_IRQ_BASE 64 #define HD64461_IRQ_NUM 16 #define HD64461_IRQ_UART (HD64461_IRQBASE+5) #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) #define __IO_PREFIX hd64461 #include <asm/io_generic.h> /* arch/sh/cchips/hd6446x/hd64461/setup.c */ void hd64461_register_irq_demux(int irq, int (*demux) (int irq, void *dev), void *dev); void hd64461_unregister_irq_demux(int irq); #endif PK ! ~d� � include/asm/clock.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CLOCK_H #define __ASM_SH_CLOCK_H #include <linux/sh_clk.h> /* Should be defined by processor-specific code */ void __deprecated arch_init_clk_ops(struct sh_clk_ops **, int type); int __init arch_clk_init(void); /* arch/sh/kernel/cpu/clock-cpg.c */ int __init __deprecated cpg_clk_init(void); /* arch/sh/kernel/cpu/clock.c */ int clk_init(void); #endif /* __ASM_SH_CLOCK_H */ PK ! #��f include/asm/processor_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * include/asm-sh/processor.h * * Copyright (C) 1999, 2000 Niibe Yutaka * Copyright (C) 2002, 2003 Paul Mundt */ #ifndef __ASM_SH_PROCESSOR_32_H #define __ASM_SH_PROCESSOR_32_H #include <linux/compiler.h> #include <linux/linkage.h> #include <asm/page.h> #include <asm/types.h> #include <asm/hw_breakpoint.h> /* Core Processor Version Register */ #define CCN_PVR 0xff000030 #define CCN_CVR 0xff000040 #define CCN_PRR 0xff000044 /* * User space process size: 2GB. * * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff */ #define TASK_SIZE 0x7c000000UL #define STACK_TOP TASK_SIZE #define STACK_TOP_MAX STACK_TOP /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) /* * Bit of SR register * * FD-bit: * When it's set, it means the processor doesn't have right to use FPU, * and it results exception when the floating operation is executed. * * IMASK-bit: * Interrupt level mask */ #define SR_DSP 0x00001000 #define SR_IMASK 0x000000f0 #define SR_FD 0x00008000 #define SR_MD 0x40000000 #define SR_USER_MASK 0x00000303 // M, Q, S, T bits /* * DSP structure and data */ struct sh_dsp_struct { unsigned long dsp_regs[14]; long status; }; /* * FPU structure and data */ struct sh_fpu_hard_struct { unsigned long fp_regs[16]; unsigned long xfp_regs[16]; unsigned long fpscr; unsigned long fpul; long status; /* software status information */ }; /* Dummy fpu emulator */ struct sh_fpu_soft_struct { unsigned long fp_regs[16]; unsigned long xfp_regs[16]; unsigned long fpscr; unsigned long fpul; unsigned char lookahead; unsigned long entry_pc; }; union thread_xstate { struct sh_fpu_hard_struct hardfpu; struct sh_fpu_soft_struct softfpu; }; struct thread_struct { /* Saved registers when thread is descheduled */ unsigned long sp; unsigned long pc; /* Various thread flags, see SH_THREAD_xxx */ unsigned long flags; /* Save middle states of ptrace breakpoints */ struct perf_event *ptrace_bps[HBP_NUM]; #ifdef CONFIG_SH_DSP /* Dsp status information */ struct sh_dsp_struct dsp_status; #endif /* Extended processor state */ union thread_xstate *xstate; /* * fpu_counter contains the number of consecutive context switches * that the FPU is used. If this is over a threshold, the lazy fpu * saving becomes unlazy to save the trap. This is an unsigned char * so that after 256 times the counter wraps and the behavior turns * lazy again; this to deal with bursty apps that only use FPU for * a short time */ unsigned char fpu_counter; }; #define INIT_THREAD { \ .sp = sizeof(init_stack) + (long) &init_stack, \ .flags = 0, \ } /* Forward declaration, a strange C thing */ struct task_struct; extern void start_thread(struct pt_regs *regs, unsigned long new_pc, unsigned long new_sp); /* Free all resources held by a thread. */ extern void release_thread(struct task_struct *); /* * FPU lazy state save handling. */ static __inline__ void disable_fpu(void) { unsigned long __dummy; /* Set FD flag in SR */ __asm__ __volatile__("stc sr, %0\n\t" "or %1, %0\n\t" "ldc %0, sr" : "=&r" (__dummy) : "r" (SR_FD)); } static __inline__ void enable_fpu(void) { unsigned long __dummy; /* Clear out FD flag in SR */ __asm__ __volatile__("stc sr, %0\n\t" "and %1, %0\n\t" "ldc %0, sr" : "=&r" (__dummy) : "r" (~SR_FD)); } /* Double presision, NANS as NANS, rounding to nearest, no exceptions */ #define FPSCR_INIT 0x00080000 #define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */ #define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */ /* * Return saved PC of a blocked thread. */ #define thread_saved_pc(tsk) (tsk->thread.pc) void show_trace(struct task_struct *tsk, unsigned long *sp, struct pt_regs *regs, const char *loglvl); #ifdef CONFIG_DUMP_CODE void show_code(struct pt_regs *regs); #else static inline void show_code(struct pt_regs *regs) { } #endif extern unsigned long __get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15]) #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) #define PREFETCH_STRIDE L1_CACHE_BYTES #define ARCH_HAS_PREFETCH #define ARCH_HAS_PREFETCHW static inline void prefetch(const void *x) { __builtin_prefetch(x, 0, 3); } static inline void prefetchw(const void *x) { __builtin_prefetch(x, 1, 3); } #endif #endif /* __ASM_SH_PROCESSOR_32_H */ PK ! j�=�� � include/asm/processor.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PROCESSOR_H #define __ASM_SH_PROCESSOR_H #include <asm/cpu-features.h> #include <asm/segment.h> #include <asm/cache.h> #ifndef __ASSEMBLY__ /* * CPU type and hardware bug flags. Kept separately for each CPU. * * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c * for parsing the subtype in get_cpu_subtype(). */ enum cpu_type { /* SH-2 types */ CPU_SH7619, CPU_J2, /* SH-2A types */ CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269, CPU_MXG, /* SH-3 types */ CPU_SH7705, CPU_SH7706, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R, CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, CPU_SH7720, CPU_SH7721, CPU_SH7729, /* SH-4 types */ CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, CPU_SH7760, CPU_SH4_202, CPU_SH4_501, /* SH-4A types */ CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3, /* SH4AL-DSP types */ CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, /* Unknown subtype */ CPU_SH_NONE }; enum cpu_family { CPU_FAMILY_SH2, CPU_FAMILY_SH2A, CPU_FAMILY_SH3, CPU_FAMILY_SH4, CPU_FAMILY_SH4A, CPU_FAMILY_SH4AL_DSP, CPU_FAMILY_UNKNOWN, }; /* * TLB information structure * * Defined for both I and D tlb, per-processor. */ struct tlb_info { unsigned long long next; unsigned long long first; unsigned long long last; unsigned int entries; unsigned int step; unsigned long flags; }; struct sh_cpuinfo { unsigned int type, family; int cut_major, cut_minor; unsigned long loops_per_jiffy; unsigned long asid_cache; struct cache_info icache; /* Primary I-cache */ struct cache_info dcache; /* Primary D-cache */ struct cache_info scache; /* Secondary cache */ /* TLB info */ struct tlb_info itlb; struct tlb_info dtlb; unsigned int phys_bits; unsigned long flags; } __attribute__ ((aligned(L1_CACHE_BYTES))); extern struct sh_cpuinfo cpu_data[]; #define boot_cpu_data cpu_data[0] #define current_cpu_data cpu_data[smp_processor_id()] #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") #define cpu_relax() barrier() void default_idle(void); void stop_this_cpu(void *); /* Forward decl */ struct seq_operations; struct task_struct; extern struct pt_regs fake_swapper_regs; extern void cpu_init(void); extern void cpu_probe(void); /* arch/sh/kernel/process.c */ extern unsigned int xstate_size; extern void free_thread_xstate(struct task_struct *); extern struct kmem_cache *task_xstate_cachep; /* arch/sh/mm/alignment.c */ extern int get_unalign_ctl(struct task_struct *, unsigned long addr); extern int set_unalign_ctl(struct task_struct *, unsigned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) /* arch/sh/mm/init.c */ extern unsigned int mem_init_done; /* arch/sh/kernel/setup.c */ const char *get_cpu_subtype(struct sh_cpuinfo *c); extern const struct seq_operations cpuinfo_op; /* thread_struct flags */ #define SH_THREAD_UAC_NOPRINT (1 << 0) #define SH_THREAD_UAC_SIGBUS (1 << 1) #define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS) /* processor boot mode configuration */ #define MODE_PIN0 (1 << 0) #define MODE_PIN1 (1 << 1) #define MODE_PIN2 (1 << 2) #define MODE_PIN3 (1 << 3) #define MODE_PIN4 (1 << 4) #define MODE_PIN5 (1 << 5) #define MODE_PIN6 (1 << 6) #define MODE_PIN7 (1 << 7) #define MODE_PIN8 (1 << 8) #define MODE_PIN9 (1 << 9) #define MODE_PIN10 (1 << 10) #define MODE_PIN11 (1 << 11) #define MODE_PIN12 (1 << 12) #define MODE_PIN13 (1 << 13) #define MODE_PIN14 (1 << 14) #define MODE_PIN15 (1 << 15) int generic_mode_pins(void); int test_mode_pin(int pin); #ifdef CONFIG_VSYSCALL int vsyscall_init(void); #else #define vsyscall_init() do { } while (0) #endif /* * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks. */ #ifdef CONFIG_CPU_SH2A extern unsigned int instruction_size(unsigned int insn); #else #define instruction_size(insn) (2) #endif void select_idle_routine(void); #endif /* __ASSEMBLY__ */ #include <asm/processor_32.h> #endif /* __ASM_SH_PROCESSOR_H */ PK ! c�� � include/asm/syscalls_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SYSCALLS_32_H #define __ASM_SH_SYSCALLS_32_H #include <linux/compiler.h> #include <linux/linkage.h> #include <linux/types.h> struct pt_regs; asmlinkage int sys_sigreturn(void); asmlinkage int sys_rt_sigreturn(void); asmlinkage int sys_sh_pipe(void); asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char __user *buf, size_t count, long dummy, loff_t pos); asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char __user *buf, size_t count, long dummy, loff_t pos); asmlinkage int sys_fadvise64_64_wrapper(int fd, u32 offset0, u32 offset1, u32 len0, u32 len1, int advice); /* Misc syscall related bits */ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs); asmlinkage void do_syscall_trace_leave(struct pt_regs *regs); asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned int save_r0, unsigned long thread_info_flags); #endif /* __ASM_SH_SYSCALLS_32_H */ PK ! Vi�C include/asm/kprobes.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_KPROBES_H #define __ASM_SH_KPROBES_H #include <asm-generic/kprobes.h> #define BREAKPOINT_INSTRUCTION 0xc33a #ifdef CONFIG_KPROBES #include <linux/types.h> #include <linux/ptrace.h> typedef insn_size_t kprobe_opcode_t; #define MAX_INSN_SIZE 16 #define MAX_STACK_SIZE 64 #define MIN_STACK_SIZE(ADDR) (((MAX_STACK_SIZE) < \ (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) \ ? (MAX_STACK_SIZE) \ : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) #define flush_insn_slot(p) do { } while (0) #define kretprobe_blacklist_size 0 struct kprobe; void arch_remove_kprobe(struct kprobe *); void __kretprobe_trampoline(void); /* Architecture specific copy of original instruction*/ struct arch_specific_insn { /* copy of the original instruction */ kprobe_opcode_t insn[MAX_INSN_SIZE]; }; struct prev_kprobe { struct kprobe *kp; unsigned long status; }; /* per-cpu kprobe control block */ struct kprobe_ctlblk { unsigned long kprobe_status; struct prev_kprobe prev_kprobe; }; extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr); extern int kprobe_exceptions_notify(struct notifier_block *self, unsigned long val, void *data); extern int kprobe_handle_illslot(unsigned long pc); #else #define kprobe_handle_illslot(pc) (-1) #endif /* CONFIG_KPROBES */ #endif /* __ASM_SH_KPROBES_H */ PK ! V;E�� � include/asm/sfp-machine.hnu �[��� /* SPDX-License-Identifier: GPL-2.0+ * * Machine-dependent software floating-point definitions. SuperH kernel version. Copyright (C) 1997,1998,1999 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Richard Henderson (rth@cygnus.com), Jakub Jelinek (jj@ultra.linux.cz), David S. Miller (davem@redhat.com) and Peter Maydell (pmaydell@chiark.greenend.org.uk). */ #ifndef _SFP_MACHINE_H #define _SFP_MACHINE_H #ifdef __BIG_ENDIAN__ #define __BYTE_ORDER __BIG_ENDIAN #define __LITTLE_ENDIAN 0 #else #define __BYTE_ORDER __LITTLE_ENDIAN #define __BIG_ENDIAN 0 #endif #define _FP_W_TYPE_SIZE 32 #define _FP_W_TYPE unsigned long #define _FP_WS_TYPE signed long #define _FP_I_TYPE long #define _FP_MUL_MEAT_S(R,X,Y) \ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) #define _FP_MUL_MEAT_D(R,X,Y) \ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) #define _FP_MUL_MEAT_Q(R,X,Y) \ _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) #define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y) #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) #define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) #define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 #define _FP_NANSIGN_S 0 #define _FP_NANSIGN_D 0 #define _FP_NANSIGN_Q 0 #define _FP_KEEPNANFRACP 1 /* * If one NaN is signaling and the other is not, * we choose that one, otherwise we choose X. */ #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ do { \ if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \ { \ R##_s = Y##_s; \ _FP_FRAC_COPY_##wc(R,Y); \ } \ else \ { \ R##_s = X##_s; \ _FP_FRAC_COPY_##wc(R,X); \ } \ R##_c = FP_CLS_NAN; \ } while (0) //#define FP_ROUNDMODE FPSCR_RM #define FP_DENORM_ZERO 1/*FPSCR_DN*/ /* Exception flags. */ #define FP_EX_INVALID (1<<4) #define FP_EX_DIVZERO (1<<3) #define FP_EX_OVERFLOW (1<<2) #define FP_EX_UNDERFLOW (1<<1) #define FP_EX_INEXACT (1<<0) #endif PK ! v �S� � include/asm/spinlock.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/spinlock.h * * Copyright (C) 2002, 2003 Paul Mundt * Copyright (C) 2006, 2007 Akio Idehara */ #ifndef __ASM_SH_SPINLOCK_H #define __ASM_SH_SPINLOCK_H #if defined(CONFIG_CPU_SH4A) #include <asm/spinlock-llsc.h> #elif defined(CONFIG_CPU_J2) #include <asm/spinlock-cas.h> #else #error "The configured cpu type does not support spinlocks" #endif #endif /* __ASM_SH_SPINLOCK_H */ PK ! �IP�5 5 include/asm/cmpxchg-grb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CMPXCHG_GRB_H #define __ASM_SH_CMPXCHG_GRB_H static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) { unsigned long retval; __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " nop \n\t" " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-4, r15 \n\t" /* LOGIN */ " mov.l @%1, %0 \n\t" /* load old value */ " mov.l %2, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (retval), "+r" (m), "+r" (val) /* inhibit r15 overloading */ : : "memory", "r0", "r1"); return retval; } static inline unsigned long xchg_u16(volatile u16 *m, unsigned long val) { unsigned long retval; __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-6, r15 \n\t" /* LOGIN */ " mov.w @%1, %0 \n\t" /* load old value */ " extu.w %0, %0 \n\t" /* extend as unsigned */ " mov.w %2, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (retval), "+r" (m), "+r" (val) /* inhibit r15 overloading */ : : "memory" , "r0", "r1"); return retval; } static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) { unsigned long retval; __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-6, r15 \n\t" /* LOGIN */ " mov.b @%1, %0 \n\t" /* load old value */ " extu.b %0, %0 \n\t" /* extend as unsigned */ " mov.b %2, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (retval), "+r" (m), "+r" (val) /* inhibit r15 overloading */ : : "memory" , "r0", "r1"); return retval; } static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new) { unsigned long retval; __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " nop \n\t" " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-8, r15 \n\t" /* LOGIN */ " mov.l @%3, %0 \n\t" /* load old value */ " cmp/eq %0, %1 \n\t" " bf 1f \n\t" /* if not equal */ " mov.l %2, @%3 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (retval), "+r" (old), "+r" (new) /* old or new can be r15 */ : "r" (m) : "memory" , "r0", "r1", "t"); return retval; } #endif /* __ASM_SH_CMPXCHG_GRB_H */ PK ! '+�� � include/asm/futex-irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_FUTEX_IRQ_H #define __ASM_SH_FUTEX_IRQ_H static inline int atomic_futex_op_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { unsigned long flags; int ret; u32 prev = 0; local_irq_save(flags); ret = get_user(prev, uaddr); if (!ret && oldval == prev) ret = put_user(newval, uaddr); local_irq_restore(flags); *uval = prev; return ret; } #endif /* __ASM_SH_FUTEX_IRQ_H */ PK ! t��� � include/asm/vermagic.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_VERMAGIC_H #define _ASM_VERMAGIC_H #ifdef CONFIG_CPU_LITTLE_ENDIAN # ifdef CONFIG_CPU_SH2 # define MODULE_PROC_FAMILY "SH2LE " # elif defined CONFIG_CPU_SH3 # define MODULE_PROC_FAMILY "SH3LE " # elif defined CONFIG_CPU_SH4 # define MODULE_PROC_FAMILY "SH4LE " # else # error unknown processor family # endif #else # ifdef CONFIG_CPU_SH2 # define MODULE_PROC_FAMILY "SH2BE " # elif defined CONFIG_CPU_SH3 # define MODULE_PROC_FAMILY "SH3BE " # elif defined CONFIG_CPU_SH4 # define MODULE_PROC_FAMILY "SH4BE " # else # error unknown processor family # endif #endif #define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY #endif /* _ASM_VERMAGIC_H */ PK ! ��j�G G include/asm/posix_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <asm/posix_types_32.h> PK ! HuF F include/asm/types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_TYPES_H #define __ASM_SH_TYPES_H #include <uapi/asm/types.h> /* * These aren't exported outside the kernel to avoid name space clashes */ #ifndef __ASSEMBLY__ typedef u16 insn_size_t; typedef u32 reg_size_t; #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_TYPES_H */ PK ! 3i� include/asm/mmzone.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_MMZONE_H #define __ASM_SH_MMZONE_H #ifdef CONFIG_NUMA #include <linux/numa.h> extern struct pglist_data *node_data[]; #define NODE_DATA(nid) (node_data[nid]) static inline int pfn_to_nid(unsigned long pfn) { int nid; for (nid = 0; nid < MAX_NUMNODES; nid++) if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid)) break; return nid; } static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn) { return NODE_DATA(pfn_to_nid(pfn)); } /* arch/sh/mm/numa.c */ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end); #else static inline void setup_bootmem_node(int nid, unsigned long start, unsigned long end) { } #endif /* CONFIG_NUMA */ /* Platform specific mem init */ void __init plat_mem_setup(void); /* arch/sh/kernel/setup.c */ void __init __add_active_range(unsigned int nid, unsigned long start_pfn, unsigned long end_pfn); /* arch/sh/mm/init.c */ void __init allocate_pgdat(unsigned int nid); #endif /* __ASM_SH_MMZONE_H */ PK ! �\3 3 include/asm/ptrace_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PTRACE_32_H #define __ASM_SH_PTRACE_32_H #include <uapi/asm/ptrace_32.h> #define MAX_REG_OFFSET offsetof(struct pt_regs, tra) static inline long regs_return_value(struct pt_regs *regs) { return regs->regs[0]; } #endif /* __ASM_SH_PTRACE_32_H */ PK ! � p� � include/asm/user.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_USER_H #define __ASM_SH_USER_H #include <asm/ptrace.h> #include <asm/page.h> /* * Core file format: The core file is written in such a way that gdb * can understand it and provide useful information to the user (under * linux we use the `trad-core' bfd). The file contents are as follows: * * upage: 1 page consisting of a user struct that tells gdb * what is present in the file. Directly after this is a * copy of the task_struct, which is currently not used by gdb, * but it may come in handy at some point. All of the registers * are stored as part of the upage. The upage should always be * only one page long. * data: The data segment follows next. We use current->end_text to * current->brk to pick up all of the user variables, plus any memory * that may have been sbrk'ed. No attempt is made to determine if a * page is demand-zero or if a page is totally unused, we just cover * the entire range. All of the addresses are rounded in such a way * that an integral number of pages is written. * stack: We need the stack information in order to get a meaningful * backtrace. We need to write the data from usp to * current->start_stack, so we round each of these in order to be able * to write an integer number of pages. */ struct user_fpu_struct { unsigned long fp_regs[16]; unsigned long xfp_regs[16]; unsigned long fpscr; unsigned long fpul; }; struct user { struct pt_regs regs; /* entire machine state */ struct user_fpu_struct fpu; /* Math Co-processor registers */ int u_fpvalid; /* True if math co-processor being used */ size_t u_tsize; /* text size (pages) */ size_t u_dsize; /* data size (pages) */ size_t u_ssize; /* stack size (pages) */ unsigned long start_code; /* text starting address */ unsigned long start_data; /* data starting address */ unsigned long start_stack; /* stack starting address */ long int signal; /* signal causing core dump */ unsigned long u_ar0; /* help gdb find registers */ struct user_fpu_struct* u_fpstate; /* Math Co-processor pointer */ unsigned long magic; /* identifies a core file */ char u_comm[32]; /* user command name */ }; #define NBPG PAGE_SIZE #define UPAGES 1 #define HOST_TEXT_START_ADDR (u.start_code) #define HOST_DATA_START_ADDR (u.start_data) #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) #endif /* __ASM_SH_USER_H */ PK ! �15? ? include/asm/sparsemem.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SPARSEMEM_H #define __ASM_SH_SPARSEMEM_H /* * SECTION_SIZE_BITS 2^N: how big each section will be * MAX_PHYSMEM_BITS 2^N: how much physical address space we have */ #define SECTION_SIZE_BITS 26 #define MAX_PHYSMEM_BITS 32 #endif /* __ASM_SH_SPARSEMEM_H */ PK ! �$�\ \ include/asm/segment.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SEGMENT_H #define __ASM_SH_SEGMENT_H #ifndef __ASSEMBLY__ typedef struct { unsigned long seg; } mm_segment_t; #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) /* * The fs value determines whether argument validity checking should be * performed or not. If get_fs() == USER_DS, checking is performed, with * get_fs() == KERNEL_DS, checking is bypassed. * * For historical reasons, these macros are grossly misnamed. */ #define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFFUL) #ifdef CONFIG_MMU #define USER_DS MAKE_MM_SEG(PAGE_OFFSET) #else #define USER_DS KERNEL_DS #endif #define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) #define get_fs() (current_thread_info()->addr_limit) #define set_fs(x) (current_thread_info()->addr_limit = (x)) #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_SEGMENT_H */ PK ! ��K� include/asm/heartbeat.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HEARTBEAT_H #define __ASM_SH_HEARTBEAT_H #include <linux/timer.h> #define HEARTBEAT_INVERTED (1 << 0) struct heartbeat_data { void __iomem *base; unsigned char *bit_pos; unsigned int nr_bits; struct timer_list timer; unsigned int regsize; unsigned int mask; unsigned long flags; }; #endif /* __ASM_SH_HEARTBEAT_H */ PK ! ��Xe include/asm/perf_event.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PERF_EVENT_H #define __ASM_SH_PERF_EVENT_H struct hw_perf_event; #define MAX_HWEVENTS 2 struct sh_pmu { const char *name; unsigned int num_events; void (*disable_all)(void); void (*enable_all)(void); void (*enable)(struct hw_perf_event *, int); void (*disable)(struct hw_perf_event *, int); u64 (*read)(int); int (*event_map)(int); unsigned int max_events; unsigned long raw_event_mask; const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; }; /* arch/sh/kernel/perf_event.c */ extern int register_sh_pmu(struct sh_pmu *); extern int reserve_pmc_hardware(void); extern void release_pmc_hardware(void); #endif /* __ASM_SH_PERF_EVENT_H */ PK ! �5�f f include/asm/romimage-macros.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ROMIMAGE_MACRO_H #define __ROMIMAGE_MACRO_H /* The LIST command is used to include comments in the script */ .macro LIST comment .endm /* The ED command is used to write a 32-bit word */ .macro ED, addr, data mov.l 1f, r1 mov.l 2f, r0 mov.l r0, @r1 bra 3f nop .align 2 1 : .long \addr 2 : .long \data 3 : .endm /* The EW command is used to write a 16-bit word */ .macro EW, addr, data mov.l 1f, r1 mov.l 2f, r0 mov.w r0, @r1 bra 3f nop .align 2 1 : .long \addr 2 : .long \data 3 : .endm /* The EB command is used to write an 8-bit word */ .macro EB, addr, data mov.l 1f, r1 mov.l 2f, r0 mov.b r0, @r1 bra 3f nop .align 2 1 : .long \addr 2 : .long \data 3 : .endm /* The WAIT command is used to delay the execution */ .macro WAIT, time mov.l 2f, r3 1 : nop tst r3, r3 bf/s 1b dt r3 bra 3f nop .align 2 2 : .long \time * 100 3 : .endm /* The DD command is used to read a 32-bit word */ .macro DD, addr, addr2, nr mov.l 1f, r1 mov.l @r1, r0 bra 2f nop .align 2 1 : .long \addr 2 : .endm #endif /* __ROMIMAGE_MACRO_H */ PK ! �𡵱 � include/asm/kdebug.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_KDEBUG_H #define __ASM_SH_KDEBUG_H /* Grossly misnamed. */ enum die_val { DIE_TRAP, DIE_NMI, DIE_OOPS, DIE_BREAKPOINT, DIE_SSTEP, }; /* arch/sh/kernel/dumpstack.c */ extern void printk_address(unsigned long address, int reliable); extern void dump_mem(const char *str, const char *loglvl, unsigned long bottom, unsigned long top); #endif /* __ASM_SH_KDEBUG_H */ PK ! p٘�� � include/asm/barrier.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima * Copyright (C) 2002 Paul Mundt */ #ifndef __ASM_SH_BARRIER_H #define __ASM_SH_BARRIER_H #if defined(CONFIG_CPU_SH4A) #include <asm/cache_insns.h> #endif /* * A brief note on ctrl_barrier(), the control register write barrier. * * Legacy SH cores typically require a sequence of 8 nops after * modification of a control register in order for the changes to take * effect. On newer cores (like the sh4a and sh5) this is accomplished * with icbi. * * Also note that on sh4a in the icbi case we can forego a synco for the * write barrier, as it's not necessary for control registers. * * Historically we have only done this type of barrier for the MMUCR, but * it's also necessary for the CCR, so we make it generic here instead. */ #if defined(CONFIG_CPU_SH4A) #define mb() __asm__ __volatile__ ("synco": : :"memory") #define rmb() mb() #define wmb() mb() #define ctrl_barrier() __icbi(PAGE_OFFSET) #else #if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) #define __smp_mb() do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0) #define __smp_rmb() __smp_mb() #define __smp_wmb() __smp_mb() #endif #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") #endif #define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) #include <asm-generic/barrier.h> #endif /* __ASM_SH_BARRIER_H */ PK ! �j�6* * include/asm/bitops-llsc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BITOPS_LLSC_H #define __ASM_SH_BITOPS_LLSC_H static inline void set_bit(int nr, volatile void *addr) { int mask; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! set_bit \n\t" "or %2, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (a), "r" (mask) : "t", "memory" ); } static inline void clear_bit(int nr, volatile void *addr) { int mask; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! clear_bit \n\t" "and %2, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (a), "r" (~mask) : "t", "memory" ); } static inline void change_bit(int nr, volatile void *addr) { int mask; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! change_bit \n\t" "xor %2, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (a), "r" (mask) : "t", "memory" ); } static inline int test_and_set_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! test_and_set_bit \n\t" "mov %0, %1 \n\t" "or %3, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "and %3, %1 \n\t" : "=&z" (tmp), "=&r" (retval) : "r" (a), "r" (mask) : "t", "memory" ); return retval != 0; } static inline int test_and_clear_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! test_and_clear_bit \n\t" "mov %0, %1 \n\t" "and %4, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "and %3, %1 \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (retval) : "r" (a), "r" (mask), "r" (~mask) : "t", "memory" ); return retval != 0; } static inline int test_and_change_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! test_and_change_bit \n\t" "mov %0, %1 \n\t" "xor %3, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "and %3, %1 \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (retval) : "r" (a), "r" (mask) : "t", "memory" ); return retval != 0; } #include <asm-generic/bitops/non-atomic.h> #endif /* __ASM_SH_BITOPS_LLSC_H */ PK ! ��i � � include/asm/linkage.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_LINKAGE_H #define __ASM_LINKAGE_H #define __ALIGN .balign 4 #define __ALIGN_STR ".balign 4" #endif PK ! SO\iG G include/asm/mmu_context.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 1999 Niibe Yutaka * Copyright (C) 2003 - 2007 Paul Mundt * * ASID handling idea taken from MIPS implementation. */ #ifndef __ASM_SH_MMU_CONTEXT_H #define __ASM_SH_MMU_CONTEXT_H #include <cpu/mmu_context.h> #include <asm/tlbflush.h> #include <linux/uaccess.h> #include <linux/mm_types.h> #include <asm/io.h> #include <asm-generic/mm_hooks.h> /* * The MMU "context" consists of two things: * (a) TLB cache version (or round, cycle whatever expression you like) * (b) ASID (Address Space IDentifier) */ #ifdef CONFIG_CPU_HAS_PTEAEX #define MMU_CONTEXT_ASID_MASK 0x0000ffff #else #define MMU_CONTEXT_ASID_MASK 0x000000ff #endif #define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK) #define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1) /* Impossible ASID value, to differentiate from NO_CONTEXT. */ #define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION #define NO_CONTEXT 0UL #define asid_cache(cpu) (cpu_data[cpu].asid_cache) #ifdef CONFIG_MMU #define cpu_context(cpu, mm) ((mm)->context.id[cpu]) #define cpu_asid(cpu, mm) \ (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK) /* * Virtual Page Number mask */ #define MMU_VPN_MASK 0xfffff000 #include <asm/mmu_context_32.h> /* * Get MMU context if needed. */ static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu) { unsigned long asid = asid_cache(cpu); /* Check if we have old version of context. */ if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0) /* It's up to date, do nothing */ return; /* It's old, we need to get new context with new version. */ if (!(++asid & MMU_CONTEXT_ASID_MASK)) { /* * We exhaust ASID of this version. * Flush all TLB and start new cycle. */ local_flush_tlb_all(); /* * Fix version; Note that we avoid version #0 * to distinguish NO_CONTEXT. */ if (!asid) asid = MMU_CONTEXT_FIRST_VERSION; } cpu_context(cpu, mm) = asid_cache(cpu) = asid; } /* * Initialize the context related info for a new mm_struct * instance. */ #define init_new_context init_new_context static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int i; for_each_online_cpu(i) cpu_context(i, mm) = NO_CONTEXT; return 0; } /* * After we have set current->mm to a new value, this activates * the context for the new mm so we see the new mappings. */ static inline void activate_context(struct mm_struct *mm, unsigned int cpu) { get_mmu_context(mm, cpu); set_asid(cpu_asid(cpu, mm)); } static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) { unsigned int cpu = smp_processor_id(); if (likely(prev != next)) { cpumask_set_cpu(cpu, mm_cpumask(next)); set_TTB(next->pgd); activate_context(next, cpu); } else if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next))) activate_context(next, cpu); } #include <asm-generic/mmu_context.h> #else #define set_asid(asid) do { } while (0) #define get_asid() (0) #define cpu_asid(cpu, mm) ({ (void)cpu; NO_CONTEXT; }) #define switch_and_save_asid(asid) (0) #define set_TTB(pgd) do { } while (0) #define get_TTB() (0) #include <asm-generic/nommu_context.h> #endif /* CONFIG_MMU */ #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4) /* * If this processor has an MMU, we need methods to turn it off/on .. * paging_init() will also have to be updated for the processor in * question. */ static inline void enable_mmu(void) { unsigned int cpu = smp_processor_id(); /* Enable MMU */ __raw_writel(MMU_CONTROL_INIT, MMUCR); ctrl_barrier(); if (asid_cache(cpu) == NO_CONTEXT) asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION; set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK); } static inline void disable_mmu(void) { unsigned long cr; cr = __raw_readl(MMUCR); cr &= ~MMU_CONTROL_INIT; __raw_writel(cr, MMUCR); ctrl_barrier(); } #else /* * MMU control handlers for processors lacking memory * management hardware. */ #define enable_mmu() do { } while (0) #define disable_mmu() do { } while (0) #endif #endif /* __ASM_SH_MMU_CONTEXT_H */ PK ! &��� � include/asm/cmpxchg-xchg.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CMPXCHG_XCHG_H #define __ASM_SH_CMPXCHG_XCHG_H /* * Copyright (C) 2016 Red Hat, Inc. * Author: Michael S. Tsirkin <mst@redhat.com> */ #include <linux/bits.h> #include <linux/compiler.h> #include <asm/byteorder.h> /* * Portable implementations of 1 and 2 byte xchg using a 4 byte cmpxchg. * Note: this header isn't self-contained: before including it, __cmpxchg_u32 * must be defined first. */ static inline u32 __xchg_cmpxchg(volatile void *ptr, u32 x, int size) { int off = (unsigned long)ptr % sizeof(u32); volatile u32 *p = ptr - off; #ifdef __BIG_ENDIAN int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE; #else int bitoff = off * BITS_PER_BYTE; #endif u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff; u32 oldv, newv; u32 ret; do { oldv = READ_ONCE(*p); ret = (oldv & bitmask) >> bitoff; newv = (oldv & ~bitmask) | (x << bitoff); } while (__cmpxchg_u32(p, oldv, newv) != oldv); return ret; } static inline unsigned long xchg_u16(volatile u16 *m, unsigned long val) { return __xchg_cmpxchg(m, val, sizeof *m); } static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) { return __xchg_cmpxchg(m, val, sizeof *m); } #endif /* __ASM_SH_CMPXCHG_XCHG_H */ PK ! ���� � include/asm/mmiowb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_MMIOWB_H #define __ASM_SH_MMIOWB_H #include <asm/barrier.h> /* synco on SH-4A, otherwise a nop */ #define mmiowb() wmb() #include <asm-generic/mmiowb.h> #endif /* __ASM_SH_MMIOWB_H */ PK ! �(�� � include/asm/ptrace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 1999, 2000 Niibe Yutaka */ #ifndef __ASM_SH_PTRACE_H #define __ASM_SH_PTRACE_H #include <linux/stringify.h> #include <linux/stddef.h> #include <linux/thread_info.h> #include <asm/addrspace.h> #include <asm/page.h> #include <uapi/asm/ptrace.h> #define user_mode(regs) (((regs)->sr & 0x40000000)==0) #define kernel_stack_pointer(_regs) ((unsigned long)(_regs)->regs[15]) static inline unsigned long instruction_pointer(struct pt_regs *regs) { return regs->pc; } static inline void instruction_pointer_set(struct pt_regs *regs, unsigned long val) { regs->pc = val; } static inline unsigned long frame_pointer(struct pt_regs *regs) { return regs->regs[14]; } static inline unsigned long user_stack_pointer(struct pt_regs *regs) { return regs->regs[15]; } static inline void user_stack_pointer_set(struct pt_regs *regs, unsigned long val) { regs->regs[15] = val; } #define arch_has_single_step() (1) /* * kprobe-based event tracer support */ struct pt_regs_offset { const char *name; int offset; }; #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} #define REGS_OFFSET_NAME(num) \ {.name = __stringify(r##num), .offset = offsetof(struct pt_regs, regs[num])} #define TREGS_OFFSET_NAME(num) \ {.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])} #define REG_OFFSET_END {.name = NULL, .offset = 0} /* Query offset/name of register from its name/offset */ extern int regs_query_register_offset(const char *name); extern const char *regs_query_register_name(unsigned int offset); extern const struct pt_regs_offset regoffset_table[]; /** * regs_get_register() - get register value from its offset * @regs: pt_regs from which register value is gotten. * @offset: offset number of the register. * * regs_get_register returns the value of a register. The @offset is the * offset of the register in struct pt_regs address which specified by @regs. * If @offset is bigger than MAX_REG_OFFSET, this returns 0. */ static inline unsigned long regs_get_register(struct pt_regs *regs, unsigned int offset) { if (unlikely(offset > MAX_REG_OFFSET)) return 0; return *(unsigned long *)((unsigned long)regs + offset); } /** * regs_within_kernel_stack() - check the address in the stack * @regs: pt_regs which contains kernel stack pointer. * @addr: address which is checked. * * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). * If @addr is within the kernel stack, it returns true. If not, returns false. */ static inline int regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) { return ((addr & ~(THREAD_SIZE - 1)) == (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); } /** * regs_get_kernel_stack_nth() - get Nth entry of the stack * @regs: pt_regs which contains kernel stack pointer. * @n: stack entry number. * * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which * is specified by @regs. If the @n th entry is NOT in the kernel stack, * this returns 0. */ static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) { unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); addr += n; if (regs_within_kernel_stack(regs, (unsigned long)addr)) return *addr; else return 0; } struct perf_event; struct perf_sample_data; extern void ptrace_triggered(struct perf_event *bp, struct perf_sample_data *data, struct pt_regs *regs); #define task_pt_regs(task) \ ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE) - 1) static inline unsigned long profile_pc(struct pt_regs *regs) { unsigned long pc = regs->pc; if (virt_addr_uncached(pc)) return CAC_ADDR(pc); return pc; } #endif /* __ASM_SH_PTRACE_H */ PK ! +�yw� � include/asm/push-switch.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PUSH_SWITCH_H #define __ASM_SH_PUSH_SWITCH_H #include <linux/timer.h> #include <linux/interrupt.h> #include <linux/workqueue.h> #include <linux/platform_device.h> struct push_switch { /* switch state */ unsigned int state:1; /* debounce timer */ struct timer_list debounce; /* workqueue */ struct work_struct work; /* platform device, for workqueue handler */ struct platform_device *pdev; }; struct push_switch_platform_info { /* IRQ handler */ irqreturn_t (*irq_handler)(int irq, void *data); /* Special IRQ flags */ unsigned int irq_flags; /* Bit location of switch */ unsigned int bit; /* Symbolic switch name */ const char *name; }; #endif /* __ASM_SH_PUSH_SWITCH_H */ PK ! tQ�� � include/asm/io_generic.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Trivial I/O routine definitions, intentionally meant to be included * multiple times. Ugly I/O routine concatenation helpers taken from * alpha. Must be included _before_ io.h to avoid preprocessor-induced * routine mismatch. */ #define IO_CONCAT(a,b) _IO_CONCAT(a,b) #define _IO_CONCAT(a,b) a ## _ ## b #ifndef __IO_PREFIX #error "Don't include this header without a valid system prefix" #endif void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size); void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr); void IO_CONCAT(__IO_PREFIX,mem_init)(void); #undef __IO_PREFIX PK ! ��-� include/asm/bitops-op32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BITOPS_OP32_H #define __ASM_SH_BITOPS_OP32_H /* * The bit modifying instructions on SH-2A are only capable of working * with a 3-bit immediate, which signifies the shift position for the bit * being worked on. */ #if defined(__BIG_ENDIAN) #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) #define BYTE_NUMBER(nr) ((nr ^ BITOP_LE_SWIZZLE) / BITS_PER_BYTE) #define BYTE_OFFSET(nr) ((nr ^ BITOP_LE_SWIZZLE) % BITS_PER_BYTE) #else #define BYTE_NUMBER(nr) ((nr) / BITS_PER_BYTE) #define BYTE_OFFSET(nr) ((nr) % BITS_PER_BYTE) #endif static inline void __set_bit(int nr, volatile unsigned long *addr) { if (__builtin_constant_p(nr)) { __asm__ __volatile__ ( "bset.b %1, @(%O2,%0) ! __set_bit\n\t" : "+r" (addr) : "i" (BYTE_OFFSET(nr)), "i" (BYTE_NUMBER(nr)) : "t", "memory" ); } else { unsigned long mask = BIT_MASK(nr); unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); *p |= mask; } } static inline void __clear_bit(int nr, volatile unsigned long *addr) { if (__builtin_constant_p(nr)) { __asm__ __volatile__ ( "bclr.b %1, @(%O2,%0) ! __clear_bit\n\t" : "+r" (addr) : "i" (BYTE_OFFSET(nr)), "i" (BYTE_NUMBER(nr)) : "t", "memory" ); } else { unsigned long mask = BIT_MASK(nr); unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); *p &= ~mask; } } /** * __change_bit - Toggle a bit in memory * @nr: the bit to change * @addr: the address to start counting from * * Unlike change_bit(), this function is non-atomic and may be reordered. * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ static inline void __change_bit(int nr, volatile unsigned long *addr) { if (__builtin_constant_p(nr)) { __asm__ __volatile__ ( "bxor.b %1, @(%O2,%0) ! __change_bit\n\t" : "+r" (addr) : "i" (BYTE_OFFSET(nr)), "i" (BYTE_NUMBER(nr)) : "t", "memory" ); } else { unsigned long mask = BIT_MASK(nr); unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); *p ^= mask; } } /** * __test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) { unsigned long mask = BIT_MASK(nr); unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); unsigned long old = *p; *p = old | mask; return (old & mask) != 0; } /** * __test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to clear * @addr: Address to count from * * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) { unsigned long mask = BIT_MASK(nr); unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); unsigned long old = *p; *p = old & ~mask; return (old & mask) != 0; } /* WARNING: non atomic and it can be reordered! */ static inline int __test_and_change_bit(int nr, volatile unsigned long *addr) { unsigned long mask = BIT_MASK(nr); unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); unsigned long old = *p; *p = old ^ mask; return (old & mask) != 0; } /** * test_bit - Determine whether a bit is set * @nr: bit number to test * @addr: Address to start counting from */ static inline int test_bit(int nr, const volatile unsigned long *addr) { return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); } #endif /* __ASM_SH_BITOPS_OP32_H */ PK ! ���� � include/asm/spinlock-cas.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/spinlock-cas.h * * Copyright (C) 2015 SEI */ #ifndef __ASM_SH_SPINLOCK_CAS_H #define __ASM_SH_SPINLOCK_CAS_H #include <asm/barrier.h> #include <asm/processor.h> static inline unsigned __sl_cas(volatile unsigned *p, unsigned old, unsigned new) { __asm__ __volatile__("cas.l %1,%0,@r0" : "+r"(new) : "r"(old), "z"(p) : "t", "memory" ); return new; } /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ #define arch_spin_is_locked(x) ((x)->lock <= 0) static inline void arch_spin_lock(arch_spinlock_t *lock) { while (!__sl_cas(&lock->lock, 1, 0)); } static inline void arch_spin_unlock(arch_spinlock_t *lock) { __sl_cas(&lock->lock, 0, 1); } static inline int arch_spin_trylock(arch_spinlock_t *lock) { return __sl_cas(&lock->lock, 1, 0); } /* * Read-write spinlocks, allowing multiple readers but only one writer. * * NOTE! it is quite common to have readers in interrupts but no interrupt * writers. For those circumstances we can "mix" irq-safe locks - any writer * needs to get a irq-safe write-lock, but readers can get non-irqsafe * read-locks. */ static inline void arch_read_lock(arch_rwlock_t *rw) { unsigned old; do old = rw->lock; while (!old || __sl_cas(&rw->lock, old, old-1) != old); } static inline void arch_read_unlock(arch_rwlock_t *rw) { unsigned old; do old = rw->lock; while (__sl_cas(&rw->lock, old, old+1) != old); } static inline void arch_write_lock(arch_rwlock_t *rw) { while (__sl_cas(&rw->lock, RW_LOCK_BIAS, 0) != RW_LOCK_BIAS); } static inline void arch_write_unlock(arch_rwlock_t *rw) { __sl_cas(&rw->lock, 0, RW_LOCK_BIAS); } static inline int arch_read_trylock(arch_rwlock_t *rw) { unsigned old; do old = rw->lock; while (old && __sl_cas(&rw->lock, old, old-1) != old); return !!old; } static inline int arch_write_trylock(arch_rwlock_t *rw) { return __sl_cas(&rw->lock, RW_LOCK_BIAS, 0) == RW_LOCK_BIAS; } #endif /* __ASM_SH_SPINLOCK_CAS_H */ PK ! _KoD D include/asm/checksum.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <asm/checksum_32.h> PK ! ̤� include/asm/bl_bit_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BL_BIT_32_H #define __ASM_SH_BL_BIT_32_H static inline void set_bl_bit(void) { unsigned long __dummy0, __dummy1; __asm__ __volatile__ ( "stc sr, %0\n\t" "or %2, %0\n\t" "and %3, %0\n\t" "ldc %0, sr\n\t" : "=&r" (__dummy0), "=r" (__dummy1) : "r" (0x10000000), "r" (0xffffff0f) : "memory" ); } static inline void clear_bl_bit(void) { unsigned long __dummy0, __dummy1; __asm__ __volatile__ ( "stc sr, %0\n\t" "and %2, %0\n\t" "ldc %0, sr\n\t" : "=&r" (__dummy0), "=r" (__dummy1) : "1" (~0x10000000) : "memory" ); } #endif /* __ASM_SH_BL_BIT_32_H */ PK ! Z�/�: : include/asm/traps_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_TRAPS_32_H #define __ASM_SH_TRAPS_32_H #include <linux/types.h> #include <asm/mmu.h> #ifdef CONFIG_CPU_HAS_SR_RB #define lookup_exception_vector() \ ({ \ unsigned long _vec; \ \ __asm__ __volatile__ ( \ "stc r2_bank, %0\n\t" \ : "=r" (_vec) \ ); \ \ _vec; \ }) #else #define lookup_exception_vector() \ ({ \ unsigned long _vec; \ __asm__ __volatile__ ( \ "mov r4, %0\n\t" \ : "=r" (_vec) \ ); \ \ _vec; \ }) #endif static inline void trigger_address_error(void) { __asm__ __volatile__ ( "ldc %0, sr\n\t" "mov.l @%1, %0" : : "r" (0x10000000), "r" (0x80000001) ); } asmlinkage void do_address_error(struct pt_regs *regs, unsigned long writeaccess, unsigned long address); asmlinkage void do_divide_error(unsigned long r4); asmlinkage void do_reserved_inst(void); asmlinkage void do_illegal_slot_inst(void); asmlinkage void do_exception_error(void); #define BUILD_TRAP_HANDLER(name) \ asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \ unsigned long r6, unsigned long r7, \ struct pt_regs __regs) #define TRAP_HANDLER_DECL \ struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \ unsigned int vec = regs->tra; \ (void)vec; #endif /* __ASM_SH_TRAPS_32_H */ PK ! ��m@p p include/asm/mmu_context_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_MMU_CONTEXT_32_H #define __ASM_SH_MMU_CONTEXT_32_H #ifdef CONFIG_CPU_HAS_PTEAEX static inline void set_asid(unsigned long asid) { __raw_writel(asid, MMU_PTEAEX); } static inline unsigned long get_asid(void) { return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK; } #else static inline void set_asid(unsigned long asid) { unsigned long __dummy; __asm__ __volatile__ ("mov.l %2, %0\n\t" "and %3, %0\n\t" "or %1, %0\n\t" "mov.l %0, %2" : "=&r" (__dummy) : "r" (asid), "m" (__m(MMU_PTEH)), "r" (0xffffff00)); } static inline unsigned long get_asid(void) { unsigned long asid; __asm__ __volatile__ ("mov.l %1, %0" : "=r" (asid) : "m" (__m(MMU_PTEH))); asid &= MMU_CONTEXT_ASID_MASK; return asid; } #endif /* CONFIG_CPU_HAS_PTEAEX */ /* MMU_TTB is used for optimizing the fault handling. */ static inline void set_TTB(pgd_t *pgd) { __raw_writel((unsigned long)pgd, MMU_TTB); } static inline pgd_t *get_TTB(void) { return (pgd_t *)__raw_readl(MMU_TTB); } #endif /* __ASM_SH_MMU_CONTEXT_32_H */ PK ! WX�He e include/asm/futex.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_FUTEX_H #define __ASM_SH_FUTEX_H #include <linux/futex.h> #include <linux/uaccess.h> #include <asm/errno.h> #if !defined(CONFIG_SMP) #include <asm/futex-irq.h> #elif defined(CONFIG_CPU_J2) #include <asm/futex-cas.h> #elif defined(CONFIG_CPU_SH4A) #include <asm/futex-llsc.h> #else #error SMP not supported on this configuration. #endif static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; return atomic_futex_op_cmpxchg_inatomic(uval, uaddr, oldval, newval); } static inline int arch_futex_atomic_op_inuser(int op, u32 oparg, int *oval, u32 __user *uaddr) { u32 oldval, newval, prev; int ret; do { ret = get_user(oldval, uaddr); if (ret) break; switch (op) { case FUTEX_OP_SET: newval = oparg; break; case FUTEX_OP_ADD: newval = oldval + oparg; break; case FUTEX_OP_OR: newval = oldval | oparg; break; case FUTEX_OP_ANDN: newval = oldval & ~oparg; break; case FUTEX_OP_XOR: newval = oldval ^ oparg; break; default: ret = -ENOSYS; break; } if (ret) break; ret = futex_atomic_cmpxchg_inatomic(&prev, uaddr, oldval, newval); } while (!ret && prev != oldval); if (!ret) *oval = oldval; return ret; } #endif /* __ASM_SH_FUTEX_H */ PK ! + ȑ: : include/asm/platform_early.hnu �[��� /* SPDX--License-Identifier: GPL-2.0 */ #ifndef __PLATFORM_EARLY__ #define __PLATFORM_EARLY__ #include <linux/types.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> struct sh_early_platform_driver { const char *class_str; struct platform_driver *pdrv; struct list_head list; int requested_id; char *buffer; int bufsize; }; #define EARLY_PLATFORM_ID_UNSET -2 #define EARLY_PLATFORM_ID_ERROR -3 extern int sh_early_platform_driver_register(struct sh_early_platform_driver *epdrv, char *buf); extern void sh_early_platform_add_devices(struct platform_device **devs, int num); static inline int is_sh_early_platform_device(struct platform_device *pdev) { return !pdev->dev.driver; } extern void sh_early_platform_driver_register_all(char *class_str); extern int sh_early_platform_driver_probe(char *class_str, int nr_probe, int user_only); #define sh_early_platform_init(class_string, platdrv) \ sh_early_platform_init_buffer(class_string, platdrv, NULL, 0) #ifndef MODULE #define sh_early_platform_init_buffer(class_string, platdrv, buf, bufsiz) \ static __initdata struct sh_early_platform_driver early_driver = { \ .class_str = class_string, \ .buffer = buf, \ .bufsize = bufsiz, \ .pdrv = platdrv, \ .requested_id = EARLY_PLATFORM_ID_UNSET, \ }; \ static int __init sh_early_platform_driver_setup_func(char *buffer) \ { \ return sh_early_platform_driver_register(&early_driver, buffer); \ } \ early_param(class_string, sh_early_platform_driver_setup_func) #else /* MODULE */ #define sh_early_platform_init_buffer(class_string, platdrv, buf, bufsiz) \ static inline char *sh_early_platform_driver_setup_func(void) \ { \ return bufsiz ? buf : NULL; \ } #endif /* MODULE */ #endif /* __PLATFORM_EARLY__ */ PK ! e�)PB B include/asm/bl_bit.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <asm/bl_bit_32.h> PK ! �6�� � include/asm/vga.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_VGA_H #define __ASM_SH_VGA_H /* Stupid drivers. */ #endif /* __ASM_SH_VGA_H */ PK ! ��5 5 include/asm/spinlock-llsc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/spinlock-llsc.h * * Copyright (C) 2002, 2003 Paul Mundt * Copyright (C) 2006, 2007 Akio Idehara */ #ifndef __ASM_SH_SPINLOCK_LLSC_H #define __ASM_SH_SPINLOCK_LLSC_H #include <asm/barrier.h> #include <asm/processor.h> /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ #define arch_spin_is_locked(x) ((x)->lock <= 0) /* * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. * * We make no fairness assumptions. They have a cost. */ static inline void arch_spin_lock(arch_spinlock_t *lock) { unsigned long tmp; unsigned long oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_spin_lock \n\t" "mov %0, %1 \n\t" "mov #0, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "cmp/pl %1 \n\t" "bf 1b \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&lock->lock) : "t", "memory" ); } static inline void arch_spin_unlock(arch_spinlock_t *lock) { unsigned long tmp; /* This could be optimised with ARCH_HAS_MMIOWB */ mmiowb(); __asm__ __volatile__ ( "mov #1, %0 ! arch_spin_unlock \n\t" "mov.l %0, @%1 \n\t" : "=&z" (tmp) : "r" (&lock->lock) : "t", "memory" ); } static inline int arch_spin_trylock(arch_spinlock_t *lock) { unsigned long tmp, oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_spin_trylock \n\t" "mov %0, %1 \n\t" "mov #0, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&lock->lock) : "t", "memory" ); return oldval; } /* * Read-write spinlocks, allowing multiple readers but only one writer. * * NOTE! it is quite common to have readers in interrupts but no interrupt * writers. For those circumstances we can "mix" irq-safe locks - any writer * needs to get a irq-safe write-lock, but readers can get non-irqsafe * read-locks. */ static inline void arch_read_lock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! arch_read_lock \n\t" "cmp/pl %0 \n\t" "bf 1b \n\t" "add #-1, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (&rw->lock) : "t", "memory" ); } static inline void arch_read_unlock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! arch_read_unlock \n\t" "add #1, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (&rw->lock) : "t", "memory" ); } static inline void arch_write_lock(arch_rwlock_t *rw) { unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%1, %0 ! arch_write_lock \n\t" "cmp/hs %2, %0 \n\t" "bf 1b \n\t" "sub %2, %0 \n\t" "movco.l %0, @%1 \n\t" "bf 1b \n\t" : "=&z" (tmp) : "r" (&rw->lock), "r" (RW_LOCK_BIAS) : "t", "memory" ); } static inline void arch_write_unlock(arch_rwlock_t *rw) { __asm__ __volatile__ ( "mov.l %1, @%0 ! arch_write_unlock \n\t" : : "r" (&rw->lock), "r" (RW_LOCK_BIAS) : "t", "memory" ); } static inline int arch_read_trylock(arch_rwlock_t *rw) { unsigned long tmp, oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_read_trylock \n\t" "mov %0, %1 \n\t" "cmp/pl %0 \n\t" "bf 2f \n\t" "add #-1, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "2: \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&rw->lock) : "t", "memory" ); return (oldval > 0); } static inline int arch_write_trylock(arch_rwlock_t *rw) { unsigned long tmp, oldval; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! arch_write_trylock \n\t" "mov %0, %1 \n\t" "cmp/hs %3, %0 \n\t" "bf 2f \n\t" "sub %3, %0 \n\t" "2: \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (oldval) : "r" (&rw->lock), "r" (RW_LOCK_BIAS) : "t", "memory" ); return (oldval > (RW_LOCK_BIAS - 1)); } #endif /* __ASM_SH_SPINLOCK_LLSC_H */ PK ! �m� � include/asm/cache_insns_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CACHE_INSNS_32_H #define __ASM_SH_CACHE_INSNS_32_H #include <linux/types.h> #if defined(CONFIG_CPU_SH4A) #define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr)) #else #define __icbi(addr) mb() #endif #define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr)) #define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr)) #define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr)) static inline reg_size_t register_align(void *val) { return (unsigned long)(signed long)val; } #endif /* __ASM_SH_CACHE_INSNS_32_H */ PK ! A�²H H include/asm/atomic.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_ATOMIC_H #define __ASM_SH_ATOMIC_H #if defined(CONFIG_CPU_J2) #include <asm-generic/atomic.h> #else /* * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. * */ #include <linux/compiler.h> #include <linux/types.h> #include <asm/cmpxchg.h> #include <asm/barrier.h> #define arch_atomic_read(v) READ_ONCE((v)->counter) #define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i)) #if defined(CONFIG_GUSA_RB) #include <asm/atomic-grb.h> #elif defined(CONFIG_CPU_SH4A) #include <asm/atomic-llsc.h> #else #include <asm/atomic-irq.h> #endif #define arch_atomic_xchg(v, new) (arch_xchg(&((v)->counter), new)) #define arch_atomic_cmpxchg(v, o, n) (arch_cmpxchg(&((v)->counter), (o), (n))) #endif /* CONFIG_CPU_J2 */ #endif /* __ASM_SH_ATOMIC_H */ PK ! ����& �& include/asm/dwarf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2009 Matt Fleming <matt@console-pimps.org> */ #ifndef __ASM_SH_DWARF_H #define __ASM_SH_DWARF_H #ifdef CONFIG_DWARF_UNWINDER /* * DWARF expression operations */ #define DW_OP_addr 0x03 #define DW_OP_deref 0x06 #define DW_OP_const1u 0x08 #define DW_OP_const1s 0x09 #define DW_OP_const2u 0x0a #define DW_OP_const2s 0x0b #define DW_OP_const4u 0x0c #define DW_OP_const4s 0x0d #define DW_OP_const8u 0x0e #define DW_OP_const8s 0x0f #define DW_OP_constu 0x10 #define DW_OP_consts 0x11 #define DW_OP_dup 0x12 #define DW_OP_drop 0x13 #define DW_OP_over 0x14 #define DW_OP_pick 0x15 #define DW_OP_swap 0x16 #define DW_OP_rot 0x17 #define DW_OP_xderef 0x18 #define DW_OP_abs 0x19 #define DW_OP_and 0x1a #define DW_OP_div 0x1b #define DW_OP_minus 0x1c #define DW_OP_mod 0x1d #define DW_OP_mul 0x1e #define DW_OP_neg 0x1f #define DW_OP_not 0x20 #define DW_OP_or 0x21 #define DW_OP_plus 0x22 #define DW_OP_plus_uconst 0x23 #define DW_OP_shl 0x24 #define DW_OP_shr 0x25 #define DW_OP_shra 0x26 #define DW_OP_xor 0x27 #define DW_OP_skip 0x2f #define DW_OP_bra 0x28 #define DW_OP_eq 0x29 #define DW_OP_ge 0x2a #define DW_OP_gt 0x2b #define DW_OP_le 0x2c #define DW_OP_lt 0x2d #define DW_OP_ne 0x2e #define DW_OP_lit0 0x30 #define DW_OP_lit1 0x31 #define DW_OP_lit2 0x32 #define DW_OP_lit3 0x33 #define DW_OP_lit4 0x34 #define DW_OP_lit5 0x35 #define DW_OP_lit6 0x36 #define DW_OP_lit7 0x37 #define DW_OP_lit8 0x38 #define DW_OP_lit9 0x39 #define DW_OP_lit10 0x3a #define DW_OP_lit11 0x3b #define DW_OP_lit12 0x3c #define DW_OP_lit13 0x3d #define DW_OP_lit14 0x3e #define DW_OP_lit15 0x3f #define DW_OP_lit16 0x40 #define DW_OP_lit17 0x41 #define DW_OP_lit18 0x42 #define DW_OP_lit19 0x43 #define DW_OP_lit20 0x44 #define DW_OP_lit21 0x45 #define DW_OP_lit22 0x46 #define DW_OP_lit23 0x47 #define DW_OP_lit24 0x48 #define DW_OP_lit25 0x49 #define DW_OP_lit26 0x4a #define DW_OP_lit27 0x4b #define DW_OP_lit28 0x4c #define DW_OP_lit29 0x4d #define DW_OP_lit30 0x4e #define DW_OP_lit31 0x4f #define DW_OP_reg0 0x50 #define DW_OP_reg1 0x51 #define DW_OP_reg2 0x52 #define DW_OP_reg3 0x53 #define DW_OP_reg4 0x54 #define DW_OP_reg5 0x55 #define DW_OP_reg6 0x56 #define DW_OP_reg7 0x57 #define DW_OP_reg8 0x58 #define DW_OP_reg9 0x59 #define DW_OP_reg10 0x5a #define DW_OP_reg11 0x5b #define DW_OP_reg12 0x5c #define DW_OP_reg13 0x5d #define DW_OP_reg14 0x5e #define DW_OP_reg15 0x5f #define DW_OP_reg16 0x60 #define DW_OP_reg17 0x61 #define DW_OP_reg18 0x62 #define DW_OP_reg19 0x63 #define DW_OP_reg20 0x64 #define DW_OP_reg21 0x65 #define DW_OP_reg22 0x66 #define DW_OP_reg23 0x67 #define DW_OP_reg24 0x68 #define DW_OP_reg25 0x69 #define DW_OP_reg26 0x6a #define DW_OP_reg27 0x6b #define DW_OP_reg28 0x6c #define DW_OP_reg29 0x6d #define DW_OP_reg30 0x6e #define DW_OP_reg31 0x6f #define DW_OP_breg0 0x70 #define DW_OP_breg1 0x71 #define DW_OP_breg2 0x72 #define DW_OP_breg3 0x73 #define DW_OP_breg4 0x74 #define DW_OP_breg5 0x75 #define DW_OP_breg6 0x76 #define DW_OP_breg7 0x77 #define DW_OP_breg8 0x78 #define DW_OP_breg9 0x79 #define DW_OP_breg10 0x7a #define DW_OP_breg11 0x7b #define DW_OP_breg12 0x7c #define DW_OP_breg13 0x7d #define DW_OP_breg14 0x7e #define DW_OP_breg15 0x7f #define DW_OP_breg16 0x80 #define DW_OP_breg17 0x81 #define DW_OP_breg18 0x82 #define DW_OP_breg19 0x83 #define DW_OP_breg20 0x84 #define DW_OP_breg21 0x85 #define DW_OP_breg22 0x86 #define DW_OP_breg23 0x87 #define DW_OP_breg24 0x88 #define DW_OP_breg25 0x89 #define DW_OP_breg26 0x8a #define DW_OP_breg27 0x8b #define DW_OP_breg28 0x8c #define DW_OP_breg29 0x8d #define DW_OP_breg30 0x8e #define DW_OP_breg31 0x8f #define DW_OP_regx 0x90 #define DW_OP_fbreg 0x91 #define DW_OP_bregx 0x92 #define DW_OP_piece 0x93 #define DW_OP_deref_size 0x94 #define DW_OP_xderef_size 0x95 #define DW_OP_nop 0x96 #define DW_OP_push_object_address 0x97 #define DW_OP_call2 0x98 #define DW_OP_call4 0x99 #define DW_OP_call_ref 0x9a #define DW_OP_form_tls_address 0x9b #define DW_OP_call_frame_cfa 0x9c #define DW_OP_bit_piece 0x9d #define DW_OP_lo_user 0xe0 #define DW_OP_hi_user 0xff /* * Addresses used in FDE entries in the .eh_frame section may be encoded * using one of the following encodings. */ #define DW_EH_PE_absptr 0x00 #define DW_EH_PE_omit 0xff #define DW_EH_PE_uleb128 0x01 #define DW_EH_PE_udata2 0x02 #define DW_EH_PE_udata4 0x03 #define DW_EH_PE_udata8 0x04 #define DW_EH_PE_sleb128 0x09 #define DW_EH_PE_sdata2 0x0a #define DW_EH_PE_sdata4 0x0b #define DW_EH_PE_sdata8 0x0c #define DW_EH_PE_signed 0x09 #define DW_EH_PE_pcrel 0x10 /* * The architecture-specific register number that contains the return * address in the .debug_frame table. */ #define DWARF_ARCH_RA_REG 17 #ifndef __ASSEMBLY__ #include <linux/compiler.h> #include <linux/bug.h> #include <linux/list.h> #include <linux/module.h> /* * Read either the frame pointer (r14) or the stack pointer (r15). * NOTE: this MUST be inlined. */ static __always_inline unsigned long dwarf_read_arch_reg(unsigned int reg) { unsigned long value = 0; switch (reg) { case 14: __asm__ __volatile__("mov r14, %0\n" : "=r" (value)); break; case 15: __asm__ __volatile__("mov r15, %0\n" : "=r" (value)); break; default: BUG(); } return value; } /** * dwarf_cie - Common Information Entry */ struct dwarf_cie { unsigned long length; unsigned long cie_id; unsigned char version; const char *augmentation; unsigned int code_alignment_factor; int data_alignment_factor; /* Which column in the rule table represents return addr of func. */ unsigned int return_address_reg; unsigned char *initial_instructions; unsigned char *instructions_end; unsigned char encoding; unsigned long cie_pointer; unsigned long flags; #define DWARF_CIE_Z_AUGMENTATION (1 << 0) /* linked-list entry if this CIE is from a module */ struct list_head link; struct rb_node node; }; /** * dwarf_fde - Frame Description Entry */ struct dwarf_fde { unsigned long length; unsigned long cie_pointer; struct dwarf_cie *cie; unsigned long initial_location; unsigned long address_range; unsigned char *instructions; unsigned char *end; /* linked-list entry if this FDE is from a module */ struct list_head link; struct rb_node node; }; /** * dwarf_frame - DWARF information for a frame in the call stack */ struct dwarf_frame { struct dwarf_frame *prev, *next; unsigned long pc; struct list_head reg_list; unsigned long cfa; /* Valid when DW_FRAME_CFA_REG_OFFSET is set in flags */ unsigned int cfa_register; unsigned int cfa_offset; /* Valid when DW_FRAME_CFA_REG_EXP is set in flags */ unsigned char *cfa_expr; unsigned int cfa_expr_len; unsigned long flags; #define DWARF_FRAME_CFA_REG_OFFSET (1 << 0) #define DWARF_FRAME_CFA_REG_EXP (1 << 1) unsigned long return_addr; }; /** * dwarf_reg - DWARF register * @flags: Describes how to calculate the value of this register */ struct dwarf_reg { struct list_head link; unsigned int number; unsigned long addr; unsigned long flags; #define DWARF_REG_OFFSET (1 << 0) #define DWARF_VAL_OFFSET (1 << 1) #define DWARF_UNDEFINED (1 << 2) }; /* * Call Frame instruction opcodes. */ #define DW_CFA_advance_loc 0x40 #define DW_CFA_offset 0x80 #define DW_CFA_restore 0xc0 #define DW_CFA_nop 0x00 #define DW_CFA_set_loc 0x01 #define DW_CFA_advance_loc1 0x02 #define DW_CFA_advance_loc2 0x03 #define DW_CFA_advance_loc4 0x04 #define DW_CFA_offset_extended 0x05 #define DW_CFA_restore_extended 0x06 #define DW_CFA_undefined 0x07 #define DW_CFA_same_value 0x08 #define DW_CFA_register 0x09 #define DW_CFA_remember_state 0x0a #define DW_CFA_restore_state 0x0b #define DW_CFA_def_cfa 0x0c #define DW_CFA_def_cfa_register 0x0d #define DW_CFA_def_cfa_offset 0x0e #define DW_CFA_def_cfa_expression 0x0f #define DW_CFA_expression 0x10 #define DW_CFA_offset_extended_sf 0x11 #define DW_CFA_def_cfa_sf 0x12 #define DW_CFA_def_cfa_offset_sf 0x13 #define DW_CFA_val_offset 0x14 #define DW_CFA_val_offset_sf 0x15 #define DW_CFA_val_expression 0x16 #define DW_CFA_lo_user 0x1c #define DW_CFA_hi_user 0x3f /* GNU extension opcodes */ #define DW_CFA_GNU_args_size 0x2e #define DW_CFA_GNU_negative_offset_extended 0x2f /* * Some call frame instructions encode their operands in the opcode. We * need some helper functions to extract both the opcode and operands * from an instruction. */ static inline unsigned int DW_CFA_opcode(unsigned long insn) { return (insn & 0xc0); } static inline unsigned int DW_CFA_operand(unsigned long insn) { return (insn & 0x3f); } #define DW_EH_FRAME_CIE 0 /* .eh_frame CIE IDs are 0 */ #define DW_CIE_ID 0xffffffff #define DW64_CIE_ID 0xffffffffffffffffULL /* * DWARF FDE/CIE length field values. */ #define DW_EXT_LO 0xfffffff0 #define DW_EXT_HI 0xffffffff #define DW_EXT_DWARF64 DW_EXT_HI extern struct dwarf_frame *dwarf_unwind_stack(unsigned long, struct dwarf_frame *); extern void dwarf_free_frame(struct dwarf_frame *); extern int module_dwarf_finalize(const Elf_Ehdr *, const Elf_Shdr *, struct module *); extern void module_dwarf_cleanup(struct module *); #endif /* !__ASSEMBLY__ */ #define CFI_STARTPROC .cfi_startproc #define CFI_ENDPROC .cfi_endproc #define CFI_DEF_CFA .cfi_def_cfa #define CFI_REGISTER .cfi_register #define CFI_REL_OFFSET .cfi_rel_offset #define CFI_UNDEFINED .cfi_undefined #else /* * Use the asm comment character to ignore the rest of the line. */ #define CFI_IGNORE ! #define CFI_STARTPROC CFI_IGNORE #define CFI_ENDPROC CFI_IGNORE #define CFI_DEF_CFA CFI_IGNORE #define CFI_REGISTER CFI_IGNORE #define CFI_REL_OFFSET CFI_IGNORE #define CFI_UNDEFINED CFI_IGNORE #ifndef __ASSEMBLY__ static inline void dwarf_unwinder_init(void) { } #define module_dwarf_finalize(hdr, sechdrs, me) (0) #define module_dwarf_cleanup(mod) do { } while (0) #endif #endif /* CONFIG_DWARF_UNWINDER */ #endif /* __ASM_SH_DWARF_H */ PK ! ���F� � include/asm/atomic-llsc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_ATOMIC_LLSC_H #define __ASM_SH_ATOMIC_LLSC_H /* * SH-4A note: * * We basically get atomic_xxx_return() for free compared with * atomic_xxx(). movli.l/movco.l require r0 due to the instruction * encoding, so the retval is automatically set without having to * do any special work. */ /* * To get proper branch prediction for the main line, we must branch * forward to code at the end of this object's .text section, then * branch back to restart the operation. */ #define ATOMIC_OP(op) \ static inline void arch_atomic_##op(int i, atomic_t *v) \ { \ unsigned long tmp; \ \ __asm__ __volatile__ ( \ "1: movli.l @%2, %0 ! atomic_" #op "\n" \ " " #op " %1, %0 \n" \ " movco.l %0, @%2 \n" \ " bf 1b \n" \ : "=&z" (tmp) \ : "r" (i), "r" (&v->counter) \ : "t"); \ } #define ATOMIC_OP_RETURN(op) \ static inline int arch_atomic_##op##_return(int i, atomic_t *v) \ { \ unsigned long temp; \ \ __asm__ __volatile__ ( \ "1: movli.l @%2, %0 ! atomic_" #op "_return \n" \ " " #op " %1, %0 \n" \ " movco.l %0, @%2 \n" \ " bf 1b \n" \ " synco \n" \ : "=&z" (temp) \ : "r" (i), "r" (&v->counter) \ : "t"); \ \ return temp; \ } #define ATOMIC_FETCH_OP(op) \ static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \ { \ unsigned long res, temp; \ \ __asm__ __volatile__ ( \ "1: movli.l @%3, %0 ! atomic_fetch_" #op " \n" \ " mov %0, %1 \n" \ " " #op " %2, %0 \n" \ " movco.l %0, @%3 \n" \ " bf 1b \n" \ " synco \n" \ : "=&z" (temp), "=&r" (res) \ : "r" (i), "r" (&v->counter) \ : "t"); \ \ return res; \ } #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op) ATOMIC_OPS(add) ATOMIC_OPS(sub) #undef ATOMIC_OPS #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OPS(and) ATOMIC_OPS(or) ATOMIC_OPS(xor) #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN #undef ATOMIC_OP #endif /* __ASM_SH_ATOMIC_LLSC_H */ PK ! �[��J J include/asm/asm-offsets.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <generated/asm-offsets.h> PK ! .6�]� � include/asm/checksum_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CHECKSUM_H #define __ASM_SH_CHECKSUM_H /* * Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka */ #include <linux/in6.h> /* * computes the checksum of a memory block at buff, length len, * and adds in "sum" (32-bit) * * returns a 32-bit number suitable for feeding into itself * or csum_tcpudp_magic * * this function must be called with even lengths, except * for the last fragment, which may be odd * * it's best to have buff aligned on a 32-bit boundary */ asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum); /* * the same as csum_partial, but copies from src while it * checksums, and handles user-space pointer exceptions correctly, when needed. * * here even more important to align src and dst on a 32-bit (or even * better 64-bit) boundary */ asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst, int len); #define _HAVE_ARCH_CSUM_AND_COPY /* * Note: when you get a NULL pointer exception here this means someone * passed in an incorrect kernel address to one of these functions. * * If you use these functions directly please don't forget the * access_ok(). */ static inline __wsum csum_partial_copy_nocheck(const void *src, void *dst, int len) { return csum_partial_copy_generic(src, dst, len); } #define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER static inline __wsum csum_and_copy_from_user(const void __user *src, void *dst, int len) { if (!access_ok(src, len)) return 0; return csum_partial_copy_generic((__force const void *)src, dst, len); } /* * Fold a partial checksum */ static inline __sum16 csum_fold(__wsum sum) { unsigned int __dummy; __asm__("swap.w %0, %1\n\t" "extu.w %0, %0\n\t" "extu.w %1, %1\n\t" "add %1, %0\n\t" "swap.w %0, %1\n\t" "add %1, %0\n\t" "not %0, %0\n\t" : "=r" (sum), "=&r" (__dummy) : "0" (sum) : "t"); return (__force __sum16)sum; } /* * This is a version of ip_compute_csum() optimized for IP headers, * which always checksum on 4 octet boundaries. * * i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted * for linux by * Arnt Gulbrandsen. */ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) { unsigned int sum, __dummy0, __dummy1; __asm__ __volatile__( "mov.l @%1+, %0\n\t" "mov.l @%1+, %3\n\t" "add #-2, %2\n\t" "clrt\n\t" "1:\t" "addc %3, %0\n\t" "movt %4\n\t" "mov.l @%1+, %3\n\t" "dt %2\n\t" "bf/s 1b\n\t" " cmp/eq #1, %4\n\t" "addc %3, %0\n\t" "addc %2, %0" /* Here %2 is 0, add carry-bit */ /* Since the input registers which are loaded with iph and ihl are modified, we must also specify them as outputs, or gcc will assume they contain their original values. */ : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1) : "1" (iph), "2" (ihl) : "t", "memory"); return csum_fold(sum); } static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len, __u8 proto, __wsum sum) { #ifdef __LITTLE_ENDIAN__ unsigned long len_proto = (proto + len) << 8; #else unsigned long len_proto = proto + len; #endif __asm__("clrt\n\t" "addc %0, %1\n\t" "addc %2, %1\n\t" "addc %3, %1\n\t" "movt %0\n\t" "add %1, %0" : "=r" (sum), "=r" (len_proto) : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum) : "t"); return sum; } /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, __u32 len, __u8 proto, __wsum sum) { return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); } /* * this routine is used for miscellaneous IP-like checksums, mainly * in icmp.c */ static inline __sum16 ip_compute_csum(const void *buff, int len) { return csum_fold(csum_partial(buff, len, 0)); } #define _HAVE_ARCH_IPV6_CSUM static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, __u32 len, __u8 proto, __wsum sum) { unsigned int __dummy; __asm__("clrt\n\t" "mov.l @(0,%2), %1\n\t" "addc %1, %0\n\t" "mov.l @(4,%2), %1\n\t" "addc %1, %0\n\t" "mov.l @(8,%2), %1\n\t" "addc %1, %0\n\t" "mov.l @(12,%2), %1\n\t" "addc %1, %0\n\t" "mov.l @(0,%3), %1\n\t" "addc %1, %0\n\t" "mov.l @(4,%3), %1\n\t" "addc %1, %0\n\t" "mov.l @(8,%3), %1\n\t" "addc %1, %0\n\t" "mov.l @(12,%3), %1\n\t" "addc %1, %0\n\t" "addc %4, %0\n\t" "addc %5, %0\n\t" "movt %1\n\t" "add %1, %0\n" : "=r" (sum), "=&r" (__dummy) : "r" (saddr), "r" (daddr), "r" (htonl(len)), "r" (htonl(proto)), "0" (sum) : "t"); return csum_fold(sum); } /* * Copy and checksum to user */ #define HAVE_CSUM_COPY_USER static inline __wsum csum_and_copy_to_user(const void *src, void __user *dst, int len) { if (!access_ok(dst, len)) return 0; return csum_partial_copy_generic((__force const void *)src, dst, len); } #endif /* __ASM_SH_CHECKSUM_H */ PK ! p�xS S include/asm/kgdb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_KGDB_H #define __ASM_SH_KGDB_H #include <asm/cacheflush.h> #include <asm/ptrace.h> enum regnames { GDB_R0, GDB_R1, GDB_R2, GDB_R3, GDB_R4, GDB_R5, GDB_R6, GDB_R7, GDB_R8, GDB_R9, GDB_R10, GDB_R11, GDB_R12, GDB_R13, GDB_R14, GDB_R15, GDB_PC, GDB_PR, GDB_SR, GDB_GBR, GDB_MACH, GDB_MACL, GDB_VBR, }; #define _GP_REGS 16 #define _EXTRA_REGS 7 #define GDB_SIZEOF_REG sizeof(u32) #define DBG_MAX_REG_NUM (_GP_REGS + _EXTRA_REGS) #define NUMREGBYTES (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG)) static inline void arch_kgdb_breakpoint(void) { __asm__ __volatile__ ("trapa #0x3c\n"); } #define BREAK_INSTR_SIZE 2 #define BUFMAX 2048 #ifdef CONFIG_SMP # define CACHE_FLUSH_IS_SAFE 0 #else # define CACHE_FLUSH_IS_SAFE 1 #endif #define GDB_ADJUSTS_BREAK_OFFSET #endif /* __ASM_SH_KGDB_H */ PK ! uQ� � include/asm/irqflags.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_IRQFLAGS_H #define __ASM_SH_IRQFLAGS_H #define ARCH_IRQ_DISABLED 0xf0 #define ARCH_IRQ_ENABLED 0x00 #include <asm-generic/irqflags.h> #endif /* __ASM_SH_IRQFLAGS_H */ PK ! � P�� � include/asm/syscall.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SYSCALL_H #define __ASM_SH_SYSCALL_H extern const unsigned long sys_call_table[]; #include <asm/syscall_32.h> #endif /* __ASM_SH_SYSCALL_H */ PK ! �a� include/asm/stacktrace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2009 Matt Fleming * * Based on: * The x86 implementation - arch/x86/include/asm/stacktrace.h */ #ifndef _ASM_SH_STACKTRACE_H #define _ASM_SH_STACKTRACE_H /* Generic stack tracer with callbacks */ struct stacktrace_ops { void (*address)(void *data, unsigned long address, int reliable); }; void dump_trace(struct task_struct *tsk, struct pt_regs *regs, unsigned long *stack, const struct stacktrace_ops *ops, void *data); #endif /* _ASM_SH_STACKTRACE_H */ PK ! � ��c c include/asm/fpu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_FPU_H #define __ASM_SH_FPU_H #ifndef __ASSEMBLY__ #include <asm/ptrace.h> struct task_struct; #ifdef CONFIG_SH_FPU static inline void release_fpu(struct pt_regs *regs) { regs->sr |= SR_FD; } static inline void grab_fpu(struct pt_regs *regs) { regs->sr &= ~SR_FD; } extern void save_fpu(struct task_struct *__tsk); extern void restore_fpu(struct task_struct *__tsk); extern void fpu_state_restore(struct pt_regs *regs); extern void __fpu_state_restore(void); #else #define save_fpu(tsk) do { } while (0) #define restore_fpu(tsk) do { } while (0) #define release_fpu(regs) do { } while (0) #define grab_fpu(regs) do { } while (0) #define fpu_state_restore(regs) do { } while (0) #define __fpu_state_restore(regs) do { } while (0) #endif struct user_regset; extern int do_fpu_inst(unsigned short, struct pt_regs *); extern int init_fpu(struct task_struct *); static inline void __unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs) { if (task_thread_info(tsk)->status & TS_USEDFPU) { task_thread_info(tsk)->status &= ~TS_USEDFPU; save_fpu(tsk); release_fpu(regs); } else tsk->thread.fpu_counter = 0; } static inline void unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs) { preempt_disable(); __unlazy_fpu(tsk, regs); preempt_enable(); } static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs) { preempt_disable(); if (task_thread_info(tsk)->status & TS_USEDFPU) { task_thread_info(tsk)->status &= ~TS_USEDFPU; release_fpu(regs); } preempt_enable(); } #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_FPU_H */ PK ! ��d include/asm/bug.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BUG_H #define __ASM_SH_BUG_H #include <linux/linkage.h> #define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */ #define BUGFLAG_UNWINDER (1 << 1) #ifdef CONFIG_GENERIC_BUG #define HAVE_ARCH_BUG #define HAVE_ARCH_WARN_ON /** * _EMIT_BUG_ENTRY * %1 - __FILE__ * %2 - __LINE__ * %3 - trap type * %4 - sizeof(struct bug_entry) * * The trapa opcode itself sits in %0. * The %O notation is used to avoid # generation. * * The offending file and line are encoded in the __bug_table section. */ #ifdef CONFIG_DEBUG_BUGVERBOSE #define _EMIT_BUG_ENTRY \ "\t.pushsection __bug_table,\"aw\"\n" \ "2:\t.long 1b, %O1\n" \ "\t.short %O2, %O3\n" \ "\t.org 2b+%O4\n" \ "\t.popsection\n" #else #define _EMIT_BUG_ENTRY \ "\t.pushsection __bug_table,\"aw\"\n" \ "2:\t.long 1b\n" \ "\t.short %O3\n" \ "\t.org 2b+%O4\n" \ "\t.popsection\n" #endif #define BUG() \ do { \ __asm__ __volatile__ ( \ "1:\t.short %O0\n" \ _EMIT_BUG_ENTRY \ : \ : "n" (TRAPA_BUG_OPCODE), \ "i" (__FILE__), \ "i" (__LINE__), "i" (0), \ "i" (sizeof(struct bug_entry))); \ unreachable(); \ } while (0) #define __WARN_FLAGS(flags) \ do { \ __asm__ __volatile__ ( \ "1:\t.short %O0\n" \ _EMIT_BUG_ENTRY \ : \ : "n" (TRAPA_BUG_OPCODE), \ "i" (__FILE__), \ "i" (__LINE__), \ "i" (BUGFLAG_WARNING|(flags)), \ "i" (sizeof(struct bug_entry))); \ } while (0) #define WARN_ON(x) ({ \ int __ret_warn_on = !!(x); \ if (__builtin_constant_p(__ret_warn_on)) { \ if (__ret_warn_on) \ __WARN(); \ } else { \ if (unlikely(__ret_warn_on)) \ __WARN(); \ } \ unlikely(__ret_warn_on); \ }) #define UNWINDER_BUG() \ do { \ __asm__ __volatile__ ( \ "1:\t.short %O0\n" \ _EMIT_BUG_ENTRY \ : \ : "n" (TRAPA_BUG_OPCODE), \ "i" (__FILE__), \ "i" (__LINE__), \ "i" (BUGFLAG_UNWINDER), \ "i" (sizeof(struct bug_entry))); \ } while (0) #define UNWINDER_BUG_ON(x) ({ \ int __ret_unwinder_on = !!(x); \ if (__builtin_constant_p(__ret_unwinder_on)) { \ if (__ret_unwinder_on) \ UNWINDER_BUG(); \ } else { \ if (unlikely(__ret_unwinder_on)) \ UNWINDER_BUG(); \ } \ unlikely(__ret_unwinder_on); \ }) #else #define UNWINDER_BUG BUG #define UNWINDER_BUG_ON BUG_ON #endif /* CONFIG_GENERIC_BUG */ #include <asm-generic/bug.h> struct pt_regs; /* arch/sh/kernel/traps.c */ extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn)); extern void die_if_kernel(const char *str, struct pt_regs *regs, long err); extern void die_if_no_fixup(const char *str, struct pt_regs *regs, long err); #endif /* __ASM_SH_BUG_H */ PK ! �JJ� include/asm/spi.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SPI_H__ #define __ASM_SPI_H__ struct sh_spi_info; struct sh_spi_info { int bus_num; int num_chipselect; void (*chip_select)(struct sh_spi_info *spi, int cs, int state); }; #endif /* __ASM_SPI_H__ */ PK ! b� � include/asm/hw_irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HW_IRQ_H #define __ASM_SH_HW_IRQ_H #include <linux/init.h> #include <linux/sh_intc.h> #include <linux/atomic.h> extern atomic_t irq_err_count; struct ipr_data { unsigned char irq; unsigned char ipr_idx; /* Index for the IPR registered */ unsigned char shift; /* Number of bits to shift the data */ unsigned char priority; /* The priority */ }; struct ipr_desc { unsigned long *ipr_offsets; unsigned int nr_offsets; struct ipr_data *ipr_data; unsigned int nr_irqs; struct irq_chip chip; }; void register_ipr_controller(struct ipr_desc *); void __init plat_irq_setup(void); void __init plat_irq_setup_sh3(void); void __init plat_irq_setup_pins(int mode); enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; #endif /* __ASM_SH_HW_IRQ_H */ PK ! Z���r r include/asm/ftrace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_FTRACE_H #define __ASM_SH_FTRACE_H #ifdef CONFIG_FUNCTION_TRACER #define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ #define FTRACE_SYSCALL_MAX NR_syscalls #ifndef __ASSEMBLY__ extern void mcount(void); #define MCOUNT_ADDR ((unsigned long)(mcount)) #ifdef CONFIG_DYNAMIC_FTRACE #define CALL_ADDR ((long)(ftrace_call)) #define STUB_ADDR ((long)(ftrace_stub)) #define GRAPH_ADDR ((long)(ftrace_graph_call)) #define CALLER_ADDR ((long)(ftrace_caller)) #define MCOUNT_INSN_OFFSET ((STUB_ADDR - CALL_ADDR) - 4) #define GRAPH_INSN_OFFSET ((CALLER_ADDR - GRAPH_ADDR) - 4) struct dyn_arch_ftrace { /* No extra data needed on sh */ }; #endif /* CONFIG_DYNAMIC_FTRACE */ static inline unsigned long ftrace_call_adjust(unsigned long addr) { /* 'addr' is the memory table address. */ return addr; } #endif /* __ASSEMBLY__ */ #endif /* CONFIG_FUNCTION_TRACER */ #ifndef __ASSEMBLY__ /* arch/sh/kernel/return_address.c */ extern void *return_address(unsigned int); #define ftrace_return_address(n) return_address(n) #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_FTRACE_H */ PK ! �`p�� � include/asm/pgtable-3level.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PGTABLE_3LEVEL_H #define __ASM_SH_PGTABLE_3LEVEL_H #include <asm-generic/pgtable-nopud.h> /* * Some cores need a 3-level page table layout, for example when using * 64-bit PTEs and 4K pages. */ #define PAGETABLE_LEVELS 3 #define PTE_MAGNITUDE 3 /* 64-bit PTEs on SH-X2 TLB */ /* PGD bits */ #define PGDIR_SHIFT 30 #define PTRS_PER_PGD 4 #define USER_PTRS_PER_PGD 2 /* PMD bits */ #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTE_MAGNITUDE)) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) #define PTRS_PER_PMD ((1 << PGDIR_SHIFT) / PMD_SIZE) #define pmd_ERROR(e) \ printk("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) typedef struct { unsigned long long pmd; } pmd_t; #define pmd_val(x) ((x).pmd) #define __pmd(x) ((pmd_t) { (x) } ) static inline pmd_t *pud_pgtable(pud_t pud) { return (pmd_t *)(unsigned long)pud_val(pud); } /* only used by the stubbed out hugetlb gup code, should never be called */ #define pud_page(pud) NULL #define pud_none(x) (!pud_val(x)) #define pud_present(x) (pud_val(x)) #define pud_clear(xp) do { set_pud(xp, __pud(0)); } while (0) #define pud_bad(x) (pud_val(x) & ~PAGE_MASK) /* * (puds are folded into pgds so this doesn't get actually called, * but the define is needed for a generic inline function.) */ #define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0) #endif /* __ASM_SH_PGTABLE_3LEVEL_H */ PK ! u�oE include/asm/hardirq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HARDIRQ_H #define __ASM_SH_HARDIRQ_H extern void ack_bad_irq(unsigned int irq); #define ack_bad_irq ack_bad_irq #define ARCH_WANTS_NMI_IRQSTAT #include <asm-generic/hardirq.h> #endif /* __ASM_SH_HARDIRQ_H */ PK ! �v v_ _ include/asm/flat.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/flat.h * * uClinux flat-format executables * * Copyright (C) 2003 Paul Mundt */ #ifndef __ASM_SH_FLAT_H #define __ASM_SH_FLAT_H #include <asm/unaligned.h> static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags, u32 *addr) { *addr = get_unaligned((__force u32 *)rp); return 0; } static inline int flat_put_addr_at_rp(u32 __user *rp, u32 addr, u32 rel) { put_unaligned(addr, (__force u32 *)rp); return 0; } #define FLAT_PLAT_INIT(_r) \ do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \ _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \ _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \ _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \ _r->sr = SR_FD; } while (0) #endif /* __ASM_SH_FLAT_H */ PK ! �w� � include/asm/uaccess.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_UACCESS_H #define __ASM_SH_UACCESS_H #include <asm/segment.h> #include <asm/extable.h> #define __addr_ok(addr) \ ((unsigned long __force)(addr) < current_thread_info()->addr_limit.seg) /* * __access_ok: Check if address with size is OK or not. * * Uhhuh, this needs 33-bit arithmetic. We have a carry.. * * sum := addr + size; carry? --> flag = true; * if (sum >= addr_limit) flag = true; */ #define __access_ok(addr, size) ({ \ unsigned long __ao_a = (addr), __ao_b = (size); \ unsigned long __ao_end = __ao_a + __ao_b - !!__ao_b; \ __ao_end >= __ao_a && __addr_ok(__ao_end); }) #define access_ok(addr, size) \ (__chk_user_ptr(addr), \ __access_ok((unsigned long __force)(addr), (size))) #define user_addr_max() (current_thread_info()->addr_limit.seg) /* * Uh, these should become the main single-value transfer routines ... * They automatically use the right size if we just have the right * pointer type ... * * As SuperH uses the same address space for kernel and user data, we * can just do these as direct assignments. * * Careful to not * (a) re-use the arguments for side effects (sizeof is ok) * (b) require any knowledge of processes at this stage */ #define put_user(x,ptr) __put_user_check((x), (ptr), sizeof(*(ptr))) #define get_user(x,ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) /* * The "__xxx" versions do not do address space checking, useful when * doing multiple accesses to the same area (the user has to do the * checks by hand with "access_ok()") */ #define __put_user(x,ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr))) #define __get_user(x,ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct __user *)(x)) #define __get_user_nocheck(x,ptr,size) \ ({ \ long __gu_err; \ unsigned long __gu_val; \ const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \ __chk_user_ptr(ptr); \ __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ (x) = (__force __typeof__(*(ptr)))__gu_val; \ __gu_err; \ }) #define __get_user_check(x,ptr,size) \ ({ \ long __gu_err = -EFAULT; \ unsigned long __gu_val = 0; \ const __typeof__(*(ptr)) *__gu_addr = (ptr); \ if (likely(access_ok(__gu_addr, (size)))) \ __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ (x) = (__force __typeof__(*(ptr)))__gu_val; \ __gu_err; \ }) #define __put_user_nocheck(x,ptr,size) \ ({ \ long __pu_err; \ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ __typeof__(*(ptr)) __pu_val = x; \ __chk_user_ptr(ptr); \ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \ __pu_err; \ }) #define __put_user_check(x,ptr,size) \ ({ \ long __pu_err = -EFAULT; \ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ __typeof__(*(ptr)) __pu_val = x; \ if (likely(access_ok(__pu_addr, size))) \ __put_user_size(__pu_val, __pu_addr, (size), \ __pu_err); \ __pu_err; \ }) # include <asm/uaccess_32.h> extern long strncpy_from_user(char *dest, const char __user *src, long count); extern __must_check long strnlen_user(const char __user *str, long n); /* Generic arbitrary sized copy. */ /* Return the number of bytes NOT copied */ __kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); static __always_inline unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n) { return __copy_user(to, (__force void *)from, n); } static __always_inline unsigned long __must_check raw_copy_to_user(void __user *to, const void *from, unsigned long n) { return __copy_user((__force void *)to, from, n); } #define INLINE_COPY_FROM_USER #define INLINE_COPY_TO_USER /* * Clear the area and return remaining number of bytes * (on failure. Usually it's 0.) */ __kernel_size_t __clear_user(void *addr, __kernel_size_t size); #define clear_user(addr,n) \ ({ \ void __user * __cl_addr = (addr); \ unsigned long __cl_size = (n); \ \ if (__cl_size && access_ok(__cl_addr, __cl_size)) \ __cl_size = __clear_user(__cl_addr, __cl_size); \ \ __cl_size; \ }) extern void *set_exception_table_vec(unsigned int vec, void *handler); static inline void *set_exception_table_evt(unsigned int evt, void *handler) { return set_exception_table_vec(evt >> 5, handler); } struct mem_access { unsigned long (*from)(void *dst, const void __user *src, unsigned long cnt); unsigned long (*to)(void __user *dst, const void *src, unsigned long cnt); }; int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, struct mem_access *ma, int, unsigned long address); #endif /* __ASM_SH_UACCESS_H */ PK ! ��� � include/asm/io_trapped.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_IO_TRAPPED_H #define __ASM_SH_IO_TRAPPED_H #include <linux/list.h> #include <linux/ioport.h> #include <asm/page.h> #define IO_TRAPPED_MAGIC 0xfeedbeef struct trapped_io { unsigned int magic; struct resource *resource; unsigned int num_resources; unsigned int minimum_bus_width; struct list_head list; void __iomem *virt_base; } __aligned(PAGE_SIZE); #ifdef CONFIG_IO_TRAPPED int register_trapped_io(struct trapped_io *tiop); int handle_trapped_io(struct pt_regs *regs, unsigned long address); void __iomem *match_trapped_io_handler(struct list_head *list, unsigned long offset, unsigned long size); #ifdef CONFIG_HAS_IOMEM extern struct list_head trapped_mem; static inline void __iomem * __ioremap_trapped(unsigned long offset, unsigned long size) { return match_trapped_io_handler(&trapped_mem, offset, size); } #else #define __ioremap_trapped(offset, size) NULL #endif #ifdef CONFIG_HAS_IOPORT_MAP extern struct list_head trapped_io; static inline void __iomem * __ioport_map_trapped(unsigned long offset, unsigned long size) { return match_trapped_io_handler(&trapped_io, offset, size); } #else #define __ioport_map_trapped(offset, size) NULL #endif #else #define register_trapped_io(tiop) (-1) #define handle_trapped_io(tiop, address) 0 #define __ioremap_trapped(offset, size) NULL #define __ioport_map_trapped(offset, size) NULL #endif #endif /* __ASM_SH_IO_TRAPPED_H */ PK ! � �G G include/asm/cache_insns.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <asm/cache_insns_32.h> PK ! ���,� � include/asm/rtc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_RTC_H #define _ASM_RTC_H void time_init(void); #define RTC_CAP_4_DIGIT_YEAR (1 << 0) struct sh_rtc_platform_info { unsigned long capabilities; }; #include <cpu/rtc.h> #endif /* _ASM_RTC_H */ PK ! ��U� � include/asm/reboot.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_REBOOT_H #define __ASM_SH_REBOOT_H #include <linux/kdebug.h> struct pt_regs; struct machine_ops { void (*restart)(char *cmd); void (*halt)(void); void (*power_off)(void); void (*shutdown)(void); void (*crash_shutdown)(struct pt_regs *); }; extern struct machine_ops machine_ops; /* arch/sh/kernel/machine_kexec.c */ void native_machine_crash_shutdown(struct pt_regs *regs); #endif /* __ASM_SH_REBOOT_H */ PK ! z��r� � include/asm/adc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ADC_H #define __ASM_ADC_H /* * Copyright (C) 2004 Andriy Skulysh */ #include <cpu/adc.h> int adc_single(unsigned int channel); #endif /* __ASM_ADC_H */ PK ! �h��D D include/asm/dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/dma.h * * Copyright (C) 2003, 2004 Paul Mundt */ #ifndef __ASM_SH_DMA_H #define __ASM_SH_DMA_H #include <linux/spinlock.h> #include <linux/wait.h> #include <linux/sched.h> #include <linux/device.h> #include <asm-generic/dma.h> /* * Read and write modes can mean drastically different things depending on the * channel configuration. Consult your DMAC documentation and module * implementation for further clues. */ #define DMA_MODE_READ 0x00 #define DMA_MODE_WRITE 0x01 #define DMA_MODE_MASK 0x01 #define DMA_AUTOINIT 0x10 /* * DMAC (dma_info) flags */ enum { DMAC_CHANNELS_CONFIGURED = 0x01, DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */ }; /* * DMA channel capabilities / flags */ enum { DMA_CONFIGURED = 0x01, /* * Transfer end interrupt, inherited from DMAC. * wait_queue used in dma_wait_for_completion. */ DMA_TEI_CAPABLE = 0x02, }; extern spinlock_t dma_spin_lock; struct dma_channel; struct dma_ops { int (*request)(struct dma_channel *chan); void (*free)(struct dma_channel *chan); int (*get_residue)(struct dma_channel *chan); int (*xfer)(struct dma_channel *chan); int (*configure)(struct dma_channel *chan, unsigned long flags); int (*extend)(struct dma_channel *chan, unsigned long op, void *param); }; struct dma_channel { char dev_id[16]; /* unique name per DMAC of channel */ unsigned int chan; /* DMAC channel number */ unsigned int vchan; /* Virtual channel number */ unsigned int mode; unsigned int count; unsigned long sar; unsigned long dar; const char **caps; unsigned long flags; atomic_t busy; wait_queue_head_t wait_queue; struct device dev; void *priv_data; }; struct dma_info { struct platform_device *pdev; const char *name; unsigned int nr_channels; unsigned long flags; struct dma_ops *ops; struct dma_channel *channels; struct list_head list; int first_channel_nr; int first_vchannel_nr; }; struct dma_chan_caps { int ch_num; const char **caplist; }; #define to_dma_channel(channel) container_of(channel, struct dma_channel, dev) /* arch/sh/drivers/dma/dma-api.c */ extern int dma_xfer(unsigned int chan, unsigned long from, unsigned long to, size_t size, unsigned int mode); #define dma_write(chan, from, to, size) \ dma_xfer(chan, from, to, size, DMA_MODE_WRITE) #define dma_write_page(chan, from, to) \ dma_write(chan, from, to, PAGE_SIZE) #define dma_read(chan, from, to, size) \ dma_xfer(chan, from, to, size, DMA_MODE_READ) #define dma_read_page(chan, from, to) \ dma_read(chan, from, to, PAGE_SIZE) extern int request_dma_bycap(const char **dmac, const char **caps, const char *dev_id); extern int get_dma_residue(unsigned int chan); extern struct dma_info *get_dma_info(unsigned int chan); extern struct dma_channel *get_dma_channel(unsigned int chan); extern void dma_wait_for_completion(unsigned int chan); extern void dma_configure_channel(unsigned int chan, unsigned long flags); extern int register_dmac(struct dma_info *info); extern void unregister_dmac(struct dma_info *info); extern struct dma_info *get_dma_info_by_name(const char *dmac_name); extern int dma_extend(unsigned int chan, unsigned long op, void *param); extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist); /* arch/sh/drivers/dma/dma-sysfs.c */ extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *); extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *); #ifdef CONFIG_PCI extern int isa_dma_bridge_buggy; #else #define isa_dma_bridge_buggy (0) #endif #endif /* __ASM_SH_DMA_H */ PK ! ����� � include/asm/fixmap.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * fixmap.h: compile-time virtual memory allocation * * Copyright (C) 1998 Ingo Molnar * * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 */ #ifndef _ASM_FIXMAP_H #define _ASM_FIXMAP_H #include <linux/kernel.h> #include <linux/threads.h> #include <asm/page.h> /* * Here we define all the compile-time 'special' virtual * addresses. The point is to have a constant address at * compile time, but to set the physical address only * in the boot process. We allocate these special addresses * from the end of P3 backwards. * Also this lets us do fail-safe vmalloc(), we * can guarantee that these special addresses and * vmalloc()-ed addresses never overlap. * * these 'compile-time allocated' memory buffers are * fixed-size 4k pages. (or larger if used with an increment * highger than 1) use fixmap_set(idx,phys) to associate * physical memory with fixmap indices. * * TLB entries of such buffers will not be flushed across * task switches. */ /* * on UP currently we will have no trace of the fixmap mechanizm, * no page table allocations, etc. This might change in the * future, say framebuffers for the console driver(s) could be * fix-mapped? */ enum fixed_addresses { /* * The FIX_CMAP entries are used by kmap_coherent() to get virtual * addresses which are of a known color, and so their values are * important. __fix_to_virt(FIX_CMAP_END - n) must give an address * which is the same color as a page (n<<PAGE_SHIFT). */ #define FIX_N_COLOURS 8 FIX_CMAP_BEGIN, FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS) - 1, #ifdef CONFIG_IOREMAP_FIXED /* * FIX_IOREMAP entries are useful for mapping physical address * space before ioremap() is useable, e.g. really early in boot * before kmalloc() is working. */ #define FIX_N_IOREMAPS 32 FIX_IOREMAP_BEGIN, FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS - 1, #endif __end_of_fixed_addresses }; extern void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t flags); extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags); /* * used by vmalloc.c. * * Leave one empty page between vmalloc'ed areas and * the start of the fixmap, and leave one page empty * at the top of mem.. */ #define FIXADDR_TOP (P4SEG - PAGE_SIZE) #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) #define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NOCACHE #include <asm-generic/fixmap.h> #endif PK ! ��ǡ� � include/asm/futex-cas.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_FUTEX_CAS_H #define __ASM_SH_FUTEX_CAS_H static inline int atomic_futex_op_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { int err = 0; __asm__ __volatile__( "1:\n\t" "cas.l %2, %1, @r0\n" "2:\n\t" #ifdef CONFIG_MMU ".section .fixup,\"ax\"\n" "3:\n\t" "mov.l 4f, %0\n\t" "jmp @%0\n\t" " mov %3, %0\n\t" ".balign 4\n" "4: .long 2b\n\t" ".previous\n" ".section __ex_table,\"a\"\n\t" ".long 1b, 3b\n\t" ".previous" #endif :"+r" (err), "+r" (newval) :"r" (oldval), "i" (-EFAULT), "z" (uaddr) :"t", "memory"); if (err) return err; *uval = newval; return 0; } #endif /* __ASM_SH_FUTEX_CAS_H */ PK ! N(l/ / include/asm/switch_to_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SWITCH_TO_32_H #define __ASM_SH_SWITCH_TO_32_H #ifdef CONFIG_SH_DSP #define is_dsp_enabled(tsk) \ (!!(tsk->thread.dsp_status.status & SR_DSP)) #define __restore_dsp(tsk) \ do { \ register u32 *__ts2 __asm__ ("r2") = \ (u32 *)&tsk->thread.dsp_status; \ __asm__ __volatile__ ( \ ".balign 4\n\t" \ "movs.l @r2+, a0\n\t" \ "movs.l @r2+, a1\n\t" \ "movs.l @r2+, a0g\n\t" \ "movs.l @r2+, a1g\n\t" \ "movs.l @r2+, m0\n\t" \ "movs.l @r2+, m1\n\t" \ "movs.l @r2+, x0\n\t" \ "movs.l @r2+, x1\n\t" \ "movs.l @r2+, y0\n\t" \ "movs.l @r2+, y1\n\t" \ "lds.l @r2+, dsr\n\t" \ "ldc.l @r2+, rs\n\t" \ "ldc.l @r2+, re\n\t" \ "ldc.l @r2+, mod\n\t" \ : : "r" (__ts2)); \ } while (0) #define __save_dsp(tsk) \ do { \ register u32 *__ts2 __asm__ ("r2") = \ (u32 *)&tsk->thread.dsp_status + 14; \ \ __asm__ __volatile__ ( \ ".balign 4\n\t" \ "stc.l mod, @-r2\n\t" \ "stc.l re, @-r2\n\t" \ "stc.l rs, @-r2\n\t" \ "sts.l dsr, @-r2\n\t" \ "movs.l y1, @-r2\n\t" \ "movs.l y0, @-r2\n\t" \ "movs.l x1, @-r2\n\t" \ "movs.l x0, @-r2\n\t" \ "movs.l m1, @-r2\n\t" \ "movs.l m0, @-r2\n\t" \ "movs.l a1g, @-r2\n\t" \ "movs.l a0g, @-r2\n\t" \ "movs.l a1, @-r2\n\t" \ "movs.l a0, @-r2\n\t" \ : : "r" (__ts2)); \ } while (0) #else #define is_dsp_enabled(tsk) (0) #define __save_dsp(tsk) do { } while (0) #define __restore_dsp(tsk) do { } while (0) #endif struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next); /* * switch_to() should switch tasks to task nr n, first */ #define switch_to(prev, next, last) \ do { \ register u32 *__ts1 __asm__ ("r1"); \ register u32 *__ts2 __asm__ ("r2"); \ register u32 *__ts4 __asm__ ("r4"); \ register u32 *__ts5 __asm__ ("r5"); \ register u32 *__ts6 __asm__ ("r6"); \ register u32 __ts7 __asm__ ("r7"); \ struct task_struct *__last; \ \ if (is_dsp_enabled(prev)) \ __save_dsp(prev); \ if (is_dsp_enabled(next)) \ __restore_dsp(next); \ \ __ts1 = (u32 *)&prev->thread.sp; \ __ts2 = (u32 *)&prev->thread.pc; \ __ts4 = (u32 *)prev; \ __ts5 = (u32 *)next; \ __ts6 = (u32 *)&next->thread.sp; \ __ts7 = next->thread.pc; \ \ __asm__ __volatile__ ( \ ".balign 4\n\t" \ "stc.l gbr, @-r15\n\t" \ "sts.l pr, @-r15\n\t" \ "mov.l r8, @-r15\n\t" \ "mov.l r9, @-r15\n\t" \ "mov.l r10, @-r15\n\t" \ "mov.l r11, @-r15\n\t" \ "mov.l r12, @-r15\n\t" \ "mov.l r13, @-r15\n\t" \ "mov.l r14, @-r15\n\t" \ "mov.l r15, @r1\t! save SP\n\t" \ "mov.l @r6, r15\t! change to new stack\n\t" \ "mova 1f, %0\n\t" \ "mov.l %0, @r2\t! save PC\n\t" \ "mov.l 2f, %0\n\t" \ "jmp @%0\t! call __switch_to\n\t" \ " lds r7, pr\t! with return to new PC\n\t" \ ".balign 4\n" \ "2:\n\t" \ ".long __switch_to\n" \ "1:\n\t" \ "mov.l @r15+, r14\n\t" \ "mov.l @r15+, r13\n\t" \ "mov.l @r15+, r12\n\t" \ "mov.l @r15+, r11\n\t" \ "mov.l @r15+, r10\n\t" \ "mov.l @r15+, r9\n\t" \ "mov.l @r15+, r8\n\t" \ "lds.l @r15+, pr\n\t" \ "ldc.l @r15+, gbr\n\t" \ : "=z" (__last) \ : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ "r" (__ts5), "r" (__ts6), "r" (__ts7) \ : "r3", "t"); \ \ last = __last; \ } while (0) #endif /* __ASM_SH_SWITCH_TO_32_H */ PK ! �b���! �! include/asm/io.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_IO_H #define __ASM_SH_IO_H /* * Convention: * read{b,w,l,q}/write{b,w,l,q} are for PCI, * while in{b,w,l}/out{b,w,l} are for ISA * * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p * and 'string' versions: ins{b,w,l}/outs{b,w,l} * * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers * automatically, there are also __raw versions, which do not. */ #include <linux/errno.h> #include <asm/cache.h> #include <asm/addrspace.h> #include <asm/machvec.h> #include <asm/page.h> #include <linux/pgtable.h> #include <asm-generic/iomap.h> #define __IO_PREFIX generic #include <asm/io_generic.h> #include <asm-generic/pci_iomap.h> #include <mach/mangle-port.h> #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a)) #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a)) #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) #define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; }) #define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; }) #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; }) #define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; }) #define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c)) #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c)) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; }) #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; }) #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; }) #define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; }) #define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); }) #define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); }) #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); }) #define readsb(p,d,l) __raw_readsb(p,d,l) #define readsw(p,d,l) __raw_readsw(p,d,l) #define readsl(p,d,l) __raw_readsl(p,d,l) #define writesb(p,d,l) __raw_writesb(p,d,l) #define writesw(p,d,l) __raw_writesw(p,d,l) #define writesl(p,d,l) __raw_writesl(p,d,l) #define __BUILD_UNCACHED_IO(bwlq, type) \ static inline type read##bwlq##_uncached(unsigned long addr) \ { \ type ret; \ jump_to_uncached(); \ ret = __raw_read##bwlq(addr); \ back_to_cached(); \ return ret; \ } \ \ static inline void write##bwlq##_uncached(type v, unsigned long addr) \ { \ jump_to_uncached(); \ __raw_write##bwlq(v, addr); \ back_to_cached(); \ } __BUILD_UNCACHED_IO(b, u8) __BUILD_UNCACHED_IO(w, u16) __BUILD_UNCACHED_IO(l, u32) __BUILD_UNCACHED_IO(q, u64) #define __BUILD_MEMORY_STRING(pfx, bwlq, type) \ \ static inline void \ pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \ unsigned int count) \ { \ const volatile type *__addr = addr; \ \ while (count--) { \ __raw_write##bwlq(*__addr, mem); \ __addr++; \ } \ } \ \ static inline void pfx##reads##bwlq(volatile void __iomem *mem, \ void *addr, unsigned int count) \ { \ volatile type *__addr = addr; \ \ while (count--) { \ *__addr = __raw_read##bwlq(mem); \ __addr++; \ } \ } __BUILD_MEMORY_STRING(__raw_, b, u8) __BUILD_MEMORY_STRING(__raw_, w, u16) void __raw_writesl(void __iomem *addr, const void *data, int longlen); void __raw_readsl(const void __iomem *addr, void *data, int longlen); __BUILD_MEMORY_STRING(__raw_, q, u64) #ifdef CONFIG_HAS_IOPORT_MAP /* * Slowdown I/O port space accesses for antique hardware. */ #undef CONF_SLOWDOWN_IO /* * On SuperH I/O ports are memory mapped, so we access them using normal * load/store instructions. sh_io_port_base is the virtual address to * which all ports are being mapped. */ extern unsigned long sh_io_port_base; static inline void __set_io_port_base(unsigned long pbase) { *(unsigned long *)&sh_io_port_base = pbase; barrier(); } #ifdef CONFIG_GENERIC_IOMAP #define __ioport_map ioport_map #else extern void __iomem *__ioport_map(unsigned long addr, unsigned int size); #endif #ifdef CONF_SLOWDOWN_IO #define SLOW_DOWN_IO __raw_readw(sh_io_port_base) #else #define SLOW_DOWN_IO #endif #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ \ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ { \ volatile type *__addr; \ \ __addr = __ioport_map(port, sizeof(type)); \ *__addr = val; \ slow; \ } \ \ static inline type pfx##in##bwlq##p(unsigned long port) \ { \ volatile type *__addr; \ type __val; \ \ __addr = __ioport_map(port, sizeof(type)); \ __val = *__addr; \ slow; \ \ return __val; \ } #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) #define BUILDIO_IOPORT(bwlq, type) \ __BUILD_IOPORT_PFX(, bwlq, type) BUILDIO_IOPORT(b, u8) BUILDIO_IOPORT(w, u16) BUILDIO_IOPORT(l, u32) BUILDIO_IOPORT(q, u64) #define __BUILD_IOPORT_STRING(bwlq, type) \ \ static inline void outs##bwlq(unsigned long port, const void *addr, \ unsigned int count) \ { \ const volatile type *__addr = addr; \ \ while (count--) { \ out##bwlq(*__addr, port); \ __addr++; \ } \ } \ \ static inline void ins##bwlq(unsigned long port, void *addr, \ unsigned int count) \ { \ volatile type *__addr = addr; \ \ while (count--) { \ *__addr = in##bwlq(port); \ __addr++; \ } \ } __BUILD_IOPORT_STRING(b, u8) __BUILD_IOPORT_STRING(w, u16) __BUILD_IOPORT_STRING(l, u32) __BUILD_IOPORT_STRING(q, u64) #else /* !CONFIG_HAS_IOPORT_MAP */ #include <asm/io_noioport.h> #endif #define IO_SPACE_LIMIT 0xffffffff /* We really want to try and get these to memcpy etc */ void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); void memcpy_toio(volatile void __iomem *, const void *, unsigned long); void memset_io(volatile void __iomem *, int, unsigned long); /* Quad-word real-mode I/O, don't ask.. */ unsigned long long peek_real_address_q(unsigned long long addr); unsigned long long poke_real_address_q(unsigned long long addr, unsigned long long val); #if !defined(CONFIG_MMU) #define virt_to_phys(address) ((unsigned long)(address)) #define phys_to_virt(address) ((void *)(address)) #else #define virt_to_phys(address) (__pa(address)) #define phys_to_virt(address) (__va(address)) #endif #ifdef CONFIG_MMU void iounmap(void __iomem *addr); void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size, pgprot_t prot, void *caller); static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) { return __ioremap_caller(offset, size, PAGE_KERNEL_NOCACHE, __builtin_return_address(0)); } static inline void __iomem * ioremap_cache(phys_addr_t offset, unsigned long size) { return __ioremap_caller(offset, size, PAGE_KERNEL, __builtin_return_address(0)); } #define ioremap_cache ioremap_cache #ifdef CONFIG_HAVE_IOREMAP_PROT static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags) { return __ioremap_caller(offset, size, __pgprot(flags), __builtin_return_address(0)); } #endif /* CONFIG_HAVE_IOREMAP_PROT */ #else /* CONFIG_MMU */ static inline void __iomem *ioremap(phys_addr_t offset, size_t size) { return (void __iomem *)(unsigned long)offset; } static inline void iounmap(volatile void __iomem *addr) { } #endif /* CONFIG_MMU */ #define ioremap_uc ioremap /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem * access */ #define xlate_dev_mem_ptr(p) __va(p) #define ARCH_HAS_VALID_PHYS_ADDR_RANGE int valid_phys_addr_range(phys_addr_t addr, size_t size); int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); #endif /* __ASM_SH_IO_H */ PK ! � �p p include/asm/kexec.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_KEXEC_H #define __ASM_SH_KEXEC_H #include <asm/ptrace.h> #include <asm/string.h> #include <linux/kernel.h> /* * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return. * I.e. Maximum page that is mapped directly into kernel memory, * and kmap is not required. * * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct * calculation for the amount of memory directly mappable into the * kernel memory space. */ /* Maximum physical address we can use pages from */ #define KEXEC_SOURCE_MEMORY_LIMIT (-1UL) /* Maximum address we can reach in physical address mode */ #define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL) /* Maximum address we can use for the control code buffer */ #define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE #define KEXEC_CONTROL_PAGE_SIZE 4096 /* The native architecture */ #define KEXEC_ARCH KEXEC_ARCH_SH #ifdef CONFIG_KEXEC /* arch/sh/kernel/machine_kexec.c */ void reserve_crashkernel(void); static inline void crash_setup_regs(struct pt_regs *newregs, struct pt_regs *oldregs) { if (oldregs) memcpy(newregs, oldregs, sizeof(*newregs)); else { __asm__ __volatile__ ("mov r0, %0" : "=r" (newregs->regs[0])); __asm__ __volatile__ ("mov r1, %0" : "=r" (newregs->regs[1])); __asm__ __volatile__ ("mov r2, %0" : "=r" (newregs->regs[2])); __asm__ __volatile__ ("mov r3, %0" : "=r" (newregs->regs[3])); __asm__ __volatile__ ("mov r4, %0" : "=r" (newregs->regs[4])); __asm__ __volatile__ ("mov r5, %0" : "=r" (newregs->regs[5])); __asm__ __volatile__ ("mov r6, %0" : "=r" (newregs->regs[6])); __asm__ __volatile__ ("mov r7, %0" : "=r" (newregs->regs[7])); __asm__ __volatile__ ("mov r8, %0" : "=r" (newregs->regs[8])); __asm__ __volatile__ ("mov r9, %0" : "=r" (newregs->regs[9])); __asm__ __volatile__ ("mov r10, %0" : "=r" (newregs->regs[10])); __asm__ __volatile__ ("mov r11, %0" : "=r" (newregs->regs[11])); __asm__ __volatile__ ("mov r12, %0" : "=r" (newregs->regs[12])); __asm__ __volatile__ ("mov r13, %0" : "=r" (newregs->regs[13])); __asm__ __volatile__ ("mov r14, %0" : "=r" (newregs->regs[14])); __asm__ __volatile__ ("mov r15, %0" : "=r" (newregs->regs[15])); __asm__ __volatile__ ("sts pr, %0" : "=r" (newregs->pr)); __asm__ __volatile__ ("sts macl, %0" : "=r" (newregs->macl)); __asm__ __volatile__ ("sts mach, %0" : "=r" (newregs->mach)); __asm__ __volatile__ ("stc gbr, %0" : "=r" (newregs->gbr)); __asm__ __volatile__ ("stc sr, %0" : "=r" (newregs->sr)); newregs->pc = _THIS_IP_; } } #else static inline void reserve_crashkernel(void) { } #endif /* CONFIG_KEXEC */ #endif /* __ASM_SH_KEXEC_H */ PK ! �� �� � include/asm/switch_to.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2000, 2001 Paolo Alberelli * Copyright (C) 2003 Paul Mundt * Copyright (C) 2004 Richard Curnow */ #include <asm/switch_to_32.h> PK ! ~ھ� � include/asm/pgtable.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * This file contains the functions and defines necessary to modify and * use the SuperH page table tree. * * Copyright (C) 1999 Niibe Yutaka * Copyright (C) 2002 - 2007 Paul Mundt */ #ifndef __ASM_SH_PGTABLE_H #define __ASM_SH_PGTABLE_H #ifdef CONFIG_X2TLB #include <asm/pgtable-3level.h> #else #include <asm/pgtable-2level.h> #endif #include <asm/page.h> #include <asm/mmu.h> #ifndef __ASSEMBLY__ #include <asm/addrspace.h> #include <asm/fixmap.h> /* * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. */ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) #endif /* !__ASSEMBLY__ */ /* * Effective and physical address definitions, to aid with sign * extension. */ #define NEFF 32 #define NEFF_SIGN (1LL << (NEFF - 1)) #define NEFF_MASK (-1LL << NEFF) static inline unsigned long long neff_sign_extend(unsigned long val) { unsigned long long extended = val; return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended; } #ifdef CONFIG_29BIT #define NPHYS 29 #else #define NPHYS 32 #endif #define NPHYS_SIGN (1LL << (NPHYS - 1)) #define NPHYS_MASK (-1LL << NPHYS) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* Entries per level */ #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) #define PHYS_ADDR_MASK29 0x1fffffff #define PHYS_ADDR_MASK32 0xffffffff static inline unsigned long phys_addr_mask(void) { /* Is the MMU in 29bit mode? */ if (__in_29bit_mode()) return PHYS_ADDR_MASK29; return PHYS_ADDR_MASK32; } #define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK) #define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT) #define VMALLOC_START (P3SEG) #define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) #include <asm/pgtable_32.h> /* * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page * protection for execute, and considers it the same as a read. Also, write * permission implies read permission. This is the closest we can get.. * * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme, * not only supporting separate execute, read, and write bits, but having * completely separate permission bits for user and kernel space. */ /*xwr*/ #define __P000 PAGE_NONE #define __P001 PAGE_READONLY #define __P010 PAGE_COPY #define __P011 PAGE_COPY #define __P100 PAGE_EXECREAD #define __P101 PAGE_EXECREAD #define __P110 PAGE_COPY #define __P111 PAGE_COPY #define __S000 PAGE_NONE #define __S001 PAGE_READONLY #define __S010 PAGE_WRITEONLY #define __S011 PAGE_SHARED #define __S100 PAGE_EXECREAD #define __S101 PAGE_EXECREAD #define __S110 PAGE_RWX #define __S111 PAGE_RWX typedef pte_t *pte_addr_t; #define kern_addr_valid(addr) (1) #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT))) struct vm_area_struct; struct mm_struct; extern void __update_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte); extern void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte); static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) { pte_t pte = *ptep; __update_cache(vma, address, pte); __update_tlb(vma, address, pte); } extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init(void); extern void page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd); static inline bool __pte_access_permitted(pte_t pte, u64 prot) { return (pte_val(pte) & (prot | _PAGE_SPECIAL)) == prot; } #ifdef CONFIG_X2TLB static inline bool pte_access_permitted(pte_t pte, bool write) { u64 prot = _PAGE_PRESENT; prot |= _PAGE_EXT(_PAGE_EXT_KERN_READ | _PAGE_EXT_USER_READ); if (write) prot |= _PAGE_EXT(_PAGE_EXT_KERN_WRITE | _PAGE_EXT_USER_WRITE); return __pte_access_permitted(pte, prot); } #else static inline bool pte_access_permitted(pte_t pte, bool write) { u64 prot = _PAGE_PRESENT | _PAGE_USER; if (write) prot |= _PAGE_RW; return __pte_access_permitted(pte, prot); } #endif #define pte_access_permitted pte_access_permitted /* arch/sh/mm/mmap.c */ #define HAVE_ARCH_UNMAPPED_AREA #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN #endif /* __ASM_SH_PGTABLE_H */ PK ! [�s include/asm/suspend.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SH_SUSPEND_H #define _ASM_SH_SUSPEND_H #ifndef __ASSEMBLY__ #include <linux/notifier.h> #include <asm/ptrace.h> struct swsusp_arch_regs { struct pt_regs user_regs; unsigned long bank1_regs[8]; }; void sh_mobile_call_standby(unsigned long mode); #ifdef CONFIG_CPU_IDLE int sh_mobile_setup_cpuidle(void); #else static inline int sh_mobile_setup_cpuidle(void) { return 0; } #endif /* notifier chains for pre/post sleep hooks */ extern struct atomic_notifier_head sh_mobile_pre_sleep_notifier_list; extern struct atomic_notifier_head sh_mobile_post_sleep_notifier_list; /* priority levels for notifiers */ #define SH_MOBILE_SLEEP_BOARD 0 #define SH_MOBILE_SLEEP_CPU 1 #define SH_MOBILE_PRE(x) (x) #define SH_MOBILE_POST(x) (-(x)) /* board code registration function for self-refresh assembly snippets */ void sh_mobile_register_self_refresh(unsigned long flags, void *pre_start, void *pre_end, void *post_start, void *post_end); /* register structure for address/data information */ struct sh_sleep_regs { unsigned long stbcr; unsigned long bar; /* MMU */ unsigned long pteh; unsigned long ptel; unsigned long ttb; unsigned long tea; unsigned long mmucr; unsigned long ptea; unsigned long pascr; unsigned long irmcr; /* Cache */ unsigned long ccr; unsigned long ramcr; }; /* data area for low-level sleep code */ struct sh_sleep_data { /* current sleep mode (SUSP_SH_...) */ unsigned long mode; /* addresses of board specific self-refresh snippets */ unsigned long sf_pre; unsigned long sf_post; /* address of resume code */ unsigned long resume; /* register state saved and restored by the assembly code */ unsigned long vbr; unsigned long spc; unsigned long sr; unsigned long sp; /* structure for keeping register addresses */ struct sh_sleep_regs addr; /* structure for saving/restoring register state */ struct sh_sleep_regs data; }; /* a bitmap of supported sleep modes (SUSP_SH..) */ extern unsigned long sh_mobile_sleep_supported; #endif /* flags passed to assembly suspend code */ #define SUSP_SH_SLEEP (1 << 0) /* Regular sleep mode */ #define SUSP_SH_STANDBY (1 << 1) /* SH-Mobile Software standby mode */ #define SUSP_SH_RSTANDBY (1 << 2) /* SH-Mobile R-standby mode */ #define SUSP_SH_USTANDBY (1 << 3) /* SH-Mobile U-standby mode */ #define SUSP_SH_SF (1 << 4) /* Enable self-refresh */ #define SUSP_SH_MMU (1 << 5) /* Save/restore MMU and cache */ #define SUSP_SH_REGS (1 << 6) /* Save/restore registers */ #endif /* _ASM_SH_SUSPEND_H */ PK ! ɖ-�% % include/asm/cmpxchg-cas.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CMPXCHG_CAS_H #define __ASM_SH_CMPXCHG_CAS_H static inline unsigned long __cmpxchg_u32(volatile u32 *m, unsigned long old, unsigned long new) { __asm__ __volatile__("cas.l %1,%0,@r0" : "+r"(new) : "r"(old), "z"(m) : "t", "memory" ); return new; } static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) { unsigned long old; do old = *m; while (__cmpxchg_u32(m, old, val) != old); return old; } #include <asm/cmpxchg-xchg.h> #endif /* __ASM_SH_CMPXCHG_CAS_H */ PK ! ��x�y y include/asm/elf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_ELF_H #define __ASM_SH_ELF_H #include <linux/utsname.h> #include <asm/auxvec.h> #include <asm/ptrace.h> #include <asm/user.h> /* ELF header e_flags defines */ #define EF_SH_PIC 0x100 /* -fpic */ #define EF_SH_FDPIC 0x8000 /* -mfdpic */ /* SH (particularly SHcompact) relocation types */ #define R_SH_NONE 0 #define R_SH_DIR32 1 #define R_SH_REL32 2 #define R_SH_DIR8WPN 3 #define R_SH_IND12W 4 #define R_SH_DIR8WPL 5 #define R_SH_DIR8WPZ 6 #define R_SH_DIR8BP 7 #define R_SH_DIR8W 8 #define R_SH_DIR8L 9 #define R_SH_SWITCH16 25 #define R_SH_SWITCH32 26 #define R_SH_USES 27 #define R_SH_COUNT 28 #define R_SH_ALIGN 29 #define R_SH_CODE 30 #define R_SH_DATA 31 #define R_SH_LABEL 32 #define R_SH_SWITCH8 33 #define R_SH_GNU_VTINHERIT 34 #define R_SH_GNU_VTENTRY 35 #define R_SH_TLS_GD_32 144 #define R_SH_TLS_LD_32 145 #define R_SH_TLS_LDO_32 146 #define R_SH_TLS_IE_32 147 #define R_SH_TLS_LE_32 148 #define R_SH_TLS_DTPMOD32 149 #define R_SH_TLS_DTPOFF32 150 #define R_SH_TLS_TPOFF32 151 #define R_SH_GOT32 160 #define R_SH_PLT32 161 #define R_SH_COPY 162 #define R_SH_GLOB_DAT 163 #define R_SH_JMP_SLOT 164 #define R_SH_RELATIVE 165 #define R_SH_GOTOFF 166 #define R_SH_GOTPC 167 /* FDPIC relocs */ #define R_SH_GOT20 201 #define R_SH_GOTOFF20 202 #define R_SH_GOTFUNCDESC 203 #define R_SH_GOTFUNCDESC20 204 #define R_SH_GOTOFFFUNCDESC 205 #define R_SH_GOTOFFFUNCDESC20 206 #define R_SH_FUNCDESC 207 #define R_SH_FUNCDESC_VALUE 208 /* SHmedia relocs */ #define R_SH_IMM_LOW16 246 #define R_SH_IMM_LOW16_PCREL 247 #define R_SH_IMM_MEDLOW16 248 #define R_SH_IMM_MEDLOW16_PCREL 249 /* Keep this the last entry. */ #define R_SH_NUM 256 /* * ELF register definitions.. */ typedef unsigned long elf_greg_t; #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef struct user_fpu_struct elf_fpregset_t; /* * These are used to set parameters in the core dumps. */ #define ELF_CLASS ELFCLASS32 #ifdef __LITTLE_ENDIAN__ #define ELF_DATA ELFDATA2LSB #else #define ELF_DATA ELFDATA2MSB #endif #define ELF_ARCH EM_SH /* * This is used to ensure we don't load something for the wrong architecture. */ #define elf_check_arch(x) ((x)->e_machine == EM_SH) #define elf_check_fdpic(x) ((x)->e_flags & EF_SH_FDPIC) #define elf_check_const_displacement(x) ((x)->e_flags & EF_SH_PIC) /* * Enable dump using regset. * This covers all of general/DSP/FPU regs. */ #define CORE_DUMP_USE_REGSET #define ELF_FDPIC_CORE_EFLAGS EF_SH_FDPIC #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This is the location that an ET_DYN program is loaded if exec'ed. Typical use of this is to invoke "./ld.so someprog" to test out a new version of the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) #define ELF_CORE_COPY_REGS(_dest,_regs) \ memcpy((char *) &_dest, (char *) _regs, \ sizeof(struct pt_regs)); /* This yields a mask that user programs can use to figure out what instruction set this CPU supports. This could be done in user space, but it's not easy, and we've already done it here. */ #define ELF_HWCAP (boot_cpu_data.flags) /* This yields a string that ld.so will use to load implementation specific libraries for optimization. This is more specific in intent than poking at uname or /proc/cpuinfo. For the moment, we have only optimizations for the Intel generations, but that could change... */ #define ELF_PLATFORM (utsname()->machine) #define ELF_PLAT_INIT(_r, load_addr) \ do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \ _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \ _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \ _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \ _r->sr = SR_FD; } while (0) #define ELF_FDPIC_PLAT_INIT(_r, _exec_map_addr, _interp_map_addr, \ _dynamic_addr) \ do { \ _r->regs[0] = 0; \ _r->regs[1] = 0; \ _r->regs[2] = 0; \ _r->regs[3] = 0; \ _r->regs[4] = 0; \ _r->regs[5] = 0; \ _r->regs[6] = 0; \ _r->regs[7] = 0; \ _r->regs[8] = _exec_map_addr; \ _r->regs[9] = _interp_map_addr; \ _r->regs[10] = _dynamic_addr; \ _r->regs[11] = 0; \ _r->regs[12] = 0; \ _r->regs[13] = 0; \ _r->regs[14] = 0; \ _r->sr = SR_FD; \ } while (0) #define SET_PERSONALITY(ex) \ set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK))) #ifdef CONFIG_VSYSCALL /* vDSO has arch_setup_additional_pages */ #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; extern int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp); extern unsigned int vdso_enabled; extern void __kernel_vsyscall; #define VDSO_BASE ((unsigned long)current->mm->context.vdso) #define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x)) #define VSYSCALL_AUX_ENT \ if (vdso_enabled) \ NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE); \ else \ NEW_AUX_ENT(AT_IGNORE, 0) #else #define VSYSCALL_AUX_ENT NEW_AUX_ENT(AT_IGNORE, 0) #endif /* CONFIG_VSYSCALL */ #ifdef CONFIG_SH_FPU #define FPU_AUX_ENT NEW_AUX_ENT(AT_FPUCW, FPSCR_INIT) #else #define FPU_AUX_ENT NEW_AUX_ENT(AT_IGNORE, 0) #endif extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape; /* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */ #define ARCH_DLINFO \ do { \ /* Optional FPU initialization */ \ FPU_AUX_ENT; \ \ /* Optional vsyscall entry */ \ VSYSCALL_AUX_ENT; \ \ /* Cache desc */ \ NEW_AUX_ENT(AT_L1I_CACHESHAPE, l1i_cache_shape); \ NEW_AUX_ENT(AT_L1D_CACHESHAPE, l1d_cache_shape); \ NEW_AUX_ENT(AT_L2_CACHESHAPE, l2_cache_shape); \ } while (0) #endif /* __ASM_SH_ELF_H */ PK ! �7F�) ) include/asm/cmpxchg-irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CMPXCHG_IRQ_H #define __ASM_SH_CMPXCHG_IRQ_H #include <linux/irqflags.h> static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) { unsigned long flags, retval; local_irq_save(flags); retval = *m; *m = val; local_irq_restore(flags); return retval; } static inline unsigned long xchg_u16(volatile u16 *m, unsigned long val) { unsigned long flags, retval; local_irq_save(flags); retval = *m; *m = val; local_irq_restore(flags); return retval; } static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) { unsigned long flags, retval; local_irq_save(flags); retval = *m; *m = val & 0xff; local_irq_restore(flags); return retval; } static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new) { __u32 retval; unsigned long flags; local_irq_save(flags); retval = *m; if (retval == old) *m = new; local_irq_restore(flags); /* implies memory barrier */ return retval; } #endif /* __ASM_SH_CMPXCHG_IRQ_H */ PK ! ��� � include/asm/syscalls.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SYSCALLS_H #define __ASM_SH_SYSCALLS_H asmlinkage int old_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, int fd, unsigned long off); asmlinkage long sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, unsigned long fd, unsigned long pgoff); #include <asm/syscalls_32.h> #endif /* __ASM_SH_SYSCALLS_H */ PK ! ��� � include/asm/smp-ops.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SMP_OPS_H #define __ASM_SH_SMP_OPS_H struct plat_smp_ops { void (*smp_setup)(void); unsigned int (*smp_processor_id)(void); void (*prepare_cpus)(unsigned int max_cpus); void (*start_cpu)(unsigned int cpu, unsigned long entry_point); void (*send_ipi)(unsigned int cpu, unsigned int message); int (*cpu_disable)(unsigned int cpu); void (*cpu_die)(unsigned int cpu); void (*play_dead)(void); }; extern struct plat_smp_ops *mp_ops; extern struct plat_smp_ops shx3_smp_ops; #ifdef CONFIG_SMP static inline void plat_smp_setup(void) { BUG_ON(!mp_ops); mp_ops->smp_setup(); } static inline void play_dead(void) { mp_ops->play_dead(); } extern void register_smp_ops(struct plat_smp_ops *ops); #else static inline void plat_smp_setup(void) { /* UP, nothing to do ... */ } static inline void register_smp_ops(struct plat_smp_ops *ops) { } static inline void play_dead(void) { BUG(); } #endif /* CONFIG_SMP */ #endif /* __ASM_SH_SMP_OPS_H */ PK ! �w `R R include/asm/machvec.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/machvec.h * * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) */ #ifndef _ASM_SH_MACHVEC_H #define _ASM_SH_MACHVEC_H #include <linux/types.h> #include <linux/time.h> #include <generated/machtypes.h> struct sh_machine_vector { void (*mv_setup)(char **cmdline_p); const char *mv_name; int (*mv_irq_demux)(int irq); void (*mv_init_irq)(void); #ifdef CONFIG_HAS_IOPORT_MAP void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); void (*mv_ioport_unmap)(void __iomem *); #endif int (*mv_clk_init)(void); int (*mv_mode_pins)(void); void (*mv_mem_init)(void); void (*mv_mem_reserve)(void); }; extern struct sh_machine_vector sh_mv; #define get_system_type() sh_mv.mv_name #define __initmv \ __used __section(".machvec.init") #endif /* _ASM_SH_MACHVEC_H */ PK ! ��>v include/asm/module.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SH_MODULE_H #define _ASM_SH_MODULE_H #include <asm-generic/module.h> #ifdef CONFIG_DWARF_UNWINDER struct mod_arch_specific { struct list_head fde_list; struct list_head cie_list; }; #endif #endif /* _ASM_SH_MODULE_H */ PK ! 3��Wl l include/asm/sh7760fb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver. * * (c) 2006-2008 MSC Vertriebsges.m.b.H., * Manuel Lauss <mano@roarinelk.homelinux.net> * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> */ #ifndef _ASM_SH_SH7760FB_H #define _ASM_SH_SH7760FB_H /* * some bits of the colormap registers should be written as zero. * create a mask for that. */ #define SH7760FB_PALETTE_MASK 0x00f8fcf8 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */ #define SH7760FB_DMA_MASK 0x0C000000 /* palette */ #define LDPR(x) (((x) << 2)) /* framebuffer registers and bits */ #define LDICKR 0x400 #define LDMTR 0x402 /* see sh7760fb.h for LDMTR bits */ #define LDDFR 0x404 #define LDDFR_PABD (1 << 8) #define LDDFR_COLOR_MASK 0x7F #define LDSMR 0x406 #define LDSMR_ROT (1 << 13) #define LDSARU 0x408 #define LDSARL 0x40c #define LDLAOR 0x410 #define LDPALCR 0x412 #define LDPALCR_PALS (1 << 4) #define LDPALCR_PALEN (1 << 0) #define LDHCNR 0x414 #define LDHSYNR 0x416 #define LDVDLNR 0x418 #define LDVTLNR 0x41a #define LDVSYNR 0x41c #define LDACLNR 0x41e #define LDINTR 0x420 #define LDPMMR 0x424 #define LDPSPR 0x426 #define LDCNTR 0x428 #define LDCNTR_DON (1 << 0) #define LDCNTR_DON2 (1 << 4) #ifdef CONFIG_CPU_SUBTYPE_SH7763 # define LDLIRNR 0x440 /* LDINTR bit */ # define LDINTR_MINTEN (1 << 15) # define LDINTR_FINTEN (1 << 14) # define LDINTR_VSINTEN (1 << 13) # define LDINTR_VEINTEN (1 << 12) # define LDINTR_MINTS (1 << 11) # define LDINTR_FINTS (1 << 10) # define LDINTR_VSINTS (1 << 9) # define LDINTR_VEINTS (1 << 8) # define VINT_START (LDINTR_VSINTEN) # define VINT_CHECK (LDINTR_VSINTS) #else /* LDINTR bit */ # define LDINTR_VINTSEL (1 << 12) # define LDINTR_VINTE (1 << 8) # define LDINTR_VINTS (1 << 0) # define VINT_START (LDINTR_VINTSEL) # define VINT_CHECK (LDINTR_VINTS) #endif /* HSYNC polarity inversion */ #define LDMTR_FLMPOL (1 << 15) /* VSYNC polarity inversion */ #define LDMTR_CL1POL (1 << 14) /* DISPLAY-ENABLE polarity inversion */ #define LDMTR_DISPEN_LOWACT (1 << 13) /* DISPLAY DATA BUS polarity inversion */ #define LDMTR_DPOL_LOWACT (1 << 12) /* AC modulation signal enable */ #define LDMTR_MCNT (1 << 10) /* Disable output of HSYNC during VSYNC period */ #define LDMTR_CL1CNT (1 << 9) /* Disable output of VSYNC during VSYNC period */ #define LDMTR_CL2CNT (1 << 8) /* Display types supported by the LCDC */ #define LDMTR_STN_MONO_4 0x00 #define LDMTR_STN_MONO_8 0x01 #define LDMTR_STN_COLOR_4 0x08 #define LDMTR_STN_COLOR_8 0x09 #define LDMTR_STN_COLOR_12 0x0A #define LDMTR_STN_COLOR_16 0x0B #define LDMTR_DSTN_MONO_8 0x11 #define LDMTR_DSTN_MONO_16 0x13 #define LDMTR_DSTN_COLOR_8 0x19 #define LDMTR_DSTN_COLOR_12 0x1A #define LDMTR_DSTN_COLOR_16 0x1B #define LDMTR_TFT_COLOR_16 0x2B /* framebuffer color layout */ #define LDDFR_1BPP_MONO 0x00 #define LDDFR_2BPP_MONO 0x01 #define LDDFR_4BPP_MONO 0x02 #define LDDFR_6BPP_MONO 0x04 #define LDDFR_4BPP 0x0A #define LDDFR_8BPP 0x0C #define LDDFR_16BPP_RGB555 0x1D #define LDDFR_16BPP_RGB565 0x2D /* LCDC Pixclock sources */ #define LCDC_CLKSRC_BUSCLOCK 0 #define LCDC_CLKSRC_PERIPHERAL 1 #define LCDC_CLKSRC_EXTERNAL 2 #define LDICKR_CLKSRC(x) \ (((x) & 3) << 12) /* LCDC pixclock input divider. Set to 1 at a minimum! */ #define LDICKR_CLKDIV(x) \ ((x) & 0x1f) struct sh7760fb_platdata { /* Set this member to a valid fb_videmode for the display you * wish to use. The following members must be initialized: * xres, yres, hsync_len, vsync_len, sync, * {left,right,upper,lower}_margin. * The driver uses the above members to calculate register values * and memory requirements. Other members are ignored but may * be used by other framebuffer layer components. */ struct fb_videomode *def_mode; /* LDMTR includes display type and signal polarity. The * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo * data above; however the polarities of the following signals * must be encoded in the ldmtr member: * Display Enable signal (default high-active) DISPEN_LOWACT * Display Data signals (default high-active) DPOL_LOWACT * AC Modulation signal (default off) MCNT * Hsync-During-Vsync suppression (default off) CL1CNT * Vsync-during-vsync suppression (default off) CL2CNT * NOTE: also set a display type! * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16}) */ u16 ldmtr; /* LDDFR controls framebuffer image format (depth, organization) * Use ONE of the LDDFR_?BPP_* macros! */ u16 lddfr; /* LDPMMR and LDPSPR control the timing of the power signals * for the display. Please read the SH7760 Hardware Manual, * Chapters 30.3.17, 30.3.18 and 30.4.6! */ u16 ldpmmr; u16 ldpspr; /* LDACLNR contains the line numbers after which the AC modulation * signal is to toggle. Set to ZERO for TFTs or displays which * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual). */ u16 ldaclnr; /* LDICKR contains information on pixelclock source and config. * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros. * minimal value for CLKDIV() must be 1!. */ u16 ldickr; /* set this member to 1 if you wish to use the LCDC's hardware * rotation function. This is limited to displays <= 320x200 * pixels resolution! */ int rotate; /* set to 1 to rotate 90 CCW */ /* set this to 1 to suppress vsync irq use. */ int novsync; /* blanking hook for platform. Set this if your platform can do * more than the LCDC in terms of blanking (e.g. disable clock * generator / backlight power supply / etc. */ void (*blank) (int); }; #endif /* _ASM_SH_SH7760FB_H */ PK ! ��p7 7 include/asm/pgtable-2level.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PGTABLE_2LEVEL_H #define __ASM_SH_PGTABLE_2LEVEL_H #include <asm-generic/pgtable-nopmd.h> /* * traditional two-level paging structure */ #define PAGETABLE_LEVELS 2 /* PTE bits */ #define PTE_MAGNITUDE 2 /* 32-bit PTEs */ #define PTE_SHIFT PAGE_SHIFT #define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE) /* PGD bits */ #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) #define PTRS_PER_PGD (PAGE_SIZE / (1 << PTE_MAGNITUDE)) #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) #endif /* __ASM_SH_PGTABLE_2LEVEL_H */ PK ! ���� � include/asm/bitops-grb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BITOPS_GRB_H #define __ASM_SH_BITOPS_GRB_H static inline void set_bit(int nr, volatile void * addr) { int mask; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ " mov.l @%1, %0 \n\t" /* load old value */ " or %2, %0 \n\t" /* or */ " mov.l %0, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (tmp), "+r" (a) : "r" (mask) : "memory" , "r0", "r1"); } static inline void clear_bit(int nr, volatile void * addr) { int mask; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = ~(1 << (nr & 0x1f)); __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ " mov.l @%1, %0 \n\t" /* load old value */ " and %2, %0 \n\t" /* and */ " mov.l %0, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (tmp), "+r" (a) : "r" (mask) : "memory" , "r0", "r1"); } static inline void change_bit(int nr, volatile void * addr) { int mask; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ " mov.l @%1, %0 \n\t" /* load old value */ " xor %2, %0 \n\t" /* xor */ " mov.l %0, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (tmp), "+r" (a) : "r" (mask) : "memory" , "r0", "r1"); } static inline int test_and_set_bit(int nr, volatile void * addr) { int mask, retval; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-14, r15 \n\t" /* LOGIN: r15 = size */ " mov.l @%2, %0 \n\t" /* load old value */ " mov %0, %1 \n\t" " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ " mov #-1, %1 \n\t" /* retvat = -1 */ " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ " or %3, %0 \n\t" " mov.l %0, @%2 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (tmp), "=&r" (retval), "+r" (a) : "r" (mask) : "memory" , "r0", "r1" ,"t"); return retval; } static inline int test_and_clear_bit(int nr, volatile void * addr) { int mask, retval,not_mask; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); not_mask = ~mask; __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-14, r15 \n\t" /* LOGIN */ " mov.l @%2, %0 \n\t" /* load old value */ " mov %0, %1 \n\t" /* %1 = *a */ " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ " mov #-1, %1 \n\t" /* retvat = -1 */ " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ " and %4, %0 \n\t" " mov.l %0, @%2 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (tmp), "=&r" (retval), "+r" (a) : "r" (mask), "r" (not_mask) : "memory" , "r0", "r1", "t"); return retval; } static inline int test_and_change_bit(int nr, volatile void * addr) { int mask, retval; volatile unsigned int *a = addr; unsigned long tmp; a += nr >> 5; mask = 1 << (nr & 0x1f); __asm__ __volatile__ ( " .align 2 \n\t" " mova 1f, r0 \n\t" /* r0 = end point */ " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-14, r15 \n\t" /* LOGIN */ " mov.l @%2, %0 \n\t" /* load old value */ " mov %0, %1 \n\t" /* %1 = *a */ " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ " mov #-1, %1 \n\t" /* retvat = -1 */ " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ " xor %3, %0 \n\t" " mov.l %0, @%2 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (tmp), "=&r" (retval), "+r" (a) : "r" (mask) : "memory" , "r0", "r1", "t"); return retval; } #include <asm-generic/bitops/non-atomic.h> #endif /* __ASM_SH_BITOPS_GRB_H */ PK ! 3;�} } include/asm/timex.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * linux/include/asm-sh/timex.h * * sh architecture timex specifications */ #ifndef __ASM_SH_TIMEX_H #define __ASM_SH_TIMEX_H /* * Only parts using the legacy CPG code for their clock framework * implementation need to define their own Pclk value. If provided, this * can be used for accurately setting CLOCK_TICK_RATE, otherwise we * simply fall back on the i8253 PIT value. */ #ifdef CONFIG_SH_PCLK_FREQ #define CLOCK_TICK_RATE (CONFIG_SH_PCLK_FREQ / 4) /* Underlying HZ */ #else #define CLOCK_TICK_RATE 1193180 #endif #include <asm-generic/timex.h> #endif /* __ASM_SH_TIMEX_H */ PK ! o5ˏ � include/asm/uaccess_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * User space memory access functions * * Copyright (C) 1999, 2002 Niibe Yutaka * Copyright (C) 2003 - 2008 Paul Mundt * * Based on: * MIPS implementation version 1.15 by * Copyright (C) 1996, 1997, 1998 by Ralf Baechle * and i386 version. */ #ifndef __ASM_SH_UACCESS_32_H #define __ASM_SH_UACCESS_32_H #define __get_user_size(x,ptr,size,retval) \ do { \ retval = 0; \ switch (size) { \ case 1: \ __get_user_asm(x, ptr, retval, "b"); \ break; \ case 2: \ __get_user_asm(x, ptr, retval, "w"); \ break; \ case 4: \ __get_user_asm(x, ptr, retval, "l"); \ break; \ case 8: \ __get_user_u64(x, ptr, retval); \ break; \ default: \ __get_user_unknown(); \ break; \ } \ } while (0) #ifdef CONFIG_MMU #define __get_user_asm(x, addr, err, insn) \ ({ \ __asm__ __volatile__( \ "1:\n\t" \ "mov." insn " %2, %1\n\t" \ "2:\n" \ ".section .fixup,\"ax\"\n" \ "3:\n\t" \ "mov #0, %1\n\t" \ "mov.l 4f, %0\n\t" \ "jmp @%0\n\t" \ " mov %3, %0\n\t" \ ".balign 4\n" \ "4: .long 2b\n\t" \ ".previous\n" \ ".section __ex_table,\"a\"\n\t" \ ".long 1b, 3b\n\t" \ ".previous" \ :"=&r" (err), "=&r" (x) \ :"m" (__m(addr)), "i" (-EFAULT), "0" (err)); }) #else #define __get_user_asm(x, addr, err, insn) \ do { \ __asm__ __volatile__ ( \ "mov." insn " %1, %0\n\t" \ : "=&r" (x) \ : "m" (__m(addr)) \ ); \ } while (0) #endif /* CONFIG_MMU */ extern void __get_user_unknown(void); #if defined(CONFIG_CPU_LITTLE_ENDIAN) #define __get_user_u64(x, addr, err) \ ({ \ __asm__ __volatile__( \ "1:\n\t" \ "mov.l %2,%R1\n\t" \ "mov.l %T2,%S1\n\t" \ "2:\n" \ ".section .fixup,\"ax\"\n" \ "3:\n\t" \ "mov #0,%R1\n\t" \ "mov #0,%S1\n\t" \ "mov.l 4f, %0\n\t" \ "jmp @%0\n\t" \ " mov %3, %0\n\t" \ ".balign 4\n" \ "4: .long 2b\n\t" \ ".previous\n" \ ".section __ex_table,\"a\"\n\t" \ ".long 1b, 3b\n\t" \ ".long 1b + 2, 3b\n\t" \ ".previous" \ :"=&r" (err), "=&r" (x) \ :"m" (__m(addr)), "i" (-EFAULT), "0" (err)); }) #else #define __get_user_u64(x, addr, err) \ ({ \ __asm__ __volatile__( \ "1:\n\t" \ "mov.l %2,%S1\n\t" \ "mov.l %T2,%R1\n\t" \ "2:\n" \ ".section .fixup,\"ax\"\n" \ "3:\n\t" \ "mov #0,%S1\n\t" \ "mov #0,%R1\n\t" \ "mov.l 4f, %0\n\t" \ "jmp @%0\n\t" \ " mov %3, %0\n\t" \ ".balign 4\n" \ "4: .long 2b\n\t" \ ".previous\n" \ ".section __ex_table,\"a\"\n\t" \ ".long 1b, 3b\n\t" \ ".long 1b + 2, 3b\n\t" \ ".previous" \ :"=&r" (err), "=&r" (x) \ :"m" (__m(addr)), "i" (-EFAULT), "0" (err)); }) #endif #define __put_user_size(x,ptr,size,retval) \ do { \ retval = 0; \ switch (size) { \ case 1: \ __put_user_asm(x, ptr, retval, "b"); \ break; \ case 2: \ __put_user_asm(x, ptr, retval, "w"); \ break; \ case 4: \ __put_user_asm(x, ptr, retval, "l"); \ break; \ case 8: \ __put_user_u64(x, ptr, retval); \ break; \ default: \ __put_user_unknown(); \ } \ } while (0) #ifdef CONFIG_MMU #define __put_user_asm(x, addr, err, insn) \ do { \ __asm__ __volatile__ ( \ "1:\n\t" \ "mov." insn " %1, %2\n\t" \ "2:\n" \ ".section .fixup,\"ax\"\n" \ "3:\n\t" \ "mov.l 4f, %0\n\t" \ "jmp @%0\n\t" \ " mov %3, %0\n\t" \ ".balign 4\n" \ "4: .long 2b\n\t" \ ".previous\n" \ ".section __ex_table,\"a\"\n\t" \ ".long 1b, 3b\n\t" \ ".previous" \ : "=&r" (err) \ : "r" (x), "m" (__m(addr)), "i" (-EFAULT), \ "0" (err) \ : "memory" \ ); \ } while (0) #else #define __put_user_asm(x, addr, err, insn) \ do { \ __asm__ __volatile__ ( \ "mov." insn " %0, %1\n\t" \ : /* no outputs */ \ : "r" (x), "m" (__m(addr)) \ : "memory" \ ); \ } while (0) #endif /* CONFIG_MMU */ #if defined(CONFIG_CPU_LITTLE_ENDIAN) #define __put_user_u64(val,addr,retval) \ ({ \ __asm__ __volatile__( \ "1:\n\t" \ "mov.l %R1,%2\n\t" \ "mov.l %S1,%T2\n\t" \ "2:\n" \ ".section .fixup,\"ax\"\n" \ "3:\n\t" \ "mov.l 4f,%0\n\t" \ "jmp @%0\n\t" \ " mov %3,%0\n\t" \ ".balign 4\n" \ "4: .long 2b\n\t" \ ".previous\n" \ ".section __ex_table,\"a\"\n\t" \ ".long 1b, 3b\n\t" \ ".previous" \ : "=r" (retval) \ : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \ : "memory"); }) #else #define __put_user_u64(val,addr,retval) \ ({ \ __asm__ __volatile__( \ "1:\n\t" \ "mov.l %S1,%2\n\t" \ "mov.l %R1,%T2\n\t" \ "2:\n" \ ".section .fixup,\"ax\"\n" \ "3:\n\t" \ "mov.l 4f,%0\n\t" \ "jmp @%0\n\t" \ " mov %3,%0\n\t" \ ".balign 4\n" \ "4: .long 2b\n\t" \ ".previous\n" \ ".section __ex_table,\"a\"\n\t" \ ".long 1b, 3b\n\t" \ ".previous" \ : "=r" (retval) \ : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \ : "memory"); }) #endif extern void __put_user_unknown(void); #endif /* __ASM_SH_UACCESS_32_H */ PK ! 6P�> > include/asm/pgtable_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PGTABLE_32_H #define __ASM_SH_PGTABLE_32_H /* * Linux PTEL encoding. * * Hardware and software bit definitions for the PTEL value (see below for * notes on SH-X2 MMUs and 64-bit PTEs): * * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4). * * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set, * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT). * * In order to keep this relatively clean, do not use these for defining * SH-3 specific flags until all of the other unused bits have been * exhausted. * * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE. * * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages. * Bit 10 is used for _PAGE_ACCESSED, and bit 11 is used for _PAGE_SPECIAL. * * - On 29 bit platforms, bits 31 to 29 are used for the space attributes * and timing control which (together with bit 0) are moved into the * old-style PTEA on the parts that support it. * * SH-X2 MMUs and extended PTEs * * SH-X2 supports an extended mode TLB with split data arrays due to the * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and * SZ bit placeholders still exist in data array 1, but are implemented as * reserved bits, with the real logic existing in data array 2. * * The downside to this is that we can no longer fit everything in to a 32-bit * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus * side, this gives us quite a few spare bits to play with for future usage. */ /* Legacy and compat mode bits */ #define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */ #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */ #define _PAGE_DIRTY 0x004 /* D-bit : page changed */ #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */ #define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ #define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ #define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/ #define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */ #define _PAGE_PROTNONE 0x200 /* software: if not present */ #define _PAGE_ACCESSED 0x400 /* software: page referenced */ #define _PAGE_SPECIAL 0x800 /* software: special page */ #define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1) #define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER) /* Extended mode bits */ #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */ #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */ #define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */ #define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */ #define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */ #define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */ #define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */ #define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */ #define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */ #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */ #define _PAGE_EXT_WIRED 0x4000 /* software: Wire TLB entry */ /* Wrapper for extended mode pgprot twiddling */ #define _PAGE_EXT(x) ((unsigned long long)(x) << 32) #ifdef CONFIG_X2TLB #define _PAGE_PCC_MASK 0x00000000 /* No legacy PTEA support */ #else /* software: moves to PTEA.TC (Timing Control) */ #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */ #define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */ /* software: moves to PTEA.SA[2:0] (Space Attributes) */ #define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */ #define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */ #define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */ #define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */ #define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */ #define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */ #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */ #define _PAGE_PCC_MASK 0xe0000001 /* copy the ptea attributes */ static inline unsigned long copy_ptea_attributes(unsigned long x) { return ((x >> 28) & 0xe) | (x & 0x1); } #endif /* Mask which drops unused bits from the PTEL value */ #if defined(CONFIG_CPU_SH3) #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \ _PAGE_SZ1 | _PAGE_HW_SHARED) #elif defined(CONFIG_X2TLB) /* Get rid of the legacy PR/SZ bits when using extended mode */ #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \ _PAGE_PR_MASK | _PAGE_SZ_MASK) #else #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED) #endif #define _PAGE_FLAGS_HARDWARE_MASK (phys_addr_mask() & ~(_PAGE_CLEAR_FLAGS)) /* Hardware flags, page size encoding */ #if !defined(CONFIG_MMU) # define _PAGE_FLAGS_HARD 0ULL #elif defined(CONFIG_X2TLB) # if defined(CONFIG_PAGE_SIZE_4KB) # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0) # elif defined(CONFIG_PAGE_SIZE_8KB) # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1) # elif defined(CONFIG_PAGE_SIZE_64KB) # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2) # endif #else # if defined(CONFIG_PAGE_SIZE_4KB) # define _PAGE_FLAGS_HARD _PAGE_SZ0 # elif defined(CONFIG_PAGE_SIZE_64KB) # define _PAGE_FLAGS_HARD _PAGE_SZ1 # endif #endif #if defined(CONFIG_X2TLB) # if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) # define _PAGE_SZHUGE (_PAGE_EXT_ESZ2) # elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K) # define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2) # elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) # define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2) # elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) # define _PAGE_SZHUGE (_PAGE_EXT_ESZ3) # elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB) # define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3) # endif # define _PAGE_WIRED (_PAGE_EXT(_PAGE_EXT_WIRED)) #else # if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) # define _PAGE_SZHUGE (_PAGE_SZ1) # elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) # define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1) # endif # define _PAGE_WIRED (0) #endif /* * Stub out _PAGE_SZHUGE if we don't have a good definition for it, * to make pte_mkhuge() happy. */ #ifndef _PAGE_SZHUGE # define _PAGE_SZHUGE (_PAGE_FLAGS_HARD) #endif /* * Mask of bits that are to be preserved across pgprot changes. */ #define _PAGE_CHG_MASK \ (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | \ _PAGE_DIRTY | _PAGE_SPECIAL) #ifndef __ASSEMBLY__ #if defined(CONFIG_X2TLB) /* SH-X2 TLB */ #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \ _PAGE_ACCESSED | _PAGE_FLAGS_HARD) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_READ | \ _PAGE_EXT_KERN_WRITE | \ _PAGE_EXT_USER_READ | \ _PAGE_EXT_USER_WRITE)) #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \ _PAGE_EXT_KERN_READ | \ _PAGE_EXT_USER_EXEC | \ _PAGE_EXT_USER_READ)) #define PAGE_COPY PAGE_EXECREAD #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_READ | \ _PAGE_EXT_USER_READ)) #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \ _PAGE_EXT_USER_WRITE)) #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \ _PAGE_EXT_KERN_READ | \ _PAGE_EXT_KERN_EXEC | \ _PAGE_EXT_USER_WRITE | \ _PAGE_EXT_USER_READ | \ _PAGE_EXT_USER_EXEC)) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \ _PAGE_DIRTY | _PAGE_ACCESSED | \ _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_READ | \ _PAGE_EXT_KERN_WRITE | \ _PAGE_EXT_KERN_EXEC)) #define PAGE_KERNEL_NOCACHE \ __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \ _PAGE_ACCESSED | _PAGE_HW_SHARED | \ _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_READ | \ _PAGE_EXT_KERN_WRITE | \ _PAGE_EXT_KERN_EXEC)) #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \ _PAGE_DIRTY | _PAGE_ACCESSED | \ _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \ _PAGE_EXT(_PAGE_EXT_KERN_READ | \ _PAGE_EXT_KERN_EXEC)) #define PAGE_KERNEL_PCC(slot, type) \ __pgprot(0) #elif defined(CONFIG_MMU) /* SH-X TLB */ #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \ _PAGE_ACCESSED | _PAGE_FLAGS_HARD) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \ _PAGE_CACHABLE | _PAGE_ACCESSED | \ _PAGE_FLAGS_HARD) #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \ _PAGE_ACCESSED | _PAGE_FLAGS_HARD) #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \ _PAGE_ACCESSED | _PAGE_FLAGS_HARD) #define PAGE_EXECREAD PAGE_READONLY #define PAGE_RWX PAGE_SHARED #define PAGE_WRITEONLY PAGE_SHARED #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \ _PAGE_DIRTY | _PAGE_ACCESSED | \ _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) #define PAGE_KERNEL_NOCACHE \ __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \ _PAGE_ACCESSED | _PAGE_HW_SHARED | \ _PAGE_FLAGS_HARD) #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \ _PAGE_DIRTY | _PAGE_ACCESSED | \ _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) #define PAGE_KERNEL_PCC(slot, type) \ __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \ _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \ (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \ (type)) #else /* no mmu */ #define PAGE_NONE __pgprot(0) #define PAGE_SHARED __pgprot(0) #define PAGE_COPY __pgprot(0) #define PAGE_EXECREAD __pgprot(0) #define PAGE_RWX __pgprot(0) #define PAGE_READONLY __pgprot(0) #define PAGE_WRITEONLY __pgprot(0) #define PAGE_KERNEL __pgprot(0) #define PAGE_KERNEL_NOCACHE __pgprot(0) #define PAGE_KERNEL_RO __pgprot(0) #define PAGE_KERNEL_PCC(slot, type) \ __pgprot(0) #endif #endif /* __ASSEMBLY__ */ #ifndef __ASSEMBLY__ /* * Certain architectures need to do special things when PTEs * within a page table are directly modified. Thus, the following * hook is made available. */ #ifdef CONFIG_X2TLB static inline void set_pte(pte_t *ptep, pte_t pte) { ptep->pte_high = pte.pte_high; smp_wmb(); ptep->pte_low = pte.pte_low; } #else #define set_pte(pteptr, pteval) (*(pteptr) = pteval) #endif #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) /* * (pmds are folded into pgds so this doesn't get actually called, * but the define is needed for a generic inline function.) */ #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) #define pfn_pte(pfn, prot) \ __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) #define pfn_pmd(pfn, prot) \ __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) #define pte_none(x) (!pte_val(x)) #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE)) #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) #define pmd_none(x) (!pmd_val(x)) #define pmd_present(x) (pmd_val(x)) #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) #define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK) #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) #define pte_page(x) pfn_to_page(pte_pfn(x)) /* * The following only work if pte_present() is true. * Undefined behaviour if not.. */ #define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT)) #define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY) #define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED) #define pte_special(pte) ((pte).pte_low & _PAGE_SPECIAL) #ifdef CONFIG_X2TLB #define pte_write(pte) \ ((pte).pte_high & (_PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE)) #else #define pte_write(pte) ((pte).pte_low & _PAGE_RW) #endif #define PTE_BIT_FUNC(h,fn,op) \ static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; } #ifdef CONFIG_X2TLB /* * We cheat a bit in the SH-X2 TLB case. As the permission bits are * individually toggled (and user permissions are entirely decoupled from * kernel permissions), we attempt to couple them a bit more sanely here. */ PTE_BIT_FUNC(high, wrprotect, &= ~(_PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE)); PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE); PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE); #else PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW); PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW); PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE); #endif PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY); PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY); PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED); PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED); PTE_BIT_FUNC(low, mkspecial, |= _PAGE_SPECIAL); /* * Macro and implementation to make a page protection as uncachable. */ #define pgprot_writecombine(prot) \ __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE) #define pgprot_noncached pgprot_writecombine /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. * * extern pte_t mk_pte(struct page *page, pgprot_t pgprot) */ #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { pte.pte_low &= _PAGE_CHG_MASK; pte.pte_low |= pgprot_val(newprot); #ifdef CONFIG_X2TLB pte.pte_high |= pgprot_val(newprot) >> 32; #endif return pte; } static inline unsigned long pmd_page_vaddr(pmd_t pmd) { return (unsigned long)pmd_val(pmd); } #define pmd_page(pmd) (virt_to_page(pmd_val(pmd))) #ifdef CONFIG_X2TLB #define pte_ERROR(e) \ printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \ &(e), (e).pte_high, (e).pte_low) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) #else #define pte_ERROR(e) \ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) #endif /* * Encode and de-code a swap entry * * Constraints: * _PAGE_PRESENT at bit 8 * _PAGE_PROTNONE at bit 9 * * For the normal case, we encode the swap type into bits 0:7 and the * swap offset into bits 10:30. For the 64-bit PTE case, we keep the * preserved bits in the low 32-bits and use the upper 32 as the swap * offset (along with a 5-bit type), following the same approach as x86 * PAE. This keeps the logic quite simple. * * As is evident by the Alpha code, if we ever get a 64-bit unsigned * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes * much cleaner.. * * NOTE: We should set ZEROs at the position of _PAGE_PRESENT * and _PAGE_PROTNONE bits */ #ifdef CONFIG_X2TLB #define __swp_type(x) ((x).val & 0x1f) #define __swp_offset(x) ((x).val >> 5) #define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5}) #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high }) #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val }) #else #define __swp_type(x) ((x).val & 0xff) #define __swp_offset(x) ((x).val >> 10) #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10}) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 }) #endif #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_PGTABLE_32_H */ PK ! 0 q � include/asm/topology.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SH_TOPOLOGY_H #define _ASM_SH_TOPOLOGY_H #ifdef CONFIG_NUMA #define cpu_to_node(cpu) ((void)(cpu),0) #define cpumask_of_node(node) ((void)node, cpu_online_mask) #define pcibus_to_node(bus) ((void)(bus), -1) #define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \ cpu_all_mask : \ cpumask_of_node(pcibus_to_node(bus))) #endif #define mc_capable() (1) const struct cpumask *cpu_coregroup_mask(int cpu); extern cpumask_t cpu_core_map[NR_CPUS]; #define topology_core_cpumask(cpu) (&cpu_core_map[cpu]) #include <asm-generic/topology.h> #endif /* _ASM_SH_TOPOLOGY_H */ PK ! ���� � include/asm/sh_bios.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BIOS_H #define __ASM_SH_BIOS_H #ifdef CONFIG_SH_STANDARD_BIOS /* * Copyright (C) 2000 Greg Banks, Mitch Davis * C API to interface to the standard LinuxSH BIOS * usually from within the early stages of kernel boot. */ extern void sh_bios_console_write(const char *buf, unsigned int len); extern void sh_bios_gdb_detach(void); extern void sh_bios_get_node_addr(unsigned char *node_addr); extern void sh_bios_shutdown(unsigned int how); extern void sh_bios_vbr_init(void); extern void sh_bios_vbr_reload(void); #else static inline void sh_bios_vbr_init(void) { } static inline void sh_bios_vbr_reload(void) { } #endif /* CONFIG_SH_STANDARD_BIOS */ #endif /* __ASM_SH_BIOS_H */ PK ! �+ �u u include/asm/bitops.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BITOPS_H #define __ASM_SH_BITOPS_H #ifndef _LINUX_BITOPS_H #error only <linux/bitops.h> can be included directly #endif /* For __swab32 */ #include <asm/byteorder.h> #include <asm/barrier.h> #ifdef CONFIG_GUSA_RB #include <asm/bitops-grb.h> #elif defined(CONFIG_CPU_SH2A) #include <asm-generic/bitops/atomic.h> #include <asm/bitops-op32.h> #elif defined(CONFIG_CPU_SH4A) #include <asm/bitops-llsc.h> #elif defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) #include <asm/bitops-cas.h> #else #include <asm-generic/bitops/atomic.h> #include <asm-generic/bitops/non-atomic.h> #endif static inline unsigned long ffz(unsigned long word) { unsigned long result; __asm__("1:\n\t" "shlr %1\n\t" "bt/s 1b\n\t" " add #1, %0" : "=r" (result), "=r" (word) : "0" (~0L), "1" (word) : "t"); return result; } /** * __ffs - find first bit in word. * @word: The word to search * * Undefined if no bit exists, so code should check against 0 first. */ static inline unsigned long __ffs(unsigned long word) { unsigned long result; __asm__("1:\n\t" "shlr %1\n\t" "bf/s 1b\n\t" " add #1, %0" : "=r" (result), "=r" (word) : "0" (~0L), "1" (word) : "t"); return result; } #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/lock.h> #include <asm-generic/bitops/sched.h> #include <asm-generic/bitops/ext2-atomic.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/fls64.h> #include <asm-generic/bitops/le.h> #include <asm-generic/bitops/find.h> #endif /* __ASM_SH_BITOPS_H */ PK ! �sj j include/asm/irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_IRQ_H #define __ASM_SH_IRQ_H #include <linux/cpumask.h> #include <asm/machvec.h> /* * Only legacy non-sparseirq platforms have to set a reasonably sane * value here. sparseirq platforms allocate their irq_descs on the fly, * so will expand automatically based on the number of registered IRQs. */ #ifdef CONFIG_SPARSE_IRQ # define NR_IRQS 8 #else # define NR_IRQS 512 #endif /* * This is a special IRQ number for indicating that no IRQ has been * triggered and to simply ignore the IRQ dispatch. This is a special * case that can happen with IRQ auto-distribution when multiple CPUs * are woken up and signalled in parallel. */ #define NO_IRQ_IGNORE ((unsigned int)-1) /* * Simple Mask Register Support */ extern void make_maskreg_irq(unsigned int irq); extern unsigned short *irq_mask_register; /* * PINT IRQs */ void init_IRQ_pint(void); void make_imask_irq(unsigned int irq); static inline int generic_irq_demux(int irq) { return irq; } #define irq_demux(irq) sh_mv.mv_irq_demux(irq) void init_IRQ(void); void migrate_irqs(void); asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs); #ifdef CONFIG_IRQSTACKS extern void irq_ctx_init(int cpu); extern void irq_ctx_exit(int cpu); #else # define irq_ctx_init(cpu) do { } while (0) # define irq_ctx_exit(cpu) do { } while (0) #endif #ifdef CONFIG_INTC_BALANCING extern unsigned int irq_lookup(unsigned int irq); extern void irq_finish(unsigned int irq); #else #define irq_lookup(irq) (irq) #define irq_finish(irq) do { } while (0) #endif #include <asm-generic/irq.h> #endif /* __ASM_SH_IRQ_H */ PK ! �p��S S include/asm/pgalloc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_PGALLOC_H #define __ASM_SH_PGALLOC_H #include <asm/page.h> #define __HAVE_ARCH_PMD_ALLOC_ONE #define __HAVE_ARCH_PMD_FREE #define __HAVE_ARCH_PGD_FREE #include <asm-generic/pgalloc.h> extern pgd_t *pgd_alloc(struct mm_struct *); extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); #if PAGETABLE_LEVELS > 2 extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd); extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address); extern void pmd_free(struct mm_struct *mm, pmd_t *pmd); #define __pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, (pmdp)) #endif static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) { set_pmd(pmd, __pmd((unsigned long)pte)); } static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte) { set_pmd(pmd, __pmd((unsigned long)page_address(pte))); } #define __pte_free_tlb(tlb,pte,addr) \ do { \ pgtable_pte_page_dtor(pte); \ tlb_remove_page((tlb), (pte)); \ } while (0) #endif /* __ASM_SH_PGALLOC_H */ PK ! �.ce include/asm/dmabrg.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * SH7760 DMABRG (USB/Audio) support */ #ifndef _DMABRG_H_ #define _DMABRG_H_ /* IRQ sources */ #define DMABRGIRQ_USBDMA 0 #define DMABRGIRQ_USBDMAERR 1 #define DMABRGIRQ_A0TXF 2 #define DMABRGIRQ_A0TXH 3 #define DMABRGIRQ_A0RXF 4 #define DMABRGIRQ_A0RXH 5 #define DMABRGIRQ_A1TXF 6 #define DMABRGIRQ_A1TXH 7 #define DMABRGIRQ_A1RXF 8 #define DMABRGIRQ_A1RXH 9 extern int dmabrg_request_irq(unsigned int, void(*)(void *), void *); extern void dmabrg_free_irq(unsigned int); #endif PK ! ��u u include/asm/atomic-grb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_ATOMIC_GRB_H #define __ASM_SH_ATOMIC_GRB_H #define ATOMIC_OP(op) \ static inline void arch_atomic_##op(int i, atomic_t *v) \ { \ int tmp; \ \ __asm__ __volatile__ ( \ " .align 2 \n\t" \ " mova 1f, r0 \n\t" /* r0 = end point */ \ " mov r15, r1 \n\t" /* r1 = saved sp */ \ " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ \ " mov.l @%1, %0 \n\t" /* load old value */ \ " " #op " %2, %0 \n\t" /* $op */ \ " mov.l %0, @%1 \n\t" /* store new value */ \ "1: mov r1, r15 \n\t" /* LOGOUT */ \ : "=&r" (tmp), \ "+r" (v) \ : "r" (i) \ : "memory" , "r0", "r1"); \ } \ #define ATOMIC_OP_RETURN(op) \ static inline int arch_atomic_##op##_return(int i, atomic_t *v) \ { \ int tmp; \ \ __asm__ __volatile__ ( \ " .align 2 \n\t" \ " mova 1f, r0 \n\t" /* r0 = end point */ \ " mov r15, r1 \n\t" /* r1 = saved sp */ \ " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ \ " mov.l @%1, %0 \n\t" /* load old value */ \ " " #op " %2, %0 \n\t" /* $op */ \ " mov.l %0, @%1 \n\t" /* store new value */ \ "1: mov r1, r15 \n\t" /* LOGOUT */ \ : "=&r" (tmp), \ "+r" (v) \ : "r" (i) \ : "memory" , "r0", "r1"); \ \ return tmp; \ } #define ATOMIC_FETCH_OP(op) \ static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \ { \ int res, tmp; \ \ __asm__ __volatile__ ( \ " .align 2 \n\t" \ " mova 1f, r0 \n\t" /* r0 = end point */ \ " mov r15, r1 \n\t" /* r1 = saved sp */ \ " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ \ " mov.l @%2, %0 \n\t" /* load old value */ \ " mov %0, %1 \n\t" /* save old value */ \ " " #op " %3, %0 \n\t" /* $op */ \ " mov.l %0, @%2 \n\t" /* store new value */ \ "1: mov r1, r15 \n\t" /* LOGOUT */ \ : "=&r" (tmp), "=&r" (res), "+r" (v) \ : "r" (i) \ : "memory" , "r0", "r1"); \ \ return res; \ } #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op) ATOMIC_OPS(add) ATOMIC_OPS(sub) #undef ATOMIC_OPS #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OPS(and) ATOMIC_OPS(or) ATOMIC_OPS(xor) #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN #undef ATOMIC_OP #endif /* __ASM_SH_ATOMIC_GRB_H */ PK ! ��L�h h include/asm/addrspace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 1999 by Kaz Kojima * * Defitions for the address spaces of the SH CPUs. */ #ifndef __ASM_SH_ADDRSPACE_H #define __ASM_SH_ADDRSPACE_H #include <cpu/addrspace.h> /* If this CPU supports segmentation, hook up the helpers */ #ifdef P1SEG /* [ P0/U0 (virtual) ] 0x00000000 <------ User space [ P1 (fixed) cached ] 0x80000000 <------ Kernel space [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area [ P4 control ] 0xE0000000 */ /* Returns the privileged segment base of a given address */ #define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) #ifdef CONFIG_29BIT /* * Map an address to a certain privileged segment */ #define P1SEGADDR(a) \ ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) #define P2SEGADDR(a) \ ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) #define P3SEGADDR(a) \ ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) #define P4SEGADDR(a) \ ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) #else /* * These will never work in 32-bit, don't even bother. */ #define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; }) #define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; }) #define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; }) #define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; }) #endif #endif /* P1SEG */ /* Check if an address can be reached in 29 bits */ #define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000) #ifdef CONFIG_SH_STORE_QUEUES /* * This is a special case for the SH-4 store queues, as pages for this * space still need to be faulted in before it's possible to flush the * store queue cache for writeout to the remapped region. */ #define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000) #else #define P3_ADDR_MAX P4SEG #endif #endif /* __ASM_SH_ADDRSPACE_H */ PK ! 1��� � include/asm/bitops-cas.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_BITOPS_CAS_H #define __ASM_SH_BITOPS_CAS_H static inline unsigned __bo_cas(volatile unsigned *p, unsigned old, unsigned new) { __asm__ __volatile__("cas.l %1,%0,@r0" : "+r"(new) : "r"(old), "z"(p) : "t", "memory" ); return new; } static inline void set_bit(int nr, volatile void *addr) { unsigned mask, old; volatile unsigned *a = addr; a += nr >> 5; mask = 1U << (nr & 0x1f); do old = *a; while (__bo_cas(a, old, old|mask) != old); } static inline void clear_bit(int nr, volatile void *addr) { unsigned mask, old; volatile unsigned *a = addr; a += nr >> 5; mask = 1U << (nr & 0x1f); do old = *a; while (__bo_cas(a, old, old&~mask) != old); } static inline void change_bit(int nr, volatile void *addr) { unsigned mask, old; volatile unsigned *a = addr; a += nr >> 5; mask = 1U << (nr & 0x1f); do old = *a; while (__bo_cas(a, old, old^mask) != old); } static inline int test_and_set_bit(int nr, volatile void *addr) { unsigned mask, old; volatile unsigned *a = addr; a += nr >> 5; mask = 1U << (nr & 0x1f); do old = *a; while (__bo_cas(a, old, old|mask) != old); return !!(old & mask); } static inline int test_and_clear_bit(int nr, volatile void *addr) { unsigned mask, old; volatile unsigned *a = addr; a += nr >> 5; mask = 1U << (nr & 0x1f); do old = *a; while (__bo_cas(a, old, old&~mask) != old); return !!(old & mask); } static inline int test_and_change_bit(int nr, volatile void *addr) { unsigned mask, old; volatile unsigned *a = addr; a += nr >> 5; mask = 1U << (nr & 0x1f); do old = *a; while (__bo_cas(a, old, old^mask) != old); return !!(old & mask); } #include <asm-generic/bitops/non-atomic.h> #endif /* __ASM_SH_BITOPS_CAS_H */ PK ! �fb�� � include/asm/spinlock_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SPINLOCK_TYPES_H #define __ASM_SH_SPINLOCK_TYPES_H #ifndef __LINUX_SPINLOCK_TYPES_H # error "please don't include this file directly" #endif typedef struct { volatile unsigned int lock; } arch_spinlock_t; #define __ARCH_SPIN_LOCK_UNLOCKED { 1 } typedef struct { volatile unsigned int lock; } arch_rwlock_t; #define RW_LOCK_BIAS 0x01000000 #define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } #endif PK ! lB B include/asm/string.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <asm/string_32.h> PK ! l��~� � include/asm/watchdog.hnu �[��� /* SPDX-License-Identifier: GPL-2.0+ * * include/asm-sh/watchdog.h * * Copyright (C) 2002, 2003 Paul Mundt * Copyright (C) 2009 Siemens AG * Copyright (C) 2009 Valentin Sitdikov */ #ifndef __ASM_SH_WATCHDOG_H #define __ASM_SH_WATCHDOG_H #include <linux/types.h> #include <linux/io.h> #define WTCNT_HIGH 0x5a #define WTCSR_HIGH 0xa5 #define WTCSR_CKS2 0x04 #define WTCSR_CKS1 0x02 #define WTCSR_CKS0 0x01 #include <cpu/watchdog.h> /* * See cpu-sh2/watchdog.h for explanation of this stupidity.. */ #ifndef WTCNT_R # define WTCNT_R WTCNT #endif #ifndef WTCSR_R # define WTCSR_R WTCSR #endif /* * CKS0-2 supports a number of clock division ratios. At the time the watchdog * is enabled, it defaults to a 41 usec overflow period .. we overload this to * something a little more reasonable, and really can't deal with anything * lower than WTCSR_CKS_1024, else we drop back into the usec range. * * Clock Division Ratio Overflow Period * -------------------------------------------- * 1/32 (initial value) 41 usecs * 1/64 82 usecs * 1/128 164 usecs * 1/256 328 usecs * 1/512 656 usecs * 1/1024 1.31 msecs * 1/2048 2.62 msecs * 1/4096 5.25 msecs */ #define WTCSR_CKS_32 0x00 #define WTCSR_CKS_64 0x01 #define WTCSR_CKS_128 0x02 #define WTCSR_CKS_256 0x03 #define WTCSR_CKS_512 0x04 #define WTCSR_CKS_1024 0x05 #define WTCSR_CKS_2048 0x06 #define WTCSR_CKS_4096 0x07 #if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780) /** * sh_wdt_read_cnt - Read from Counter * Reads back the WTCNT value. */ static inline __u32 sh_wdt_read_cnt(void) { return __raw_readl(WTCNT_R); } /** * sh_wdt_write_cnt - Write to Counter * @val: Value to write * * Writes the given value @val to the lower byte of the timer counter. * The upper byte is set manually on each write. */ static inline void sh_wdt_write_cnt(__u32 val) { __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT); } /** * sh_wdt_write_bst - Write to Counter * @val: Value to write * * Writes the given value @val to the lower byte of the timer counter. * The upper byte is set manually on each write. */ static inline void sh_wdt_write_bst(__u32 val) { __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST); } /** * sh_wdt_read_csr - Read from Control/Status Register * * Reads back the WTCSR value. */ static inline __u32 sh_wdt_read_csr(void) { return __raw_readl(WTCSR_R); } /** * sh_wdt_write_csr - Write to Control/Status Register * @val: Value to write * * Writes the given value @val to the lower byte of the control/status * register. The upper byte is set manually on each write. */ static inline void sh_wdt_write_csr(__u32 val) { __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR); } #else /** * sh_wdt_read_cnt - Read from Counter * Reads back the WTCNT value. */ static inline __u8 sh_wdt_read_cnt(void) { return __raw_readb(WTCNT_R); } /** * sh_wdt_write_cnt - Write to Counter * @val: Value to write * * Writes the given value @val to the lower byte of the timer counter. * The upper byte is set manually on each write. */ static inline void sh_wdt_write_cnt(__u8 val) { __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT); } /** * sh_wdt_read_csr - Read from Control/Status Register * * Reads back the WTCSR value. */ static inline __u8 sh_wdt_read_csr(void) { return __raw_readb(WTCSR_R); } /** * sh_wdt_write_csr - Write to Control/Status Register * @val: Value to write * * Writes the given value @val to the lower byte of the control/status * register. The upper byte is set manually on each write. */ static inline void sh_wdt_write_csr(__u8 val) { __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR); } #endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */ #endif /* __ASM_SH_WATCHDOG_H */ PK ! ��С� � include/asm/hugetlb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SH_HUGETLB_H #define _ASM_SH_HUGETLB_H #include <asm/cacheflush.h> #include <asm/page.h> /* * If the arch doesn't supply something else, assume that hugepage * size aligned regions are ok without further preparation. */ #define __HAVE_ARCH_PREPARE_HUGEPAGE_RANGE static inline int prepare_hugepage_range(struct file *file, unsigned long addr, unsigned long len) { if (len & ~HPAGE_MASK) return -EINVAL; if (addr & ~HPAGE_MASK) return -EINVAL; return 0; } #define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) { } static inline void arch_clear_hugepage_flags(struct page *page) { clear_bit(PG_dcache_clean, &page->flags); } #define arch_clear_hugepage_flags arch_clear_hugepage_flags #include <asm-generic/hugetlb.h> #endif /* _ASM_SH_HUGETLB_H */ PK ! �`�} } include/asm/syscall_32.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SYSCALL_32_H #define __ASM_SH_SYSCALL_32_H #include <uapi/linux/audit.h> #include <linux/kernel.h> #include <linux/sched.h> #include <linux/err.h> #include <asm/ptrace.h> /* The system call number is given by the user in R3 */ static inline long syscall_get_nr(struct task_struct *task, struct pt_regs *regs) { return (regs->tra >= 0) ? regs->regs[3] : -1L; } static inline void syscall_rollback(struct task_struct *task, struct pt_regs *regs) { /* * XXX: This needs some thought. On SH we don't * save away the original r0 value anywhere. */ } static inline long syscall_get_error(struct task_struct *task, struct pt_regs *regs) { return IS_ERR_VALUE(regs->regs[0]) ? regs->regs[0] : 0; } static inline long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) { return regs->regs[0]; } static inline void syscall_set_return_value(struct task_struct *task, struct pt_regs *regs, int error, long val) { regs->regs[0] = (long) error ?: val; } static inline void syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, unsigned long *args) { /* Argument pattern is: R4, R5, R6, R7, R0, R1 */ args[5] = regs->regs[1]; args[4] = regs->regs[0]; args[3] = regs->regs[7]; args[2] = regs->regs[6]; args[1] = regs->regs[5]; args[0] = regs->regs[4]; } static inline void syscall_set_arguments(struct task_struct *task, struct pt_regs *regs, const unsigned long *args) { regs->regs[1] = args[5]; regs->regs[0] = args[4]; regs->regs[7] = args[3]; regs->regs[6] = args[2]; regs->regs[5] = args[1]; regs->regs[4] = args[0]; } static inline int syscall_get_arch(struct task_struct *task) { int arch = AUDIT_ARCH_SH; #ifdef CONFIG_CPU_LITTLE_ENDIAN arch |= __AUDIT_ARCH_LE; #endif return arch; } #endif /* __ASM_SH_SYSCALL_32_H */ PK ! ��F� � include/asm/device.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Arch specific extensions to struct device */ #ifndef __ASM_SH_DEVICE_H #define __ASM_SH_DEVICE_H #include <asm-generic/device.h> struct platform_device; /* allocate contiguous memory chunk and fill in struct resource */ int platform_resource_setup_memory(struct platform_device *pdev, char *name, unsigned long memsize); void plat_early_device_setup(void); #endif /* __ASM_SH_DEVICE_H */ PK ! \@��= = include/asm/cmpxchg-llsc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_CMPXCHG_LLSC_H #define __ASM_SH_CMPXCHG_LLSC_H static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) { unsigned long retval; unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! xchg_u32 \n\t" "mov %0, %1 \n\t" "mov %3, %0 \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "synco \n\t" : "=&z"(tmp), "=&r" (retval) : "r" (m), "r" (val) : "t", "memory" ); return retval; } static inline unsigned long __cmpxchg_u32(volatile u32 *m, unsigned long old, unsigned long new) { unsigned long retval; unsigned long tmp; __asm__ __volatile__ ( "1: \n\t" "movli.l @%2, %0 ! __cmpxchg_u32 \n\t" "mov %0, %1 \n\t" "cmp/eq %1, %3 \n\t" "bf 2f \n\t" "mov %4, %0 \n\t" "2: \n\t" "movco.l %0, @%2 \n\t" "bf 1b \n\t" "synco \n\t" : "=&z" (tmp), "=&r" (retval) : "r" (m), "r" (old), "r" (new) : "t", "memory" ); return retval; } #include <asm/cmpxchg-xchg.h> #endif /* __ASM_SH_CMPXCHG_LLSC_H */ PK ! ���W� � boot/romimage/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # linux/arch/sh/boot/romimage/Makefile # # create an romImage file suitable for burning to flash/mmc from zImage # targets := vmlinux head.o zeropage.bin piggy.o load-y := 0 mmcif-load-$(CONFIG_CPU_SUBTYPE_SH7724) := 0xe5200000 # ILRAM mmcif-obj-$(CONFIG_CPU_SUBTYPE_SH7724) := $(obj)/mmcif-sh7724.o load-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-load-y) obj-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-obj-y) LDFLAGS_vmlinux := --oformat $(ld_bfd) -Ttext $(load-y) -e romstart \ -T $(obj)/../../kernel/vmlinux.lds $(obj)/vmlinux: $(obj)/head.o $(obj-y) $(obj)/piggy.o FORCE $(call if_changed,ld) OBJCOPYFLAGS += -j .empty_zero_page $(obj)/zeropage.bin: vmlinux FORCE $(call if_changed,objcopy) LDFLAGS_piggy.o := -r --format binary --oformat $(ld_bfd) -T $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/zeropage.bin arch/sh/boot/zImage FORCE $(call if_changed,ld) PK ! ް�H H boot/compressed/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # linux/arch/sh/boot/compressed/Makefile # # create a compressed vmlinux image from the original vmlinux # targets := vmlinux vmlinux.bin vmlinux.bin.gz \ vmlinux.bin.bz2 vmlinux.bin.lzma \ vmlinux.bin.xz vmlinux.bin.lzo \ head_32.o misc.o piggy.o OBJECTS = $(obj)/head_32.o $(obj)/misc.o $(obj)/cache.o GCOV_PROFILE := n # # IMAGE_OFFSET is the load offset of the compression loader # ifeq ($(CONFIG_32BIT),y) IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_MEMORY_START) + \ $(CONFIG_BOOT_LINK_OFFSET)]') else IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_PAGE_OFFSET) + \ $(KERNEL_MEMORY) + \ $(CONFIG_BOOT_LINK_OFFSET)]') endif ccflags-remove-$(CONFIG_MCOUNT) += -pg LDFLAGS_vmlinux := --oformat $(ld_bfd) -Ttext $(IMAGE_OFFSET) -e startup \ -T $(obj)/../../kernel/vmlinux.lds # # Pull in the necessary libgcc bits from the in-kernel implementation. # lib1funcs-y := ashiftrt.S ashldi3.c ashrsi3.S ashlsi3.S lshrsi3.S lib1funcs-obj := \ $(addsuffix .o, $(basename $(addprefix $(obj)/, $(lib1funcs-y)))) lib1funcs-dir := $(srctree)/arch/$(SRCARCH)/lib KBUILD_CFLAGS += -I$(lib1funcs-dir) -DDISABLE_BRANCH_PROFILING $(addprefix $(obj)/,$(lib1funcs-y)): $(obj)/%: $(lib1funcs-dir)/% FORCE $(call cmd,shipped) $(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(lib1funcs-obj) FORCE $(call if_changed,ld) $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) vmlinux.bin.all-y := $(obj)/vmlinux.bin $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE $(call if_changed,gzip) $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE $(call if_changed,bzip2) $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE $(call if_changed,lzma) $(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE $(call if_changed,xzkern) $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE $(call if_changed,lzo) OBJCOPYFLAGS += -R .empty_zero_page LDFLAGS_piggy.o := -r --format binary --oformat $(ld_bfd) -T $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE $(call if_changed,ld) PK ! /q�q boot/Makefilenu �[��� # # arch/sh/boot/Makefile # # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive # for more details. # # Copyright (C) 1999 Stuart Menefy # # # Assign safe dummy values if these variables are not defined, # in order to suppress error message. # CONFIG_PAGE_OFFSET ?= 0x80000000 CONFIG_MEMORY_START ?= 0x0c000000 CONFIG_BOOT_LINK_OFFSET ?= 0x00800000 CONFIG_ZERO_PAGE_OFFSET ?= 0x00001000 CONFIG_ENTRY_OFFSET ?= 0x00001000 CONFIG_PHYSICAL_START ?= $(CONFIG_MEMORY_START) suffix-y := bin suffix-$(CONFIG_KERNEL_GZIP) := gz suffix-$(CONFIG_KERNEL_BZIP2) := bz2 suffix-$(CONFIG_KERNEL_LZMA) := lzma suffix-$(CONFIG_KERNEL_XZ) := xz suffix-$(CONFIG_KERNEL_LZO) := lzo targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz \ uImage.bz2 uImage.lzma uImage.xz uImage.lzo uImage.bin extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \ vmlinux.bin.xz vmlinux.bin.lzo subdir- := compressed romimage $(obj)/zImage: $(obj)/compressed/vmlinux FORCE $(call if_changed,objcopy) @echo ' Kernel: $@ is ready' $(obj)/compressed/vmlinux: FORCE $(Q)$(MAKE) $(build)=$(obj)/compressed $@ $(obj)/romImage: $(obj)/romimage/vmlinux FORCE $(call if_changed,objcopy) @echo ' Kernel: $@ is ready' $(obj)/romimage/vmlinux: $(obj)/zImage FORCE $(Q)$(MAKE) $(build)=$(obj)/romimage $@ KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_PHYSICAL_START) & 0x1fffffff]') KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_PAGE_OFFSET) + \ $(KERNEL_MEMORY) + \ $(CONFIG_ZERO_PAGE_OFFSET)]') KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_PAGE_OFFSET) + \ $(KERNEL_MEMORY) + \ $(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]') UIMAGE_LOADADDR = $(KERNEL_LOAD) UIMAGE_ENTRYADDR = $(KERNEL_ENTRY) $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) $(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE $(call if_changed,gzip) $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE $(call if_changed,bzip2) $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE $(call if_changed,lzma) $(obj)/vmlinux.bin.xz: $(obj)/vmlinux.bin FORCE $(call if_changed,xzkern) $(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE $(call if_changed,lzo) $(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 FORCE $(call if_changed,uimage,bzip2) $(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE $(call if_changed,uimage,gzip) $(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE $(call if_changed,uimage,lzma) $(obj)/uImage.xz: $(obj)/vmlinux.bin.xz FORCE $(call if_changed,uimage,xz) $(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE $(call if_changed,uimage,lzo) $(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE $(call if_changed,uimage,none) OBJCOPYFLAGS_vmlinux.srec := -I binary -O srec $(obj)/vmlinux.srec: $(obj)/compressed/vmlinux FORCE $(call if_changed,objcopy) OBJCOPYFLAGS_uImage.srec := -I binary -O srec $(obj)/uImage.srec: $(obj)/uImage FORCE $(call if_changed,objcopy) $(obj)/uImage: $(obj)/uImage.$(suffix-y) @ln -sf $(notdir $<) $@ @echo ' Image $@ is ready' export CONFIG_PAGE_OFFSET CONFIG_MEMORY_START CONFIG_BOOT_LINK_OFFSET \ CONFIG_PHYSICAL_START CONFIG_ZERO_PAGE_OFFSET CONFIG_ENTRY_OFFSET \ KERNEL_MEMORY suffix-y PK ! �/�Ь � boot/dts/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"") obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o endif PK ! WU� � Kbuildnu �[��� # SPDX-License-Identifier: GPL-2.0-only obj-y += kernel/ mm/ boards/ obj-$(CONFIG_SH_FPU_EMU) += math-emu/ obj-$(CONFIG_USE_BUILTIN_DTB) += boot/dts/ PK ! t��ê � boards/mach-sh03/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Interface (CTP/PCI-SH03) specific parts of the kernel # obj-y := setup.o obj-$(CONFIG_RTC_DRV_GENERIC) += rtc.o PK ! Pݪ� � boards/mach-dreamcast/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Sega Dreamcast specific parts of the kernel # obj-y := setup.o irq.o obj-$(CONFIG_RTC_DRV_GENERIC) += rtc.o PK ! 5�� � boards/mach-lboxre2/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the L-BOX RE2 specific parts of the kernel # Copyright (c) 2007 Nobuhiro Iwamatsu obj-y := setup.o irq.o PK ! T�_ boards/mach-ecovec24/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the R0P7724LC0011/21RL (EcoVec) # # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive # for more details. # obj-y := setup.o sdram.o PK ! Ȁ > > boards/mach-ap325rxa/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y := setup.o sdram.o PK ! zz� � boards/mach-hp6xx/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the HP6xx specific parts of the kernel # obj-y := setup.o obj-$(CONFIG_PM) += pm.o pm_wakeup.o obj-$(CONFIG_APM_EMULATION) += hp6xx_apm.o PK ! �T��� � boards/mach-sdk7786/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y := fpga.o irq.o nmi.o setup.o obj-$(CONFIG_GPIOLIB) += gpio.o obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o PK ! ��ij� � boards/mach-microdev/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the SuperH MicroDev specific parts of the kernel # obj-y := setup.o irq.o io.o fdc37c93xapm.o PK ! �+L L boards/mach-sdk7780/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 if SH_SDK7780 choice prompt "SDK7780 options" default SH_SDK7780_BASE config SH_SDK7780_BASE bool "SDK7780 with base-board support" depends on CPU_SUBTYPE_SH7780 help Selecting this option will enable support for the expansion baseboard devices. If in doubt, say Y. endchoice endif PK ! �=��x x boards/mach-sdk7780/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the SDK7780 specific parts of the kernel # obj-y := setup.o irq.o PK ! l�s$� � boards/mach-migor/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 if SH_MIGOR choice prompt "Migo-R LCD Panel Board Selection" default SH_MIGOR_QVGA config SH_MIGOR_QVGA bool "QVGA (320x240)" config SH_MIGOR_RTA_WVGA bool "RTA WVGA (800x480)" endchoice endif PK ! ��h�h h boards/mach-migor/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y := setup.o sdram.o obj-$(CONFIG_SH_MIGOR_QVGA) += lcd_qvga.o PK ! I(%y^ ^ boards/mach-x3proto/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y += setup.o ilsel.o obj-$(CONFIG_GPIOLIB) += gpio.o PK ! =�I� � boards/mach-landisk/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for I-O DATA DEVICE, INC. "LANDISK Series" # obj-y := setup.o irq.o psw.o gio.o PK ! �#� � � boards/mach-rsk/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 if SH_RSK choice prompt "RSK+ options" default SH_RSK7203 config SH_RSK7201 bool "RSK7201" depends on CPU_SUBTYPE_SH7201 config SH_RSK7203 bool "RSK7203" select GPIOLIB depends on CPU_SUBTYPE_SH7203 config SH_RSK7264 bool "RSK2+SH7264" select GPIOLIB depends on CPU_SUBTYPE_SH7264 config SH_RSK7269 bool "RSK2+SH7269" select GPIOLIB depends on CPU_SUBTYPE_SH7269 endchoice endif PK ! ��y�� � boards/mach-rsk/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y := setup.o obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o obj-$(CONFIG_SH_RSK7269) += devices-rsk7269.o PK ! U�d|= = boards/mach-sh7763rdp/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y := setup.o irq.o PK ! �'6?{& {& boards/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 menu "Board support" config SOLUTION_ENGINE bool config SH_ALPHA_BOARD bool config SH_CUSTOM_CLK def_bool y depends on !SH_DEVICE_TREE select HAVE_LEGACY_CLK config SH_DEVICE_TREE bool select OF select OF_EARLY_FLATTREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY config SH_JCORE_SOC bool "J-Core SoC" select SH_DEVICE_TREE select CLKSRC_JCORE_PIT select JCORE_AIC depends on CPU_J2 help Select this option to include drivers core components of the J-Core SoC, including interrupt controllers and timers. config SH_SOLUTION_ENGINE bool "SolutionEngine" select SOLUTION_ENGINE select CPU_HAS_IPR_IRQ depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \ CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ CPU_SUBTYPE_SH7750R help Select SolutionEngine if configuring for a Hitachi SH7705, SH7709, SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board. config SH_7206_SOLUTION_ENGINE bool "SolutionEngine7206" select SOLUTION_ENGINE depends on CPU_SUBTYPE_SH7206 help Select 7206 SolutionEngine if configuring for a Hitachi SH7206 evaluation board. config SH_7619_SOLUTION_ENGINE bool "SolutionEngine7619" select SOLUTION_ENGINE depends on CPU_SUBTYPE_SH7619 help Select 7619 SolutionEngine if configuring for a Hitachi SH7619 evaluation board. config SH_7721_SOLUTION_ENGINE bool "SolutionEngine7721" select SOLUTION_ENGINE depends on CPU_SUBTYPE_SH7721 help Select 7721 SolutionEngine if configuring for a Hitachi SH7721 evaluation board. config SH_7722_SOLUTION_ENGINE bool "SolutionEngine7722" select SOLUTION_ENGINE select GENERIC_IRQ_CHIP select IRQ_DOMAIN depends on CPU_SUBTYPE_SH7722 help Select 7722 SolutionEngine if configuring for a Hitachi SH772 evaluation board. config SH_7724_SOLUTION_ENGINE bool "SolutionEngine7724" select SOLUTION_ENGINE depends on CPU_SUBTYPE_SH7724 select GPIOLIB select SND_SOC_AK4642 if SND_SIMPLE_CARD select REGULATOR_FIXED_VOLTAGE if REGULATOR help Select 7724 SolutionEngine if configuring for a Hitachi SH7724 evaluation board. config SH_7751_SOLUTION_ENGINE bool "SolutionEngine7751" select SOLUTION_ENGINE select CPU_HAS_IPR_IRQ depends on CPU_SUBTYPE_SH7751 help Select 7751 SolutionEngine if configuring for a Hitachi SH7751 evaluation board. config SH_7780_SOLUTION_ENGINE bool "SolutionEngine7780" select SOLUTION_ENGINE select HAVE_PCI depends on CPU_SUBTYPE_SH7780 help Select 7780 SolutionEngine if configuring for a Renesas SH7780 evaluation board. config SH_7343_SOLUTION_ENGINE bool "SolutionEngine7343" select SOLUTION_ENGINE select GENERIC_IRQ_CHIP select IRQ_DOMAIN depends on CPU_SUBTYPE_SH7343 help Select 7343 SolutionEngine if configuring for a Hitachi SH7343 (SH-Mobile 3AS) evaluation board. config SH_HP6XX bool "HP6XX" select SYS_SUPPORTS_APM_EMULATION select HD6446X_SERIES depends on CPU_SUBTYPE_SH7709 help Select HP6XX if configuring for a HP jornada HP6xx. More information (hardware only) at <http://www.hp.com/jornada/>. config SH_DREAMCAST bool "Dreamcast" select HAVE_PCI depends on CPU_SUBTYPE_SH7091 help Select Dreamcast if configuring for a SEGA Dreamcast. More information at <http://www.linux-sh.org> config SH_SH03 bool "Interface CTP/PCI-SH03" depends on CPU_SUBTYPE_SH7751 select CPU_HAS_IPR_IRQ select HAVE_PCI help CTP/PCI-SH03 is a CPU module computer that is produced by Interface Corporation. More information at <http://www.interface.co.jp> config SH_SECUREEDGE5410 bool "SecureEdge5410" depends on CPU_SUBTYPE_SH7751R select CPU_HAS_IPR_IRQ select HAVE_PCI help Select SecureEdge5410 if configuring for a SnapGear SH board. This includes both the OEM SecureEdge products as well as the SME product line. config SH_RTS7751R2D bool "RTS7751R2D" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI select IO_TRAPPED if MMU help Select RTS7751R2D if configuring for a Renesas Technology Sales SH-Graphics board. config SH_RSK bool "Renesas Starter Kit" depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \ CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269 select REGULATOR_FIXED_VOLTAGE if REGULATOR help Select this option if configuring for any of the RSK+ MCU evaluation platforms. config SH_SDK7780 bool "SDK7780R3" depends on CPU_SUBTYPE_SH7780 select HAVE_PCI help Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3 evaluation board. config SH_SDK7786 bool "SDK7786" depends on CPU_SUBTYPE_SH7786 select HAVE_PCI select NO_IOPORT_MAP if !PCI select HAVE_SRAM_POOL select REGULATOR_FIXED_VOLTAGE if REGULATOR help Select SDK7786 if configuring for a Renesas Technology Europe SH7786-65nm board. config SH_HIGHLANDER bool "Highlander" depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 select HAVE_PCI select IO_TRAPPED if MMU config SH_SH7757LCR bool "SH7757LCR" depends on CPU_SUBTYPE_SH7757 select GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR config SH_SH7785LCR bool "SH7785LCR" depends on CPU_SUBTYPE_SH7785 select HAVE_PCI config SH_SH7785LCR_29BIT_PHYSMAPS bool "SH7785LCR 29bit physmaps" depends on SH_SH7785LCR && 29BIT default y help This board has 2 physical memory maps. It can be changed with DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, you can access all on-board device in 29bit address mode. config SH_SH7785LCR_PT bool "SH7785LCR prototype board on 32-bit MMU mode" depends on SH_SH7785LCR && 32BIT default n help If you use prototype board, this option is enabled. config SH_URQUELL bool "Urquell" depends on CPU_SUBTYPE_SH7786 select GPIOLIB select HAVE_PCI select NO_IOPORT_MAP if !PCI config SH_MIGOR bool "Migo-R" depends on CPU_SUBTYPE_SH7722 select GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR help Select Migo-R if configuring for the SH7722 Migo-R platform by Renesas System Solutions Asia Pte. Ltd. config SH_AP325RXA bool "AP-325RXA" depends on CPU_SUBTYPE_SH7723 select GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR help Renesas "AP-325RXA" support. Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" config SH_KFR2R09 bool "KFR2R09" depends on CPU_SUBTYPE_SH7724 select GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR help "Kit For R2R for 2009" support. config SH_ECOVEC bool "EcoVec" depends on CPU_SUBTYPE_SH7724 select GPIOLIB select SND_SOC_DA7210 if SND_SIMPLE_CARD select REGULATOR_FIXED_VOLTAGE if REGULATOR help Renesas "R0P7724LC0011/21RL (EcoVec)" support. config SH_SH7763RDP bool "SH7763RDP" depends on CPU_SUBTYPE_SH7763 help Select SH7763RDP if configuring for a Renesas SH7763 evaluation board. config SH_ESPT bool "ESPT" depends on CPU_SUBTYPE_SH7763 help Select ESPT if configuring for a Renesas SH7763 with gigabit ether evaluation board. config SH_EDOSK7705 bool "EDOSK7705" depends on CPU_SUBTYPE_SH7705 config SH_EDOSK7760 bool "EDOSK7760" depends on CPU_SUBTYPE_SH7760 help Select if configuring for a Renesas EDOSK7760 evaluation board. config SH_SH4202_MICRODEV bool "SH4-202 MicroDev" depends on CPU_SUBTYPE_SH4_202 help Select SH4-202 MicroDev if configuring for a SuperH MicroDev board with an SH4-202 CPU. config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support. config SH_TITAN bool "TITAN" depends on CPU_SUBTYPE_SH7751R select CPU_HAS_IPR_IRQ select HAVE_PCI help Select Titan if you are configuring for a Nimble Microsystems NetEngine NP51R. config SH_SHMIN bool "SHMIN" depends on CPU_SUBTYPE_SH7706 select CPU_HAS_IPR_IRQ help Select SHMIN if configuring for the SHMIN board. config SH_LBOX_RE2 bool "L-BOX RE2" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI help Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2. config SH_X3PROTO bool "SH-X3 Prototype board" depends on CPU_SUBTYPE_SHX3 select NO_IOPORT_MAP if !PCI select IRQ_DOMAIN config SH_MAGIC_PANEL_R2 bool "Magic Panel R2" depends on CPU_SUBTYPE_SH7720 select GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR help Select Magic Panel R2 if configuring for Magic Panel R2. config SH_POLARIS bool "SMSC Polaris" select CPU_HAS_IPR_IRQ select REGULATOR_FIXED_VOLTAGE if REGULATOR depends on CPU_SUBTYPE_SH7709 help Select if configuring for an SMSC Polaris development board config SH_SH2007 bool "SH-2007 board" select NO_IOPORT_MAP select REGULATOR_FIXED_VOLTAGE if REGULATOR depends on CPU_SUBTYPE_SH7780 help SH-2007 is a single-board computer based around SH7780 chip intended for embedded applications. It has an Ethernet interface (SMC9118), direct connected Compact Flash socket, two serial ports and PC-104 bus. More information at <http://sh2000.sh-linux.org>. config SH_APSH4A3A bool "AP-SH4A-3A" select SH_ALPHA_BOARD select REGULATOR_FIXED_VOLTAGE if REGULATOR depends on CPU_SUBTYPE_SH7785 help Select AP-SH4A-3A if configuring for an ALPHAPROJECT AP-SH4A-3A. config SH_APSH4AD0A bool "AP-SH4AD-0A" select SH_ALPHA_BOARD select HAVE_PCI select REGULATOR_FIXED_VOLTAGE if REGULATOR depends on CPU_SUBTYPE_SH7786 help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" source "arch/sh/boards/mach-migor/Kconfig" source "arch/sh/boards/mach-rsk/Kconfig" if SH_MAGIC_PANEL_R2 menu "Magic Panel R2 options" config SH_MAGIC_PANEL_R2_VERSION int "Magic Panel R2 Version" default "3" help Set the version of the Magic Panel R2 endmenu endif endmenu PK ! �}{ boards/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Specific board support, not covered by a mach group. # obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o obj-$(CONFIG_SH_SECUREEDGE5410) += board-secureedge5410.o obj-$(CONFIG_SH_SH2007) += board-sh2007.o obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o obj-$(CONFIG_SH_URQUELL) += board-urquell.o obj-$(CONFIG_SH_SHMIN) += board-shmin.o obj-$(CONFIG_SH_EDOSK7705) += board-edosk7705.o obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o obj-$(CONFIG_SH_ESPT) += board-espt.o obj-$(CONFIG_SH_POLARIS) += board-polaris.o obj-$(CONFIG_SH_TITAN) += board-titan.o obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o obj-$(CONFIG_SH_APSH4A3A) += board-apsh4a3a.o obj-$(CONFIG_SH_APSH4AD0A) += board-apsh4ad0a.o obj-$(CONFIG_SH_DEVICE_TREE) += of-generic.o PK ! �r�= = boards/mach-se/7722/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the HITACHI UL SolutionEngine 7722 specific parts of the kernel # # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive # for more details. # # obj-y := setup.o irq.o PK ! �b�o= = boards/mach-se/7780/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the HITACHI UL SolutionEngine 7780 specific parts of the kernel # # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive # for more details. # # obj-y := setup.o irq.o PK ! �(˄ � boards/mach-se/770x/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the 770x SolutionEngine specific parts of the kernel # obj-y := setup.o irq.o PK ! R� � boards/mach-se/7751/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the 7751 SolutionEngine specific parts of the kernel # obj-y := setup.o irq.o PK ! � {�; ; boards/mach-se/7721/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y := setup.o irq.o PK ! 2�m�� � boards/mach-se/7343/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the 7343 SolutionEngine specific parts of the kernel # obj-y := setup.o irq.o PK ! ���Մ � boards/mach-se/7206/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the 7206 SolutionEngine specific parts of the kernel # obj-y := setup.o irq.o PK ! p|Y�� � boards/mach-se/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_SH_7619_SOLUTION_ENGINE) += board-se7619.o obj-$(CONFIG_SH_SOLUTION_ENGINE) += 770x/ obj-$(CONFIG_SH_7206_SOLUTION_ENGINE) += 7206/ obj-$(CONFIG_SH_7722_SOLUTION_ENGINE) += 7722/ obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += 7751/ obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/ obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/ obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/ obj-$(CONFIG_SH_7724_SOLUTION_ENGINE) += 7724/ PK ! �_��E E boards/mach-se/7724/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the HITACHI UL SolutionEngine 7724 specific parts of the kernel # # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive # for more details. # # obj-y := setup.o irq.o sdram.o PK ! �}l} } boards/mach-kfr2r09/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y := setup.o sdram.o ifneq ($(CONFIG_FB_SH_MOBILE_LCDC),) obj-y += lcd_wqvga.o endif PK ! �� � boards/mach-highlander/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 if SH_HIGHLANDER choice prompt "Highlander options" default SH_R7780MP config SH_R7780RP bool "R7780RP-1 board support" depends on CPU_SUBTYPE_SH7780 config SH_R7780MP bool "R7780MP board support" depends on CPU_SUBTYPE_SH7780 help Selecting this option will enable support for the mass-production version of the R7780RP. If in doubt, say Y. config SH_R7785RP bool "R7785RP board support" depends on CPU_SUBTYPE_SH7785 select GPIOLIB endchoice endif PK ! ���N N boards/mach-highlander/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Highlander specific parts of the kernel # obj-y := setup.o obj-$(CONFIG_SH_R7780RP) += irq-r7780rp.o obj-$(CONFIG_SH_R7780MP) += irq-r7780mp.o obj-$(CONFIG_SH_R7785RP) += irq-r7785rp.o pinmux-r7785rp.o ifneq ($(CONFIG_SH_R7785RP),y) obj-$(CONFIG_PUSH_SWITCH) += psw.o endif PK ! M��� � boards/mach-r2d/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 if SH_RTS7751R2D menu "RTS7751R2D Board Revision" config RTS7751R2D_PLUS bool "R2D-PLUS" help Selecting this option will configure the kernel for R2D-PLUS. R2D-PLUS is the smaller of the two R2D board versions, equipped with a single PCI slot. config RTS7751R2D_1 bool "R2D-1" help Selecting this option will configure the kernel for R2D-1. R2D-1 is the larger of the two R2D board versions, equipped with two PCI slots. endmenu endif PK ! ��Ġ{ { boards/mach-r2d/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the RTS7751R2D specific parts of the kernel # obj-y := setup.o irq.o PK ! s�h� lib/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for SuperH-specific library files.. # lib-y = delay.o memmove.o memchr.o \ checksum.o strlen.o div64.o div64-generic.o # Extracted from libgcc obj-y += movmem.o ashldi3.o ashrdi3.o lshrdi3.o \ ashlsi3.o ashrsi3.o ashiftrt.o lshrsi3.o \ udiv_qrnnd.o udivsi3-y := udivsi3_i4i-Os.o ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y) udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o endif udivsi3-y += udivsi3.o obj-y += io.o memcpy-y := memcpy.o memcpy-$(CONFIG_CPU_SH4) := memcpy-sh4.o memset-y := memset.o memset-$(CONFIG_CPU_SH4) := memset-sh4.o lib-$(CONFIG_MMU) += copy_page.o __clear_user.o lib-$(CONFIG_MCOUNT) += mcount.o lib-y += $(memcpy-y) $(memset-y) $(udivsi3-y) PK ! ��7`� � tools/Makefilenu �[��� # # arch/sh/tools/Makefile # # Copyright (C) 2003 Paul Mundt # # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive # for more details. # # Shamelessly cloned from ARM. # include/generated/machtypes.h: $(src)/gen-mach-types $(src)/mach-types @echo ' Generating $@' $(Q)mkdir -p $(dir $@) $(Q)LC_ALL=C $(AWK) -f $^ > $@ PK ! ��� Kconfig.debugnu �[��� # SPDX-License-Identifier: GPL-2.0 config SH_STANDARD_BIOS bool "Use LinuxSH standard BIOS" help Say Y here if your target has the gdb-sh-stub package from www.m17n.org (or any conforming standard LinuxSH BIOS) in FLASH or EPROM. The kernel will use standard BIOS calls during boot for various housekeeping tasks (including calls to read and write characters to a system console, get a MAC address from an on-board Ethernet interface, and shut down the hardware). Note this does not work with machines with an existing operating system in mask ROM and no flash (WindowsCE machines fall in this category). If unsure, say N. config STACK_DEBUG bool "Check for stack overflows" depends on DEBUG_KERNEL && PRINTK help This option will cause messages to be printed if free stack space drops below a certain limit. Saying Y here will add overhead to every function call and will therefore incur a major performance hit. Most users should say N. config EARLY_PRINTK bool "Early printk" depends on SH_STANDARD_BIOS help Say Y here to redirect kernel printk messages to the serial port used by the SH-IPL bootloader, starting very early in the boot process and ending when the kernel's serial console is initialised. This option is only useful while porting the kernel to a new machine, when the kernel may crash or hang before the serial console is initialised. If unsure, say N. config 4KSTACKS bool "Use 4Kb for kernel stacks instead of 8Kb" depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB help If you say Y here the kernel will use a 4Kb stacksize for the kernel stack attached to each process/thread. This facilitates running more threads on a system and also reduces the pressure on the VM subsystem for higher order allocations. This option will also use IRQ stacks to compensate for the reduced stackspace. config IRQSTACKS bool "Use separate kernel stacks when processing interrupts" depends on DEBUG_KERNEL && BROKEN help If you say Y here the kernel will use separate kernel stacks for handling hard and soft interrupts. This can help avoid overflowing the process kernel stacks. config DUMP_CODE bool "Show disassembly of nearby code in register dumps" depends on DEBUG_KERNEL default y if DEBUG_BUGVERBOSE default n help This prints out a code trace of the instructions leading up to the faulting instruction as a debugging aid. As this does grow the kernel in size a bit, most users will want to say N here. Those looking for more verbose debugging output should say Y. config DWARF_UNWINDER bool "Enable the DWARF unwinder for stacktraces" depends on DEBUG_KERNEL select FRAME_POINTER default n help Enabling this option will make stacktraces more accurate, at the cost of an increase in overall kernel size. config SH_NO_BSS_INIT bool "Avoid zeroing BSS (to speed-up startup on suitable platforms)" depends on DEBUG_KERNEL default n help If running in painfully slow environments, such as an RTL simulation or from remote memory via SHdebug, where the memory can already be guaranteed to ber zeroed on boot, say Y. For all other cases, say N. If this option seems perplexing, or you aren't sure, say N. config MCOUNT def_bool y depends on STACK_DEBUG || FUNCTION_TRACER PK ! ���� � drivers/superhyway/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the SuperHyway specific kernel interface routines under Linux. # obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += ops-sh4-202.o PK ! �&��� � drivers/dma/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 menu "DMA support" config SH_DMA bool "SuperH on-chip DMA controller (DMAC) support" depends on CPU_SH3 || CPU_SH4 default n config SH_DMA_IRQ_MULTI bool depends on SH_DMA default y if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \ CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091 || \ CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7780 || \ CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7760 config SH_DMA_API depends on SH_DMA bool "SuperH DMA API support" default n help SH_DMA_API always enabled DMA API of used SuperH. If you want to use DMA ENGINE, you must not enable this. Please enable DMA_ENGINE and SH_DMAE. config NR_ONCHIP_DMA_CHANNELS int depends on SH_DMA default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ CPU_SUBTYPE_SH7760 default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \ CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724 default "6" help This allows you to specify the number of channels that the on-chip DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. config SH_DMABRG bool "SH7760 DMABRG support" depends on CPU_SUBTYPE_SH7760 help The DMABRG does data transfers from main memory to Audio/USB units of the SH7760. Say Y if you want to use Audio/USB DMA on your SH7760 board. config PVR2_DMA tristate "PowerVR 2 DMAC support" depends on SH_DREAMCAST && SH_DMA help Selecting this will enable support for the PVR2 DMA controller. As this chains off of the on-chip DMAC, that must also be enabled by default. This is primarily used by the pvr2fb framebuffer driver for certain optimizations, but is not necessary for functionality. If in doubt, say N. config G2_DMA tristate "G2 Bus DMA support" depends on SH_DREAMCAST && SH_DMA_API help This enables support for the DMA controller for the Dreamcast's G2 bus. Drivers that want this will generally enable this on their own. If in doubt, say N. endmenu PK ! ��3� drivers/dma/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the SuperH DMA specific kernel interface routines under Linux. # obj-$(CONFIG_SH_DMA_API) += dma-sh.o dma-api.o dma-sysfs.o obj-$(CONFIG_PVR2_DMA) += dma-pvr2.o obj-$(CONFIG_G2_DMA) += dma-g2.o obj-$(CONFIG_SH_DMABRG) += dmabrg.o PK ! �/� � drivers/pci/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the PCI specific kernel interface routines under Linux. # obj-y += common.o pci.o obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7786) += pcie-sh7786.o ops-sh7786.o obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ pci-dreamcast.o obj-$(CONFIG_SH_SECUREEDGE5410) += fixups-snapgear.o obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += fixups-se7751.o obj-$(CONFIG_SH_RTS7751R2D) += fixups-rts7751r2d.o obj-$(CONFIG_SH_SH03) += fixups-sh03.o obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o obj-$(CONFIG_SH_SDK7786) += fixups-sdk7786.o obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += fixups-sdk7780.o obj-$(CONFIG_SH_TITAN) += fixups-titan.o obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o PK ! �iyxG G drivers/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 source "arch/sh/drivers/dma/Kconfig" source "arch/sh/cchips/Kconfig" menu "Additional SuperH Device Drivers" config HEARTBEAT bool "Heartbeat LED" help Use the power-on LED on your machine as a load meter. The exact behavior is platform-dependent, but normally the flash frequency is a hyperbolic function of the 5-minute load average. config PUSH_SWITCH tristate "Push switch support" help This enables support for the push switch framework, a simple framework that allows for sysfs driven switch status reporting. endmenu PK ! ��ˈ drivers/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux SuperH-specific device drivers. # obj-y += dma/ platform_early.o obj-$(CONFIG_PCI) += pci/ obj-$(CONFIG_SUPERHYWAY) += superhyway/ obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT) += heartbeat.o PK ! |A+ + Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 # # DMA engine configuration for sh # config RENESAS_DMA bool select DMA_ENGINE # # DMA Engine Helpers # config SH_DMAE_BASE bool "Renesas SuperH DMA Engine support" depends on SUPERH || COMPILE_TEST depends on !SUPERH || SH_DMA depends on !SH_DMA_API default y select RENESAS_DMA help Enable support for the Renesas SuperH DMA controllers. # # DMA Controllers # config SH_DMAE tristate "Renesas SuperH DMAC support" depends on SH_DMAE_BASE help Enable support for the Renesas SuperH DMA controllers. config RCAR_DMAC tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller" depends on ARCH_RENESAS || COMPILE_TEST select RENESAS_DMA help This driver supports the general purpose DMA controller found in the Renesas R-Car Gen{2,3} and RZ/G{1,2} SoCs. config RENESAS_USB_DMAC tristate "Renesas USB-DMA Controller" depends on ARCH_RENESAS || COMPILE_TEST select RENESAS_DMA select DMA_VIRTUAL_CHANNELS help This driver supports the USB-DMA controller found in the Renesas SoCs. config RZ_DMAC tristate "Renesas RZ/G2L DMA Controller" depends on ARCH_R9A07G044 || COMPILE_TEST select RENESAS_DMA select DMA_VIRTUAL_CHANNELS help This driver supports the general purpose DMA controller found in the Renesas RZ/G2L SoC variants. PK ! \,��F F Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # DMA Engine Helpers # obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o # # DMA Controllers # shdma-y := shdmac.o shdma-objs := $(shdma-y) obj-$(CONFIG_SH_DMAE) += shdma.o obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o obj-$(CONFIG_RZ_DMAC) += rz-dmac.o PK ! ]���E E Kconfig.cpunu �[��� # SPDX-License-Identifier: GPL-2.0 menu "Processor features" choice prompt "Endianness selection" default CPU_LITTLE_ENDIAN help Some SuperH machines can be configured for either little or big endian byte order. These modes require different kernels. config CPU_LITTLE_ENDIAN bool "Little Endian" config CPU_BIG_ENDIAN bool "Big Endian" endchoice config SH_FPU def_bool y prompt "FPU support" depends on CPU_HAS_FPU help Selecting this option will enable support for SH processors that have FPU units (ie, SH77xx). This option must be set in order to enable the FPU. config SH_FPU_EMU def_bool n prompt "FPU emulation support" depends on !SH_FPU help Selecting this option will enable support for software FPU emulation. Most SH-3 users will want to say Y here, whereas most SH-4 users will want to say N. config SH_DSP def_bool y prompt "DSP support" depends on CPU_HAS_DSP help Selecting this option will enable support for SH processors that have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP). This option must be set in order to enable the DSP. config SH_ADC def_bool y prompt "ADC support" depends on CPU_SH3 help Selecting this option will allow the Linux kernel to use SH3 on-chip ADC module. If unsure, say N. config SH_STORE_QUEUES bool "Support for Store Queues" depends on CPU_SH4 help Selecting this option will enable an in-kernel API for manipulating the store queues integrated in the SH-4 processors. config SPECULATIVE_EXECUTION bool "Speculative subroutine return" depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786 help This enables support for a speculative instruction fetch for subroutine return. There are various pitfalls associated with this, as outlined in the SH7780 hardware manual. If unsure, say N. config CPU_HAS_INTEVT bool config CPU_HAS_IPR_IRQ bool config CPU_HAS_SR_RB bool help This will enable the use of SR.RB register bank usage. Processors that are lacking this bit must have another method in place for accomplishing what is taken care of by the banked registers. See <file:Documentation/sh/register-banks.rst> for further information on SR.RB and register banking in the kernel in general. config CPU_HAS_PTEAEX bool config CPU_HAS_DSP bool config CPU_HAS_FPU bool endmenu PK ! }��n� � mm/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 menu "Memory management options" config MMU bool "Support for memory management hardware" depends on !CPU_SH2 default y help Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to boot on these systems, this option must not be set. On other systems (such as the SH-3 and 4) where an MMU exists, turning this off will boot the kernel on these machines with the MMU implicitly switched off. config PAGE_OFFSET hex default "0x80000000" if MMU default "0x00000000" config FORCE_MAX_ZONEORDER int "Maximum zone order" range 9 64 if PAGE_SIZE_16KB default "9" if PAGE_SIZE_16KB range 7 64 if PAGE_SIZE_64KB default "7" if PAGE_SIZE_64KB range 11 64 default "14" if !MMU default "11" help The kernel memory allocator divides physically contiguous memory blocks into "zones", where each zone is a power of two number of pages. This option selects the largest power of two that the kernel keeps in the memory allocator. If you need to allocate very large blocks of physically contiguous memory, then you may need to increase this value. This config option is actually maximum order plus one. For example, a value of 11 means that the largest free memory block is 2^10 pages. The page size is not necessarily 4KB. Keep this in mind when choosing a value for this option. config MEMORY_START hex "Physical memory start address" default "0x08000000" help Computers built with Hitachi SuperH processors always map the ROM starting at address zero. But the processor does not specify the range that RAM takes. The physical memory (RAM) start address will be automatically set to 08000000. Other platforms, such as the Solution Engine boards typically map RAM at 0C000000. Tweak this only when porting to a new machine which does not already have a defconfig. Changing it from the known correct value on any of the known systems will only lead to disaster. config MEMORY_SIZE hex "Physical memory size" default "0x04000000" help This sets the default memory size assumed by your SH kernel. It can be overridden as normal by the 'mem=' argument on the kernel command line. If unsure, consult your board specifications or just leave it as 0x04000000 which was the default value before this became configurable. # Physical addressing modes config 29BIT def_bool !32BIT select UNCACHED_MAPPING config 32BIT bool default !MMU config PMB bool "Support 32-bit physical addressing through PMB" depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP select 32BIT select UNCACHED_MAPPING help If you say Y here, physical addressing will be extended to 32-bits through the SH-4A PMB. If this is not set, legacy 29-bit physical addressing will be used. config X2TLB def_bool y depends on (CPU_SHX2 || CPU_SHX3) && MMU config VSYSCALL bool "Support vsyscall page" depends on MMU && (CPU_SH3 || CPU_SH4) default y help This will enable support for the kernel mapping a vDSO page in process space, and subsequently handing down the entry point to the libc through the ELF auxiliary vector. From the kernel side this is used for the signal trampoline. For systems with an MMU that can afford to give up a page, (the default value) say Y. config NUMA bool "Non-Uniform Memory Access (NUMA) Support" depends on MMU && SYS_SUPPORTS_NUMA select ARCH_WANT_NUMA_VARIABLE_LOCALITY default n help Some SH systems have many various memories scattered around the address space, each with varying latencies. This enables support for these blocks by binding them to nodes and allowing memory policies to be used for prioritizing and controlling allocation behaviour. config NODES_SHIFT int default "3" if CPU_SUBTYPE_SHX3 default "1" depends on NUMA config ARCH_FLATMEM_ENABLE def_bool y depends on !NUMA config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC config ARCH_SPARSEMEM_DEFAULT def_bool y config ARCH_SELECT_MEMORY_MODEL def_bool y config ARCH_MEMORY_PROBE def_bool y depends on MEMORY_HOTPLUG config IOREMAP_FIXED def_bool y depends on X2TLB config UNCACHED_MAPPING bool config HAVE_SRAM_POOL bool select GENERIC_ALLOCATOR choice prompt "Kernel page size" default PAGE_SIZE_4KB config PAGE_SIZE_4KB bool "4kB" help This is the default page size used by all SuperH CPUs. config PAGE_SIZE_8KB bool "8kB" depends on !MMU || X2TLB help This enables 8kB pages as supported by SH-X2 and later MMUs. config PAGE_SIZE_16KB bool "16kB" depends on !MMU help This enables 16kB pages on MMU-less SH systems. config PAGE_SIZE_64KB bool "64kB" depends on !MMU || CPU_SH4 help This enables support for 64kB pages, possible on all SH-4 CPUs and later. endchoice choice prompt "HugeTLB page size" depends on HUGETLB_PAGE default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB default HUGETLB_PAGE_SIZE_64K config HUGETLB_PAGE_SIZE_64K bool "64kB" depends on !PAGE_SIZE_64KB config HUGETLB_PAGE_SIZE_256K bool "256kB" depends on X2TLB config HUGETLB_PAGE_SIZE_1MB bool "1MB" config HUGETLB_PAGE_SIZE_4MB bool "4MB" depends on X2TLB config HUGETLB_PAGE_SIZE_64MB bool "64MB" depends on X2TLB endchoice config SCHED_MC bool "Multi-core scheduler support" depends on SMP default y help Multi-core scheduler support improves the CPU scheduler's decision making when dealing with multi-core CPU chips at a cost of slightly increased overhead in some places. If unsure say N here. endmenu menu "Cache configuration" config SH7705_CACHE_32KB bool "Enable 32KB cache size for SH7705" depends on CPU_SUBTYPE_SH7705 default y choice prompt "Cache mode" default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) config CACHE_WRITEBACK bool "Write-back" config CACHE_WRITETHROUGH bool "Write-through" help Selecting this option will configure the caches in write-through mode, as opposed to the default write-back configuration. Since there's sill some aliasing issues on SH-4, this option will unfortunately still require the majority of flushing functions to be implemented to deal with aliasing. If unsure, say N. config CACHE_OFF bool "Off" endchoice endmenu PK ! �ߒ�' ' mm/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux SuperH-specific parts of the memory manager. # obj-y := alignment.o cache.o init.o consistent.o mmap.o cacheops-$(CONFIG_CPU_J2) := cache-j2.o cacheops-$(CONFIG_CPU_SUBTYPE_SH7619) := cache-sh2.o cacheops-$(CONFIG_CPU_SH2A) := cache-sh2a.o cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o cacheops-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o cacheops-$(CONFIG_CPU_SHX3) += cache-shx3.o obj-y += $(cacheops-y) mmu-y := nommu.o extable_32.o mmu-$(CONFIG_MMU) := extable_32.o fault.o ioremap.o kmap.o \ pgtable.o tlbex_32.o tlbflush_32.o obj-y += $(mmu-y) debugfs-y := asids-debugfs.o ifndef CONFIG_CACHE_OFF debugfs-$(CONFIG_CPU_SH4) += cache-debugfs.o endif ifdef CONFIG_MMU debugfs-$(CONFIG_CPU_SH4) += tlb-debugfs.o tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o tlb-urb.o tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o tlb-urb.o obj-y += $(tlb-y) endif obj-$(CONFIG_DEBUG_FS) += $(debugfs-y) obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_PMB) += pmb.o obj-$(CONFIG_NUMA) += numa.o obj-$(CONFIG_IOREMAP_FIXED) += ioremap_fixed.o obj-$(CONFIG_UNCACHED_MAPPING) += uncached.o obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o GCOV_PROFILE_pmb.o := n PK ! ��� � kernel/cpu/sh4a/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH SH-4 backends. # # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o obj-$(CONFIG_CPU_SUBTYPE_SH7734) += setup-sh7734.o obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o # SMP setup smp-$(CONFIG_CPU_SHX3) := smp-shx3.o # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o clock-$(CONFIG_CPU_SUBTYPE_SH7734) := clock-sh7734.o clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o # Pinmux setup pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7734) := pinmux-sh7734.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o obj-y += $(clock-y) obj-$(CONFIG_SMP) += $(smp-y) obj-$(CONFIG_GPIOLIB) += $(pinmux-y) obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += ubc.o PK ! gXI� � kernel/cpu/shmobile/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH SH-Mobile backends. # # Power Management & Sleep mode obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o PK ! i�jV& & kernel/cpu/sh3/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH SH-3 backends. # obj-y := ex.o probe.o entry.o setup-sh3.o obj-$(CONFIG_HIBERNATION) += swsusp.o # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o serial-sh770x.o obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o serial-sh770x.o obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh770x.o serial-sh770x.o obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh770x.o serial-sh770x.o obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o serial-sh770x.o obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o serial-sh7710.o obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o serial-sh7710.o obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o serial-sh7720.o obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o serial-sh7720.o # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SH3) := clock-sh3.o clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o clock-$(CONFIG_CPU_SUBTYPE_SH7712) := clock-sh7712.o # Pinmux setup pinmux-$(CONFIG_CPU_SUBTYPE_SH7720) := pinmux-sh7720.o obj-y += $(clock-y) obj-$(CONFIG_GPIOLIB) += $(pinmux-y) PK ! ǃן � kernel/cpu/irq/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH CPU-specific IRQ handlers. # obj-y += imask.o obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o PK ! �J�S kernel/cpu/sh2/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH SH-2 backends. # obj-y := ex.o probe.o entry.o obj-$(CONFIG_CPU_SUBTYPE_SH7619) += setup-sh7619.o clock-sh7619.o # SMP setup smp-$(CONFIG_CPU_J2) := smp-j2.o obj-$(CONFIG_SMP) += $(smp-y) PK ! em~�� � kernel/cpu/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH CPU-specific backends. # obj-$(CONFIG_CPU_SH2) = sh2/ obj-$(CONFIG_CPU_SH2A) = sh2a/ obj-$(CONFIG_CPU_SH3) = sh3/ obj-$(CONFIG_CPU_SH4) = sh4/ # Special cases for family ancestry. obj-$(CONFIG_CPU_SH4A) += sh4a/ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ # Common interfaces. obj-$(CONFIG_SH_ADC) += adc.o obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o PK ! �EBb b kernel/cpu/sh2a/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH SH-2A backends. # obj-y := common.o probe.o opcode_helper.o common-y += ex.o entry.o obj-$(CONFIG_SH_FPU) += fpu.o obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o obj-$(CONFIG_CPU_SUBTYPE_SH7269) += setup-sh7269.o clock-sh7269.o obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o # Pinmux setup pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o obj-$(CONFIG_GPIOLIB) += $(pinmux-y) PK ! ��m͊ � kernel/cpu/sh4/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH SH-4 backends. # obj-y := probe.o common.o common-y += $(addprefix ../sh3/, entry.o ex.o) obj-$(CONFIG_HIBERNATION) += $(addprefix ../sh3/, swsusp.o) obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o obj-$(CONFIG_SH_STORE_QUEUES) += sq.o # Perf events perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750S) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7091) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7751) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o # Primary on-chip clocks (common) ifndef CONFIG_CPU_SH4A clock-$(CONFIG_CPU_SH4) := clock-sh4.o endif # Additional clocks by subtype clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o obj-y += $(clock-y) obj-$(CONFIG_PERF_EVENTS) += $(perf-y) PK ! ��W� � kernel/syscalls/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 kapi := arch/$(SRCARCH)/include/generated/asm uapi := arch/$(SRCARCH)/include/generated/uapi/asm _dummy := $(shell [ -d '$(uapi)' ] || mkdir -p '$(uapi)') \ $(shell [ -d '$(kapi)' ] || mkdir -p '$(kapi)') syscall := $(src)/syscall.tbl syshdr := $(srctree)/scripts/syscallhdr.sh systbl := $(srctree)/scripts/syscalltbl.sh quiet_cmd_syshdr = SYSHDR $@ cmd_syshdr = $(CONFIG_SHELL) $(syshdr) --emit-nr $< $@ quiet_cmd_systbl = SYSTBL $@ cmd_systbl = $(CONFIG_SHELL) $(systbl) $< $@ $(uapi)/unistd_32.h: $(syscall) $(syshdr) FORCE $(call if_changed,syshdr) $(kapi)/syscall_table.h: $(syscall) $(systbl) FORCE $(call if_changed,systbl) uapisyshdr-y += unistd_32.h kapisyshdr-y += syscall_table.h uapisyshdr-y := $(addprefix $(uapi)/, $(uapisyshdr-y)) kapisyshdr-y := $(addprefix $(kapi)/, $(kapisyshdr-y)) targets += $(addprefix ../../../../, $(uapisyshdr-y) $(kapisyshdr-y)) PHONY += all all: $(uapisyshdr-y) $(kapisyshdr-y) @: PK ! �NB� kernel/vsyscall/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-y += vsyscall.o vsyscall-syscall.o vsyscall-syms.o $(obj)/vsyscall-syscall.o: \ $(foreach F,trapa,$(obj)/vsyscall-$F.so) # Teach kbuild about targets targets += $(foreach F,trapa,vsyscall-$F.o vsyscall-$F.so) targets += vsyscall-note.o vsyscall.lds vsyscall-dummy.o # The DSO images are built using a special linker script quiet_cmd_syscall = SYSCALL $@ cmd_syscall = $(CC) -nostdlib $(SYSCFLAGS_$(@F)) \ -Wl,-T,$(filter-out FORCE,$^) -o $@ export CPPFLAGS_vsyscall.lds += -P -C -Ush vsyscall-flags = -shared -s -Wl,-soname=linux-gate.so.1 -Wl,--hash-style=sysv SYSCFLAGS_vsyscall-trapa.so = $(vsyscall-flags) $(obj)/vsyscall-trapa.so: \ $(obj)/vsyscall-%.so: $(src)/vsyscall.lds $(obj)/vsyscall-%.o FORCE $(call if_changed,syscall) # We also create a special relocatable object that should mirror the symbol # table and layout of the linked DSO. With ld -R we can then refer to # these symbols in the kernel code rather than hand-coded addresses. SYSCFLAGS_vsyscall-dummy.o = -r $(obj)/vsyscall-dummy.o: $(src)/vsyscall.lds \ $(obj)/vsyscall-trapa.o $(obj)/vsyscall-note.o FORCE $(call if_changed,syscall) LDFLAGS_vsyscall-syms.o := -r -R $(obj)/vsyscall-syms.o: $(obj)/vsyscall-dummy.o FORCE $(call if_changed,ld) PK ! _n�� � kernel/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Linux/SuperH kernel. # extra-y := head_32.o vmlinux.lds ifdef CONFIG_FUNCTION_TRACER # Do not profile debug and lowlevel utilities CFLAGS_REMOVE_ftrace.o = -pg endif CFLAGS_REMOVE_return_address.o = -pg obj-y := debugtraps.o dumpstack.o \ idle.o io.o irq.o irq_32.o kdebugfs.o \ machvec.o nmi_debug.o process.o \ process_32.o ptrace.o ptrace_32.o \ reboot.o return_address.o \ setup.o signal_32.o sys_sh.o \ syscalls_32.o time.o topology.o traps.o \ traps_32.o unwinder.o ifndef CONFIG_GENERIC_IOMAP obj-y += iomap.o obj-$(CONFIG_HAS_IOPORT_MAP) += ioport.o endif obj-y += sys_sh32.o obj-y += cpu/ obj-$(CONFIG_VSYSCALL) += vsyscall/ obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_MODULES) += sh_ksyms_32.o module.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_IO_TRAPPED) += io_trapped.o obj-$(CONFIG_KPROBES) += kprobes.o obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o obj-$(CONFIG_DUMP_CODE) += disassemble.o obj-$(CONFIG_HIBERNATION) += swsusp.o obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o obj-$(CONFIG_DMA_NONCOHERENT) += dma-coherent.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o PK ! >�L8 8 math-emu/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only obj-y := math.o PK ! y�oa a maple/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only # Makefile for Maple Bus obj-$(CONFIG_MAPLE) := maple.o PK ! ��M�[ [ clk/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only obj-y := core.o obj-$(CONFIG_SH_CLK_CPG) += cpg.o PK ! 7��/� � superhyway/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only # # Makefile for the SuperHyway bus drivers. # obj-$(CONFIG_SUPERHYWAY) += superhyway.o obj-$(CONFIG_SYSFS) += superhyway-sysfs.o PK ! �%�� � intc/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only config SH_INTC bool select IRQ_DOMAIN if SH_INTC comment "Interrupt controller options" config INTC_USERIMASK bool "Userspace interrupt masking support" depends on (SUPERH && CPU_SH4A) || COMPILE_TEST help This enables support for hardware-assisted userspace hardirq masking. SH-4A and newer interrupt blocks all support a special shadowed page with all non-masking registers obscured when mapped in to userspace. This is primarily for use by userspace device drivers that are using special priority levels. If in doubt, say N. config INTC_BALANCING bool "Hardware IRQ balancing support" depends on SMP && SUPERH && CPU_SHX3 help This enables support for IRQ auto-distribution mode on SH-X3 SMP parts. All of the balancing and CPU wakeup decisions are taken care of automatically by hardware for distributed vectors. If in doubt, say N. config INTC_MAPPING_DEBUG bool "Expose IRQ to per-controller id mapping via debugfs" depends on DEBUG_FS help This will create a debugfs entry for showing the relationship between system IRQs and the per-controller id tables. If in doubt, say N. endif PK ! �gp� � intc/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only obj-y := access.o chip.o core.o handle.o irqdomain.o virq.o obj-$(CONFIG_INTC_BALANCING) += balancing.o obj-$(CONFIG_INTC_USERIMASK) += userimask.o obj-$(CONFIG_INTC_MAPPING_DEBUG) += virq-debugfs.o PK ! �Pya a cchips/hd6446x/Makefilenu �[��� PK ! �8�� � cchips/Kconfignu �[��� PK ! Ʋ9j� � � include/mach-sh03/mach/io.hnu �[��� PK ! "�hM� � ' include/mach-sh03/mach/sh03.hnu �[��� PK ! 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