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PK ! ���) ) h3xxx.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Definitions for Compaq iPAQ H3100 and H3600 handheld computers * * (c) 2000 Compaq Computer Corporation. (Author: Jamey Hicks) * (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru> */ #ifndef _INCLUDE_H3XXX_H_ #define _INCLUDE_H3XXX_H_ #include "hardware.h" /* Gives GPIO_MAX */ /* Physical memory regions corresponding to chip selects */ #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) #define H3600_BANK_2_PHYS SA1100_CS2_PHYS #define H3600_BANK_4_PHYS SA1100_CS4_PHYS /* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ #define H3600_EGPIO_VIRT 0xf0000000 #define H3600_BANK_2_VIRT 0xf1000000 #define H3600_BANK_4_VIRT 0xf3800000 /* * gpiolib numbers for all iPAQs */ #define H3XXX_GPIO_PWR_BUTTON 0 #define H3XXX_GPIO_PCMCIA_CD1 10 #define H3XXX_GPIO_PCMCIA_IRQ1 11 #define H3XXX_GPIO_PCMCIA_CD0 17 #define H3XXX_GPIO_ACTION_BUTTON 18 #define H3XXX_GPIO_SYS_CLK 19 #define H3XXX_GPIO_PCMCIA_IRQ0 21 #define H3XXX_GPIO_COM_DCD 23 #define H3XXX_GPIO_OPTION 24 #define H3XXX_GPIO_COM_CTS 25 #define H3XXX_GPIO_COM_RTS 26 /* machine-specific gpios */ #define H3100_GPIO_BT_ON 2 #define H3100_GPIO_QMUTE 4 #define H3100_GPIO_LCD_3V_ON 5 #define H3100_GPIO_AUD_ON 6 #define H3100_GPIO_AUD_PWR_ON 7 #define H3100_GPIO_IR_ON 8 #define H3100_GPIO_IR_FSEL 9 #define H3600_GPIO_CLK_SET0 12 /* audio sample rate clock generator */ #define H3600_GPIO_CLK_SET1 13 #define H3600_GPIO_SOFT_RESET 20 /* also known as BATT_FAULT */ #define H3600_GPIO_OPT_LOCK 22 #define H3600_GPIO_OPT_DET 27 /* H3100 / 3600 EGPIO pins */ #define H3XXX_EGPIO_BASE (GPIO_MAX + 1) #define H3XXX_EGPIO_VPP_ON (H3XXX_EGPIO_BASE + 0) #define H3XXX_EGPIO_CARD_RESET (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card. active high. */ #define H3XXX_EGPIO_OPT_RESET (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack. active high. */ #define H3XXX_EGPIO_CODEC_NRESET (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341. active low. */ #define H3XXX_EGPIO_OPT_NVRAM_ON (H3XXX_EGPIO_BASE + 4) /* apply power to optionpack nvram, active high. */ #define H3XXX_EGPIO_OPT_ON (H3XXX_EGPIO_BASE + 5) /* full power to option pack. active high. */ #define H3XXX_EGPIO_LCD_ON (H3XXX_EGPIO_BASE + 6) /* enable 3.3V to LCD. active high. */ #define H3XXX_EGPIO_RS232_ON (H3XXX_EGPIO_BASE + 7) /* UART3 transceiver force on. Active high. */ /* H3600 only EGPIO pins */ #define H3600_EGPIO_LCD_PCI (H3XXX_EGPIO_BASE + 8) /* LCD control IC enable. active high. */ #define H3600_EGPIO_IR_ON (H3XXX_EGPIO_BASE + 9) /* apply power to IR module. active high. */ #define H3600_EGPIO_AUD_AMP_ON (H3XXX_EGPIO_BASE + 10) /* apply power to audio power amp. active high. */ #define H3600_EGPIO_AUD_PWR_ON (H3XXX_EGPIO_BASE + 11) /* apply power to reset of audio circuit. active high. */ #define H3600_EGPIO_QMUTE (H3XXX_EGPIO_BASE + 12) /* mute control for onboard UDA1341. active high. */ #define H3600_EGPIO_IR_FSEL (H3XXX_EGPIO_BASE + 13) /* IR speed select: 1->fast, 0->slow */ #define H3600_EGPIO_LCD_5V_ON (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */ #define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */ void __init h3xxx_map_io(void); void __init h3xxx_mach_init(void); #endif /* _INCLUDE_H3XXX_H_ */ PK ! � _� � uncompress.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/uncompress.h * * Copyright (C) 2002 Intel Corporation. * Copyright (C) 2003-2004 MontaVista Software, Inc. */ #ifndef _ARCH_UNCOMPRESS_H_ #define _ARCH_UNCOMPRESS_H_ #include "ixp4xx-regs.h" #include <asm/mach-types.h> #include <linux/serial_reg.h> #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) volatile u32* uart_base; static inline void putc(int c) { /* Check THRE and TEMT bits before we transmit the character. */ while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) barrier(); *uart_base = c; } static void flush(void) { } static __inline__ void __arch_decomp_setup(unsigned long arch_id) { /* * Some boards are using UART2 as console */ if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2() || machine_is_devixp() || machine_is_miccpt() || machine_is_mic256()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; } /* * arch_id is a variable in decompress_kernel() */ #define arch_decomp_setup() __arch_decomp_setup(arch_id) #endif PK ! ]_��2 2 irqs.hnu �[��� /* * arch/arm/mach-omap2/include/mach/irqs.h */ PK ! Mj��a a nanoengine.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-sa1100/include/mach/nanoengine.h * * This file contains the hardware specific definitions for nanoEngine. * Only include this file from SA1100-specific files. * * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> */ #ifndef __ASM_ARCH_NANOENGINE_H #define __ASM_ARCH_NANOENGINE_H #include <mach/irqs.h> #define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ #define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ #define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ #define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ #define GPIO_PC_RESET0 15 /* reset socket 0 */ #define GPIO_PC_RESET1 16 /* reset socket 1 */ #define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 #define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 #define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12 #define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13 #define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14 /* * nanoEngine Memory Map: * * 0000.0000 - 003F.0000 - 4 MB Flash * C000.0000 - C1FF.FFFF - 32 MB SDRAM * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode * */ #define NANO_PCI_MEM_RW_PHYS 0x18600000 #define NANO_PCI_MEM_RW_VIRT 0xf1000000 #define NANO_PCI_MEM_RW_SIZE SZ_1M #define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000 #define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000 #define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K #endif PK ! }��Z bitfield.hnu �[��� /* * FILE bitfield.h * * Version 1.1 * Author Copyright (c) Marc A. Viredaz, 1998 * DEC Western Research Laboratory, Palo Alto, CA * Date April 1998 (April 1997) * System Advanced RISC Machine (ARM) * Language C or ARM Assembly * Purpose Definition of macros to operate on bit fields. */ #ifndef __BITFIELD_H #define __BITFIELD_H #ifndef __ASSEMBLY__ #define UData(Data) ((unsigned long) (Data)) #else #define UData(Data) (Data) #endif /* * MACRO: Fld * * Purpose * The macro "Fld" encodes a bit field, given its size and its shift value * with respect to bit 0. * * Note * A more intuitive way to encode bit fields would have been to use their * mask. However, extracting size and shift value information from a bit * field's mask is cumbersome and might break the assembler (255-character * line-size limit). * * Input * Size Size of the bit field, in number of bits. * Shft Shift value of the bit field with respect to bit 0. * * Output * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) /* * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit * * Purpose * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return * the size, shift value, mask, aligned mask, and first bit of a * bit field. * * Input * Field Encoded bit field (using the macro "Fld"). * * Output * FSize Size of the bit field, in number of bits. * FShft Shift value of the bit field with respect to bit 0. * FMsk Mask for the bit field. * FAlnMsk Mask for the bit field, aligned on bit 0. * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) #define FShft(Field) ((Field) & 0x0000FFFF) #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) #define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) #define F1stBit(Field) (UData (1) << FShft (Field)) /* * MACRO: FInsrt * * Purpose * The macro "FInsrt" inserts a value into a bit field by shifting the * former appropriately. * * Input * Value Bit-field value. * Field Encoded bit field (using the macro "Fld"). * * Output * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ (UData (Value) << FShft (Field)) /* * MACRO: FExtr * * Purpose * The macro "FExtr" extracts the value of a bit field by masking and * shifting it appropriately. * * Input * Data Data containing the bit-field to be extracted. * Field Encoded bit field (using the macro "Fld"). * * Output * FExtr Bit-field value. */ #define FExtr(Data, Field) \ ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) #endif /* __BITFIELD_H */ PK ! �1DB B neponset.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-sa1100/include/mach/neponset.h * * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net> * * This file contains the hardware specific definitions for Assabet * Only include this file from SA1100-specific files. * * 2000/05/23 John Dorsey <john+@cs.cmu.edu> * Definitions for Neponset added. */ #ifndef __ASM_ARCH_NEPONSET_H #define __ASM_ARCH_NEPONSET_H /* * Neponset definitions: */ #define NCR_GP01_OFF (1<<0) #define NCR_TP_PWR_EN (1<<1) #define NCR_MS_PWR_EN (1<<2) #define NCR_ENET_OSC_EN (1<<3) #define NCR_SPI_KB_WK_UP (1<<4) #define NCR_A0VPP (1<<5) #define NCR_A1VPP (1<<6) void neponset_ncr_frob(unsigned int, unsigned int); #define neponset_ncr_set(v) neponset_ncr_frob(0, v) #define neponset_ncr_clear(v) neponset_ncr_frob(v, 0) #endif PK ! �� � mtd-xip.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * MTD primitives for XIP support. Architecture specific functions * * Do not include this file directly. It's included from linux/mtd/xip.h * * Author: Nicolas Pitre * Created: Nov 2, 2004 * Copyright: (C) 2004 MontaVista Software, Inc. */ #ifndef __ARCH_SA1100_MTD_XIP_H__ #define __ARCH_SA1100_MTD_XIP_H__ #include <mach/hardware.h> #define xip_irqpending() (ICIP & ICMR) /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ #define xip_currtime() readl_relaxed(OSCR) #define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4) #endif /* __ARCH_SA1100_MTD_XIP_H__ */ PK ! �@��� � hardware.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/hardware.h * * Copyright (C) 2002 Intel Corporation. * Copyright (C) 2003-2004 MontaVista Software, Inc. */ /* * Hardware definitions for IXP4xx based systems */ #ifndef __ASM_ARCH_HARDWARE_H__ #define __ASM_ARCH_HARDWARE_H__ #ifdef CONFIG_IXP4XX_INDIRECT_PCI #define PCIBIOS_MAX_MEM 0x4FFFFFFF #else #define PCIBIOS_MAX_MEM 0x4BFFFFFF #endif /* Register locations and bits */ #include "ixp4xx-regs.h" #ifndef __ASSEMBLER__ #include <linux/soc/ixp4xx/cpu.h> #endif /* Platform helper functions and definitions */ #include "platform.h" #endif /* _ASM_ARCH_HARDWARE_H */ PK ! ��W��~ �~ SA-1100.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * FILE SA-1100.h * * Version 1.2 * Author Copyright (c) Marc A. Viredaz, 1998 * DEC Western Research Laboratory, Palo Alto, CA * Date January 1998 (April 1997) * System StrongARM SA-1100 * Language C or ARM Assembly * Purpose Definition of constants related to the StrongARM * SA-1100 microprocessor (Advanced RISC Machine (ARM) * architecture version 4). This file is based on the * StrongARM SA-1100 data sheet version 2.2. * */ /* Be sure that virtual mapping is defined right */ #ifndef __ASM_ARCH_HARDWARE_H #error You must include hardware.h not SA-1100.h #endif #include "bitfield.h" /* * SA1100 CS line to physical address */ #define SA1100_CS0_PHYS 0x00000000 #define SA1100_CS1_PHYS 0x08000000 #define SA1100_CS2_PHYS 0x10000000 #define SA1100_CS3_PHYS 0x18000000 #define SA1100_CS4_PHYS 0x40000000 #define SA1100_CS5_PHYS 0x48000000 /* * Personal Computer Memory Card International Association (PCMCIA) sockets */ #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ (0x20000000 + (Nb)*PCMCIASp) #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ (_PCMCIA (Nb) + 2*PCMCIAPrtSp) #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ (_PCMCIA (Nb) + 3*PCMCIAPrtSp) #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ /* * Universal Serial Bus (USB) Device Controller (UDC) control registers * * Registers * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control Register (read/write). * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Address Register (read/write). * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Output Maximum Packet size register * (read/write). * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Input Maximum Packet size register * (read/write). * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 0 * (read/write). * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 1 * (output, read/write). * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Control/Status register end-point 2 * (input, read/write). * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Data register end-point 0 * (read/write). * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Write Count register end-point 0 * (read). * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Data Register (read/write). * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device * Controller (UDC) Status Register (read/write). */ #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ #define UDCCR_UDD 0x00000001 /* UDC Disable */ #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ /* (disable) */ #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ /* (disable) */ #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ /* (disable) */ #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ /* (disable) */ #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ #define UDCAR_ADD Fld (7, 0) /* function ADDress */ #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ /* [byte] */ #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ /* [byte] */ #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCIMP_INMAXP)) #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ #define UDCCS0_SST 0x00000004 /* Sent STall */ #define UDCCS0_FST 0x00000008 /* Force STall */ #define UDCCS0_DE 0x00000010 /* Data End */ #define UDCCS0_SE 0x00000020 /* Setup End (read) */ #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ /* (write) */ #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ /* Service request (read) */ #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ #define UDCCS1_SST 0x00000008 /* Sent STall */ #define UDCCS1_FST 0x00000010 /* Force STall */ #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ /* Service request (read) */ #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ #define UDCCS2_SST 0x00000010 /* Sent STall */ #define UDCCS2_FST 0x00000020 /* Force STall */ #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #define UDCWC_WC Fld (4, 0) /* Write Count */ #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ /* * Universal Asynchronous Receiver/Transmitter (UART) control registers * * Registers * Ser1UTCR0 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 0 * (read/write). * Ser1UTCR1 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 1 * (read/write). * Ser1UTCR2 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 2 * (read/write). * Ser1UTCR3 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 3 * (read/write). * Ser1UTDR Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Data Register * (read/write). * Ser1UTSR0 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 0 * (read/write). * Ser1UTSR1 Serial port 1 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 1 (read). * * Ser2UTCR0 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 0 * (read/write). * Ser2UTCR1 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 1 * (read/write). * Ser2UTCR2 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 2 * (read/write). * Ser2UTCR3 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 3 * (read/write). * Ser2UTCR4 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 4 * (read/write). * Ser2UTDR Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Data Register * (read/write). * Ser2UTSR0 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 0 * (read/write). * Ser2UTSR1 Serial port 2 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 1 (read). * * Ser3UTCR0 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 0 * (read/write). * Ser3UTCR1 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 1 * (read/write). * Ser3UTCR2 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 2 * (read/write). * Ser3UTCR3 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Control Register 3 * (read/write). * Ser3UTDR Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Data Register * (read/write). * Ser3UTSR0 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 0 * (read/write). * Ser3UTSR1 Serial port 3 Universal Asynchronous * Receiver/Transmitter (UART) Status Register 1 (read). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz * or 3.5795 MHz). * fua, Tua Frequency, period of the UART communication. */ #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ /* Those are still used in some places */ #define _Ser1UTCR0 __PREG(Ser1UTCR0) #define _Ser2UTCR0 __PREG(Ser2UTCR0) #define _Ser3UTCR0 __PREG(Ser3UTCR0) /* Register offsets */ #define UTCR0 0x00 #define UTCR1 0x04 #define UTCR2 0x08 #define UTCR3 0x0c #define UTDR 0x14 #define UTSR0 0x1c #define UTSR1 0x20 #define UTCR0_PE 0x00000001 /* Parity Enable */ #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ #define UTCR0_SBS 0x00000004 /* Stop Bit Select */ #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ #define UTCR0_DSS 0x00000008 /* Data Size Select */ #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ /* (ser. port 1: GPIO [18], */ /* ser. port 3: GPIO [20]) */ #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ (UTCR0_1StpBit + UTCR0_8BitData) #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ /* fua = fxtl/(16*(BRD[11:0] + 1)) */ /* Tua = 16*(BRD [11:0] + 1)*Txtl */ #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Floor (Div/16)) */ /* Tua = 16*Floor (Div/16)*Txtl */ #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Ceil (Div/16)) */ /* Tua = 16*Ceil (Div/16)*Txtl */ #define UTCR3_RXE 0x00000001 /* Receive Enable */ #define UTCR3_TXE 0x00000002 /* Transmit Enable */ #define UTCR3_BRK 0x00000004 /* BReaK mode */ #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ /* more Interrupt Enable */ #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ /* Interrupt Enable */ #define UTCR3_LBM 0x00000020 /* Look-Back Mode */ #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ /* TIE, LBM can be set or cleared) */ \ (UTCR3_RXE + UTCR3_TXE) #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ /* (HP-SIR) modulation Enable */ #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ #define UTCR4_LPM 0x00000002 /* Low-Power Mode */ #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #if 0 /* Hidden receive FIFO bits */ #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ /* Service request (read) */ #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ /* more Service request (read) */ #define UTSR0_RID 0x00000004 /* Receiver IDle */ #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ #define UTSR0_REB 0x00000010 /* Receive End of Break */ #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ /* * Synchronous Data Link Controller (SDLC) control registers * * Registers * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 0 (read/write). * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 1 (read/write). * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 2 (read/write). * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 3 (read/write). * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) * Control Register 4 (read/write). * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) * Data Register (read/write). * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) * Status Register 0 (read/write). * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) * Status Register 1 (read/write). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz * or 3.5795 MHz). * fsd, Tsd Frequency, period of the SDLC communication. */ #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ #define SDCR0_LBM 0x00000004 /* Look-Back Mode */ #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ /* (GPIO [16]) */ #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ /* (GPIO [17]) */ #define SDCR1_TXE 0x00000002 /* Transmit Enable */ #define SDCR1_RXE 0x00000004 /* Receive Enable */ #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ /* more Interrupt Enable */ #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ /* Interrupt Enable */ #define SDCR1_AME 0x00000020 /* Address Match Enable */ #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ #define SDCR2_AMV Fld (8, 0) /* Address Match Value */ #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ FShft (SDCR3_BRD)) #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ FShft (SDCR4_BRD)) /* fsd = fxtl/(16*Floor (Div/16)) */ /* Tsd = 16*Floor (Div/16)*Txtl */ #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ FShft (SDCR3_BRD)) #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ FShft (SDCR4_BRD)) /* fsd = fxtl/(16*Ceil (Div/16)) */ /* Tsd = 16*Ceil (Div/16)*Txtl */ #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #if 0 /* Hidden receive FIFO bits */ #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ #define SDSR0_RAB 0x00000004 /* Receive ABort */ #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ /* Service request (read) */ #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ /* more Service request (read) */ #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ /* * High-Speed Serial to Parallel controller (HSSP) control registers * * Registers * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel * controller (HSSP) Control Register 0 (read/write). * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel * controller (HSSP) Control Register 1 (read/write). * Ser2HSDR Serial port 2 High-Speed Serial to Parallel * controller (HSSP) Data Register (read/write). * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel * controller (HSSP) Status Register 0 (read/write). * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel * controller (HSSP) Status Register 1 (read). * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel * controller (HSSP) Control Register 2 (read/write). * [The HSCR2 register is only implemented in * versions 2.0 (rev. = 8) and higher of the StrongARM * SA-1100.] */ #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */ #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */ #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */ #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */ #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */ #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */ #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ #define HSCR0_LBM 0x00000002 /* Look-Back Mode */ #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ #define HSCR0_TXE 0x00000008 /* Transmit Enable */ #define HSCR0_RXE 0x00000010 /* Receive Enable */ #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ /* more Interrupt Enable */ #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ /* Interrupt Enable */ #define HSCR0_AME 0x00000080 /* Address Match Enable */ #define HSCR1_AMV Fld (8, 0) /* Address Match Value */ #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #if 0 /* Hidden receive FIFO bits */ #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ #define HSSR0_RAB 0x00000004 /* Receive ABort */ #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ /* Service request (read) */ #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ /* more Service request (read) */ #define HSSR0_FRE 0x00000020 /* receive FRaming Error */ #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ /* (inverted) */ #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ /* (non-inverted) */ #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ /* (inverted) */ #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ /* (non-inverted) */ /* * Multi-media Communications Port (MCP) control registers * * Registers * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) * Control Register 0 (read/write). * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) * Data Register 0 (audio, read/write). * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) * Data Register 1 (telecom, read/write). * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) * Data Register 2 (CODEC registers, read/write). * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) * Status Register (read/write). * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) * Control Register 1 (read/write). * [The MCCR1 register is only implemented in * versions 2.0 (rev. = 8) and higher of the StrongARM * SA-1100.] * * Clocks * fmc, Tmc Frequency, period of the MCP communication (10 MHz, * 12 MHz, or GPIO [21]). * faud, Taud Frequency, period of the audio sampling. * ftcm, Ttcm Frequency, period of the telecom sampling. */ #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */ #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */ #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */ #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */ #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */ #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */ #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ /* [6..127] */ /* faud = fmc/(32*ASD) */ /* Taud = 32*ASD*Tmc */ #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ /* [192..4064] */ \ ((Div)/32 << FShft (MCCR0_ASD)) /* faud = fmc/(32*Floor (Div/32)) */ /* Taud = 32*Floor (Div/32)*Tmc */ #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ (((Div) + 31)/32 << FShft (MCCR0_ASD)) /* faud = fmc/(32*Ceil (Div/32)) */ /* Taud = 32*Ceil (Div/32)*Tmc */ #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ /* Divisor/32 [16..127] */ /* ftcm = fmc/(32*TSD) */ /* Ttcm = 32*TSD*Tmc */ #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ /* [512..4064] */ \ ((Div)/32 << FShft (MCCR0_TSD)) /* ftcm = fmc/(32*Floor (Div/32)) */ /* Ttcm = 32*Floor (Div/32)*Tmc */ #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ (((Div) + 31)/32 << FShft (MCCR0_TSD)) /* ftcm = fmc/(32*Ceil (Div/32)) */ /* Ttcm = 32*Ceil (Div/32)*Tmc */ #define MCCR0_MCE 0x00010000 /* MCP Enable */ #define MCCR0_ECS 0x00020000 /* External Clock Select */ #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ /* sampling/storing Mode */ #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ /* or less interrupt Enable */ #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ /* or more interrupt Enable */ #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ /* or less interrupt Enable */ #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ /* more interrupt Enable */ #define MCCR0_LBM 0x00800000 /* Look-Back Mode */ #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ (((Div) - 1) << FShft (MCCR0_ECP)) #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ /* FIFOs */ #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ /* FIFOs */ /* receive/transmit CODEC reg. */ /* FIFOs: */ #define MCDR2_DATA Fld (16, 0) /* reg. DATA */ #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ /* or less Service request (read) */ #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ /* more Service request (read) */ #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ /* or less Service request (read) */ #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ /* or more Service request (read) */ #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ /* (read) */ #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ /* (read) */ #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ /* (read) */ #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ /* (read) */ #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ /* (read) */ #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ /* (read) */ #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ /* (11.981 MHz) */ #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ /* (9.585 MHz) */ /* * Synchronous Serial Port (SSP) control registers * * Registers * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control * Register 0 (read/write). * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control * Register 1 (read/write). * [Bits SPO and SP are only implemented in versions 2.0 * (rev. = 8) and higher of the StrongARM SA-1100.] * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data * Register (read/write). * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status * Register (read/write). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz * or 3.5795 MHz). * fss, Tss Frequency, period of the SSP communication. */ #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */ #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */ #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */ #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */ #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ (((Size) - 1) << FShft (SSCR0_DSS)) #define SSCR0_FRF Fld (2, 4) /* FRame Format */ #define SSCR0_Motorola /* Motorola Serial Peripheral */ \ /* Interface (SPI) format */ \ (0 << FShft (SSCR0_FRF)) #define SSCR0_TI /* Texas Instruments Synchronous */ \ /* Serial format */ \ (1 << FShft (SSCR0_FRF)) #define SSCR0_National /* National Microwire format */ \ (2 << FShft (SSCR0_FRF)) #define SSCR0_SSE 0x00000080 /* SSP Enable */ #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ /* fss = fxtl/(2*(SCR + 1)) */ /* Tss = 2*(SCR + 1)*Txtl */ #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ (((Div) - 2)/2 << FShft (SSCR0_SCR)) /* fss = fxtl/(2*Floor (Div/2)) */ /* Tss = 2*Floor (Div/2)*Txtl */ #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ (((Div) - 1)/2 << FShft (SSCR0_SCR)) /* fss = fxtl/(2*Ceil (Div/2)) */ /* Tss = 2*Ceil (Div/2)*Txtl */ #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ /* Interrupt Enable */ #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ /* Interrupt Enable */ #define SSCR1_LBM 0x00000004 /* Look-Back Mode */ #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ /* after frame (SFRM, 1st edge) */ #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ /* after frame (SFRM, 1st edge) */ #define SSCR1_ECS 0x00000020 /* External Clock Select */ #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ /* Service request (read) */ #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ /* Service request (read) */ #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ /* * Operating System (OS) timer control registers * * Registers * OSMR0 Operating System (OS) timer Match Register 0 * (read/write). * OSMR1 Operating System (OS) timer Match Register 1 * (read/write). * OSMR2 Operating System (OS) timer Match Register 2 * (read/write). * OSMR3 Operating System (OS) timer Match Register 3 * (read/write). * OSCR Operating System (OS) timer Counter Register * (read/write). * OSSR Operating System (OS) timer Status Register * (read/write). * OWER Operating System (OS) timer Watch-dog Enable Register * (read/write). * OIER Operating System (OS) timer Interrupt Enable Register * (read/write). */ #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */ #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */ #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */ #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */ #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */ #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */ #define OSSR_M(Nb) /* Match detected [0..3] */ \ (0x00000001 << (Nb)) #define OSSR_M0 OSSR_M (0) /* Match detected 0 */ #define OSSR_M1 OSSR_M (1) /* Match detected 1 */ #define OSSR_M2 OSSR_M (2) /* Match detected 2 */ #define OSSR_M3 OSSR_M (3) /* Match detected 3 */ #define OWER_WME 0x00000001 /* Watch-dog Match Enable */ /* (set only) */ #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ (0x00000001 << (Nb)) #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ /* * Power Manager (PM) control registers * * Registers * PMCR Power Manager (PM) Control Register (read/write). * PSSR Power Manager (PM) Sleep Status Register (read/write). * PSPR Power Manager (PM) Scratch-Pad Register (read/write). * PWER Power Manager (PM) Wake-up Enable Register * (read/write). * PCFR Power Manager (PM) general ConFiguration Register * (read/write). * PPCR Power Manager (PM) Phase-Locked Loop (PLL) * Configuration Register (read/write). * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) * Sleep state Register (read/write, see GPIO pins). * POSR Power Manager (PM) Oscillator Status Register (read). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz * or 3.5795 MHz). * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). */ #define PMCR __REG(0x90020000) /* PM Control Reg. */ #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */ #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */ #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */ #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */ #define PMCR_SF 0x00000001 /* Sleep Force (set only) */ #define PSSR_SS 0x00000001 /* Software Sleep */ #define PSSR_BFS 0x00000002 /* Battery Fault Status */ /* (BATT_FAULT) */ #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ #define PSSR_DH 0x00000008 /* DRAM control Hold */ #define PSSR_PH 0x00000010 /* Peripheral control Hold */ #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ #define PCFR_FP 0x00000002 /* Float PCMCIA pins */ #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ #define PCFR_FS 0x00000004 /* Float Static memory pins */ #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ #define PCFR_FO 0x00000008 /* Force RTC oscillator */ /* (32.768 kHz) enable On */ #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ (0x00 << FShft (PPCR_CCF)) #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ (0x01 << FShft (PPCR_CCF)) #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ (0x02 << FShft (PPCR_CCF)) #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ (0x03 << FShft (PPCR_CCF)) #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ (0x04 << FShft (PPCR_CCF)) #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ (0x05 << FShft (PPCR_CCF)) #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ (0x06 << FShft (PPCR_CCF)) #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ (0x07 << FShft (PPCR_CCF)) #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ (0x08 << FShft (PPCR_CCF)) #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ (0x09 << FShft (PPCR_CCF)) #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ (0x0A << FShft (PPCR_CCF)) #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ (0x0B << FShft (PPCR_CCF)) #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ (0x0C << FShft (PPCR_CCF)) #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ (0x0D << FShft (PPCR_CCF)) #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ (0x0E << FShft (PPCR_CCF)) #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ (0x0F << FShft (PPCR_CCF)) /* 3.6864 MHz crystal (fxtl): */ #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ /* 3.5795 MHz crystal (fxtl): */ #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ /* * Reset Controller (RC) control registers * * Registers * RSRR Reset Controller (RC) Software Reset Register * (read/write). * RCSR Reset Controller (RC) Status Register (read/write). */ #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ #define RCSR __REG(0x90030004) /* RC Status Reg. */ #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ #define RCSR_HWR 0x00000001 /* HardWare Reset */ #define RCSR_SWR 0x00000002 /* SoftWare Reset */ #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ /* * Test unit control registers * * Registers * TUCR Test Unit Control Register (read/write). */ #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ #define TUCR_TIC 0x00000040 /* TIC mode */ #define TUCR_TTST 0x00000080 /* Trim TeST mode */ #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ /* Check */ #define TUCR_PMD 0x00000200 /* Power Management Disable */ #define TUCR_MR 0x00000400 /* Memory Request mode */ #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ /* grant (MBGNT) on GPIO [22:21] */ #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ (0 << FShft (TUCR_TSEL)) #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ (1 << FShft (TUCR_TSEL)) #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ (2 << FShft (TUCR_TSEL)) #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ (3 << FShft (TUCR_TSEL)) #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ /* Clocks on GPIO [26:27] */ \ (4 << FShft (TUCR_TSEL)) #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ /* (Alternative) */ \ (5 << FShft (TUCR_TSEL)) #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ (6 << FShft (TUCR_TSEL)) #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ (7 << FShft (TUCR_TSEL)) /* * General-Purpose Input/Output (GPIO) control registers * * Registers * GPLR General-Purpose Input/Output (GPIO) Pin Level * Register (read). * GPDR General-Purpose Input/Output (GPIO) Pin Direction * Register (read/write). * GPSR General-Purpose Input/Output (GPIO) Pin output Set * Register (write). * GPCR General-Purpose Input/Output (GPIO) Pin output Clear * Register (write). * GRER General-Purpose Input/Output (GPIO) Rising-Edge * detect Register (read/write). * GFER General-Purpose Input/Output (GPIO) Falling-Edge * detect Register (read/write). * GEDR General-Purpose Input/Output (GPIO) Edge Detect * status Register (read/write). * GAFR General-Purpose Input/Output (GPIO) Alternate * Function Register (read/write). * * Clock * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). */ #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */ #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */ #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */ #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */ #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */ #define GPIO_MIN (0) #define GPIO_MAX (27) #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ (0x00000001 << (Nb)) #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ GPIO_GPIO ((Nb) - 6) #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ /* ser. port 4: */ #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ /* ser. port 1: */ #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ /* ser. port 4: */ #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ /* ser. port 3: */ #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ /* ser. port 4: */ #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ /* test controller: */ #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ #define GPDR_In 0 /* Input */ #define GPDR_Out 1 /* Output */ /* * Interrupt Controller (IC) control registers * * Registers * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) * Pending register (read). * ICMR Interrupt Controller (IC) Mask Register (read/write). * ICLR Interrupt Controller (IC) Level Register (read/write). * ICCR Interrupt Controller (IC) Control Register * (read/write). * [The ICCR register is only implemented in versions 2.0 * (rev. = 8) and higher of the StrongARM SA-1100.] * ICFP Interrupt Controller (IC) Fast Interrupt reQuest * (FIQ) Pending register (read). * ICPR Interrupt Controller (IC) Pending Register (read). * [The ICPR register is active low (inverted) in * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the * StrongARM SA-1100, it is active high (non-inverted) in * versions 2.0 (rev. = 8) and higher.] */ #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */ #define ICMR __REG(0x90050004) /* IC Mask Reg. */ #define ICLR __REG(0x90050008) /* IC Level Reg. */ #define ICCR __REG(0x9005000C) /* IC Control Reg. */ #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */ #define ICPR __REG(0x90050020) /* IC Pending Reg. */ #define IC_GPIO(Nb) /* GPIO [0..10] */ \ (0x00000001 << (Nb)) #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ #define IC_LCD 0x00001000 /* LCD controller */ #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ (0x00100000 << (Nb)) #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ #define IC_OST(Nb) /* OS Timer match [0..3] */ \ (0x04000000 << (Nb)) #define IC_OST0 IC_OST (0) /* OS Timer match 0 */ #define IC_OST1 IC_OST (1) /* OS Timer match 1 */ #define IC_OST2 IC_OST (2) /* OS Timer match 2 */ #define IC_OST3 IC_OST (3) /* OS Timer match 3 */ #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ #define IC_RTCAlrm 0x80000000 /* RTC Alarm */ #define ICLR_IRQ 0 /* Interrupt ReQuest */ #define ICLR_FIQ 1 /* Fast Interrupt reQuest */ #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ /* Mask */ #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ /* (ICMR ignored) */ #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ /* enable (ICMR used) */ /* * Peripheral Pin Controller (PPC) control registers * * Registers * PPDR Peripheral Pin Controller (PPC) Pin Direction * Register (read/write). * PPSR Peripheral Pin Controller (PPC) Pin State Register * (read/write). * PPAR Peripheral Pin Controller (PPC) Pin Assignment * Register (read/write). * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin * Direction Register (read/write). * PPFR Peripheral Pin Controller (PPC) Pin Flag Register * (read). */ #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */ #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */ #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */ #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */ #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */ #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ (0x00000001 << (Nb)) #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ /* ser. port 1: */ #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ /* ser. port 2: */ #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ /* ser. port 3: */ #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ /* ser. port 4: */ #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ #define PPDR_In 0 /* Input */ #define PPDR_Out 1 /* Output */ /* ser. port 1: */ #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ /* ser. port 4: */ #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ /* & SFRM_C */ #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ #define PSDR_OutL 0 /* Output Low in sleep mode */ #define PSDR_Flt 1 /* Floating (input) in sleep mode */ #define PPFR_LCD 0x00000001 /* LCD controller */ #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ #define PPFR_PerEn 0 /* Peripheral Enabled */ #define PPFR_PPCEn 1 /* PPC Enabled */ /* * Dynamic Random-Access Memory (DRAM) control registers * * Registers * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) * CoNFiGuration register (read/write). * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) * Column Address Strobe (CAS) shift register 0 * (read/write). * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) * Column Address Strobe (CAS) shift register 1 * (read/write). * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) * Column Address Strobe (CAS) shift register 2 * (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). * fcas, Tcas Frequency, period of the DRAM CAS shift registers. */ #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ /* SA1100 MDCNFG values */ #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ (0x00000001 << (Nb)) #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ (((Add) - 9) << FShft (MDCNFG_DRAC)) #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ /* (fcas = fcpu/2) */ #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ ((Tcpu) << FShft (MDCNFG_TDL)) #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ /* [Tmem] */ #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ /* [0..262136 Tcpu] */ \ ((Tcpu)/8 << FShft (MDCNFG_DRI)) /* SA1110 MDCNFG values */ #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ /* bank 0/1 */ #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ /* bank 0/1 */ #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ /* * Static memory control registers * * Registers * MSC0 Memory system: Static memory Control register 0 * (read/write). * MSC1 Memory system: Static memory Control register 1 * (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). */ #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */ #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ Fld (16, ((Nb) Modulo 2)*16) #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ #define MSC_RT Fld (2, 0) /* ROM/static memory Type */ #define MSC_NonBrst /* Non-Burst static memory */ \ (0 << FShft (MSC_RT)) #define MSC_SRAM /* 32-bit byte-writable SRAM */ \ (1 << FShft (MSC_RT)) #define MSC_Brst4 /* Burst-of-4 static memory */ \ (2 << FShft (MSC_RT)) #define MSC_Brst8 /* Burst-of-8 static memory */ \ (3 << FShft (MSC_RT)) #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ /* First access - 1(.5) [Tmem] */ #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ /* static memory) [3..65 Tcpu] */ \ ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ /* Next access - 1 [Tmem] */ #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ /* time/2 [Tmem] */ #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ (((Tcpu)/4) << FShft (MSC_RRR)) #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) /* * Personal Computer Memory Card International Association (PCMCIA) control * register * * Register * MECR Memory system: Expansion memory bus (PCMCIA) * Configuration Register (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). */ /* Memory system: */ #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */ #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ Fld (15, (Nb)*16) #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ /* [Tmem] */ #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) /* * On SA1110 only */ #define MDREFR __REG(0xA000001C) #define MDREFR_TRASR Fld (4, 0) #define MDREFR_DRI Fld (12, 4) #define MDREFR_E0PIN (1 << 16) #define MDREFR_K0RUN (1 << 17) #define MDREFR_K0DB2 (1 << 18) #define MDREFR_E1PIN (1 << 20) #define MDREFR_K1RUN (1 << 21) #define MDREFR_K1DB2 (1 << 22) #define MDREFR_K2RUN (1 << 25) #define MDREFR_K2DB2 (1 << 26) #define MDREFR_EAPD (1 << 28) #define MDREFR_KAPD (1 << 29) #define MDREFR_SLFRSH (1 << 31) /* * Direct Memory Access (DMA) control registers */ #define DMA_SIZE (6 * 0x20) #define DMA_PHYS 0xb0000000 /* * Liquid Crystal Display (LCD) control registers * * Registers * LCCR0 Liquid Crystal Display (LCD) Control Register 0 * (read/write). * [Bits LDM, BAM, and ERM are only implemented in * versions 2.0 (rev. = 8) and higher of the StrongARM * SA-1100.] * LCSR Liquid Crystal Display (LCD) Status Register * (read/write). * [Bit LDD can be only read in versions 1.0 (rev. = 1) * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be * read and written (cleared) in versions 2.0 (rev. = 8) * and higher.] * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access * (DMA) Base Address Register channel 1 (read/write). * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access * (DMA) Current Address Register channel 1 (read). * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access * (DMA) Base Address Register channel 2 (read/write). * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access * (DMA) Current Address Register channel 2 (read). * LCCR1 Liquid Crystal Display (LCD) Control Register 1 * (read/write). * [The LCCR1 register can be only written in * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the * StrongARM SA-1100, it can be written and read in * versions 2.0 (rev. = 8) and higher.] * LCCR2 Liquid Crystal Display (LCD) Control Register 2 * (read/write). * [The LCCR1 register can be only written in * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the * StrongARM SA-1100, it can be written and read in * versions 2.0 (rev. = 8) and higher.] * LCCR3 Liquid Crystal Display (LCD) Control Register 3 * (read/write). * [The LCCR1 register can be only written in * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the * StrongARM SA-1100, it can be written and read in * versions 2.0 (rev. = 8) and higher. Bit PCP is only * implemented in versions 2.0 (rev. = 8) and higher of * the StrongARM SA-1100.] * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). * fpix, Tpix Frequency, period of the pixel clock. * fln, Tln Frequency, period of the line clock. * fac, Tac Frequency, period of the AC bias clock. */ #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ /* [byte] */ \ (16*LCD_PEntrySp) #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ /* [byte] */ \ (256*LCD_PEntrySp) #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ /* dummy-Palette Space [byte] */ \ (16*LCD_PEntrySp) #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ #define LCD_4Bit /* LCD 4-Bit pixel mode */ \ (0 << FShft (LCD_PBS)) #define LCD_8Bit /* LCD 8-Bit pixel mode */ \ (1 << FShft (LCD_PBS)) #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ (2 << FShft (LCD_PBS)) #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ /* (Alternative) */ #define LCCR0_LEN 0x00000001 /* LCD ENable */ #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ /* Select */ #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ /* interrupt Mask (disable) */ #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ /* interrupt Mask (disable) */ #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ /* IUU, OOL, OUL, OOU, and OUU) */ /* interrupt Mask (disable) */ #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ /* display mode) */ #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ /* display */ #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ /* display */ #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ /* [Tmem] */ #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ /* [0..510 Tcpu] */ \ ((Tcpu)/2 << FShft (LCCR0_PDD)) #define LCSR_LDD 0x00000001 /* LCD Disable Done */ #define LCSR_BAU 0x00000002 /* Base Address Update (read) */ #define LCSR_BER 0x00000004 /* Bus ERror */ #define LCSR_ABC 0x00000008 /* AC Bias clock Count */ #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ /* panel */ #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ /* panel */ #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ /* panel */ #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ /* panel */ #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ /* panel */ #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ /* panel */ #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ /* panel */ #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ /* panel */ #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ /* pulse Width - 1 [Tpix] (L_LCLK) */ #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ /* pulse Width [1..64 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_HSW)) #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ /* count - 1 [Tpix] */ #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ /* [1..256 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_ELW)) #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ /* Wait count - 1 [Tpix] */ #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ /* [1..256 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_BLW)) #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ (((Line) - 1) << FShft (LCCR2_LPP)) #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ /* Width - 1 [Tln] (L_FCLK) */ #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ /* Width [1..64 Tln] */ \ (((Tln) - 1) << FShft (LCCR2_VSW)) #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ /* count [Tln] */ #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_EFW)) #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ /* Wait count [Tln] */ #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_BFW)) #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ /* [1..255] (L_PCLK) */ /* fpix = fcpu/(2*(PCD + 2)) */ /* Tpix = 2*(PCD + 2)*Tcpu */ #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ (((Div) - 4)/2 << FShft (LCCR3_PCD)) /* fpix = fcpu/(2*Floor (Div/2)) */ /* Tpix = 2*Floor (Div/2)*Tcpu */ #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ (((Div) - 3)/2 << FShft (LCCR3_PCD)) /* fpix = fcpu/(2*Ceil (Div/2)) */ /* Tpix = 2*Ceil (Div/2)*Tcpu */ #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ /* [Tln] (L_BIAS) */ #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ (((Div) - 2)/2 << FShft (LCCR3_ACB)) /* fac = fln/(2*Floor (Div/2)) */ /* Tac = 2*Floor (Div/2)*Tln */ #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ (((Div) - 1)/2 << FShft (LCCR3_ACB)) /* fac = fln/(2*Ceil (Div/2)) */ /* Tac = 2*Ceil (Div/2)*Tln */ #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ /* Interrupt */ #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ /* Off */ \ (0 << FShft (LCCR3_API)) #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ /* [1..15] */ \ ((Trans) << FShft (LCCR3_API)) #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ /* Polarity (L_FCLK) */ #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ /* active High */ #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ /* active Low */ #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ /* pulse Polarity (L_LCLK) */ #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ /* pulse active High */ #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ /* pulse active Low */ #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ /* active display mode) */ #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ PK ! ���% % memory.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-sa1100/include/mach/memory.h * * Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net> */ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H #include <linux/sizes.h> /* * Because of the wide memory address space between physical RAM banks on the * SA1100, it's much convenient to use Linux's SparseMEM support to implement * our memory map representation. Assuming all memory nodes have equal access * characteristics, we then have generic discontiguous memory support. * * The sparsemem banks are matched with the physical memory bank addresses * which are incidentally the same as virtual addresses. * * node 0: 0xc0000000 - 0xc7ffffff * node 1: 0xc8000000 - 0xcfffffff * node 2: 0xd0000000 - 0xd7ffffff * node 3: 0xd8000000 - 0xdfffffff */ #define MAX_PHYSMEM_BITS 32 #define SECTION_SIZE_BITS 27 /* * Cache flushing area - SA1100 zero bank */ #define FLUSH_BASE_PHYS 0xe0000000 #define FLUSH_BASE 0xf5000000 #define FLUSH_BASE_MINICACHE 0xf5100000 #endif PK ! #�bL L assabet.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-sa1100/include/mach/assabet.h * * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net> * * This file contains the hardware specific definitions for Assabet * Only include this file from SA1100-specific files. * * 2000/05/23 John Dorsey <john+@cs.cmu.edu> * Definitions for Neponset added. */ #ifndef __ASM_ARCH_ASSABET_H #define __ASM_ARCH_ASSABET_H /* System Configuration Register flags */ #define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */ #define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */ #define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */ #define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */ #define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */ #define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */ #define ASSABET_SCR_INIT -1 extern unsigned long SCR_value; #ifdef CONFIG_ASSABET_NEPONSET #define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0) #else #define machine_has_neponset() (0) #endif /* Board Control Register */ #define ASSABET_BCR_BASE 0xf1000000 #define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE)) #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ #define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ #define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ #define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ #define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */ #define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */ #define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */ #define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */ #define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */ #define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */ #define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */ #define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */ #define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */ #define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */ #define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */ #define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */ #define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */ #define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */ #define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */ #define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */ #define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */ #define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */ #ifdef CONFIG_SA1100_ASSABET extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); #else #define ASSABET_BCR_frob(x,y) do { } while (0) #endif extern void assabet_uda1341_reset(int set); #define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) #define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) #define ASSABET_BSR_BASE 0xf1000000 #define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE)) #define ASSABET_BSR_RS232_VALID (1 << 24) #define ASSABET_BSR_COM_DCD (1 << 25) #define ASSABET_BSR_COM_CTS (1 << 26) #define ASSABET_BSR_COM_DSR (1 << 27) #define ASSABET_BSR_RAD_CTS (1 << 28) #define ASSABET_BSR_RAD_DSR (1 << 29) #define ASSABET_BSR_RAD_DCD (1 << 30) #define ASSABET_BSR_RAD_RI (1 << 31) /* GPIOs (bitmasks) for which the generic definition doesn't say much */ #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ #endif PK ! �}��* * jornada720.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-sa1100/include/mach/jornada720.h * * SSP/MCU communication definitions for HP Jornada 710/720/728 * * Copyright 2007,2008 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> * Copyright 2000 John Ankcorn <jca@lcs.mit.edu> */ /* HP Jornada 7xx microprocessor commands */ #define GETBATTERYDATA 0xc0 #define GETSCANKEYCODE 0x90 #define GETTOUCHSAMPLES 0xa0 #define GETCONTRAST 0xD0 #define SETCONTRAST 0xD1 #define GETBRIGHTNESS 0xD2 #define SETBRIGHTNESS 0xD3 #define CONTRASTOFF 0xD8 #define BRIGHTNESSOFF 0xD9 #define PWMOFF 0xDF #define TXDUMMY 0x11 #define ERRORCODE 0x00 extern void jornada_ssp_start(void); extern void jornada_ssp_end(void); extern int jornada_ssp_inout(u8 byte); extern int jornada_ssp_byte(u8 byte); PK ! #�I reset.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_RESET_H #define __ASM_ARCH_RESET_H #include "hardware.h" #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ #define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */ #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ #define RESET_STATUS_ALL (0xf) extern unsigned int reset_status; static inline void clear_reset_status(unsigned int mask) { RCSR = mask; } #endif /* __ASM_ARCH_RESET_H */ PK ! ��)X� � cerf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-sa1100/include/mach/cerf.h * * Apr-2003 : Removed some old PDA crud [FB] */ #ifndef _INCLUDE_CERF_H_ #define _INCLUDE_CERF_H_ #define CERF_ETH_IO 0xf0000000 #define CERF_ETH_IRQ IRQ_GPIO26 #define CERF_GPIO_CF_BVD2 19 #define CERF_GPIO_CF_BVD1 20 #define CERF_GPIO_CF_RESET 21 #define CERF_GPIO_CF_IRQ 22 #define CERF_GPIO_CF_CD 23 #endif // _INCLUDE_CERF_H_ PK ! ��M M badge4.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-sa1100/include/mach/badge4.h * * Tim Connors <connors@hpl.hp.com> * Christopher Hoover <ch@hpl.hp.com> * * Copyright (C) 2002 Hewlett-Packard Company */ #ifndef __ASM_ARCH_HARDWARE_H #error "include <mach/hardware.h> instead" #endif #define BADGE4_SA1111_BASE (0x48000000) /* GPIOs on the BadgePAD 4 */ #define BADGE4_GPIO_INT_1111 GPIO_GPIO0 /* SA-1111 IRQ */ #define BADGE4_GPIO_INT_VID GPIO_GPIO1 /* Video expansion */ #define BADGE4_GPIO_LGP2 GPIO_GPIO2 /* GPIO_LDD8 */ #define BADGE4_GPIO_LGP3 GPIO_GPIO3 /* GPIO_LDD9 */ #define BADGE4_GPIO_LGP4 GPIO_GPIO4 /* GPIO_LDD10 */ #define BADGE4_GPIO_LGP5 GPIO_GPIO5 /* GPIO_LDD11 */ #define BADGE4_GPIO_LGP6 GPIO_GPIO6 /* GPIO_LDD12 */ #define BADGE4_GPIO_LGP7 GPIO_GPIO7 /* GPIO_LDD13 */ #define BADGE4_GPIO_LGP8 GPIO_GPIO8 /* GPIO_LDD14 */ #define BADGE4_GPIO_LGP9 GPIO_GPIO9 /* GPIO_LDD15 */ #define BADGE4_GPIO_GPA_VID GPIO_GPIO10 /* Video expansion */ #define BADGE4_GPIO_GPB_VID GPIO_GPIO11 /* Video expansion */ #define BADGE4_GPIO_GPC_VID GPIO_GPIO12 /* Video expansion */ #define BADGE4_GPIO_UART_HS1 GPIO_GPIO13 #define BADGE4_GPIO_UART_HS2 GPIO_GPIO14 #define BADGE4_GPIO_MUXSEL0 GPIO_GPIO15 #define BADGE4_GPIO_TESTPT_J7 GPIO_GPIO16 #define BADGE4_GPIO_SDSDA GPIO_GPIO17 /* SDRAM SPD Data */ #define BADGE4_GPIO_SDSCL GPIO_GPIO18 /* SDRAM SPD Clock */ #define BADGE4_GPIO_SDTYP0 GPIO_GPIO19 /* SDRAM Type Control */ #define BADGE4_GPIO_SDTYP1 GPIO_GPIO20 /* SDRAM Type Control */ #define BADGE4_GPIO_BGNT_1111 GPIO_GPIO21 /* GPIO_MBGNT */ #define BADGE4_GPIO_BREQ_1111 GPIO_GPIO22 /* GPIO_TREQA */ #define BADGE4_GPIO_TESTPT_J6 GPIO_GPIO23 #define BADGE4_GPIO_PCMEN5V GPIO_GPIO24 /* 5V power */ #define BADGE4_GPIO_SA1111_NRST GPIO_GPIO25 /* SA-1111 nRESET */ #define BADGE4_GPIO_TESTPT_J5 GPIO_GPIO26 #define BADGE4_GPIO_CLK_1111 GPIO_GPIO27 /* GPIO_32_768kHz */ /* Interrupts on the BadgePAD 4 */ #define BADGE4_IRQ_GPIO_SA1111 IRQ_GPIO0 /* SA-1111 interrupt */ /* PCM5ENV Usage tracking */ #define BADGE4_5V_PCMCIA_SOCK0 (1<<0) #define BADGE4_5V_PCMCIA_SOCK1 (1<<1) #define BADGE4_5V_PCMCIA_SOCK(n) (1<<(n)) #define BADGE4_5V_USB (1<<2) #define BADGE4_5V_INITIALLY (1<<3) #ifndef __ASSEMBLY__ extern void badge4_set_5V(unsigned subsystem, int on); #endif PK ! E��7 simpad.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-sa1100/include/mach/simpad.h * * based of assabet.h same as HUW_Webpanel * * This file contains the hardware specific definitions for SIMpad * * 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch> */ #ifndef __ASM_ARCH_SIMPAD_H #define __ASM_ARCH_SIMPAD_H #define GPIO_UART1_RTS GPIO_GPIO14 #define GPIO_UART1_DTR GPIO_GPIO7 #define GPIO_UART1_CTS GPIO_GPIO8 #define GPIO_UART1_DCD GPIO_GPIO23 #define GPIO_UART1_DSR GPIO_GPIO6 #define GPIO_UART3_RTS GPIO_GPIO12 #define GPIO_UART3_DTR GPIO_GPIO16 #define GPIO_UART3_CTS GPIO_GPIO13 #define GPIO_UART3_DCD GPIO_GPIO18 #define GPIO_UART3_DSR GPIO_GPIO17 #define GPIO_POWER_BUTTON GPIO_GPIO0 #define GPIO_UCB1300_IRQ GPIO_GPIO22 /* UCB GPIO and touchscreen */ #define IRQ_UART1_CTS IRQ_GPIO15 #define IRQ_UART1_DCD GPIO_GPIO23 #define IRQ_UART1_DSR GPIO_GPIO6 #define IRQ_UART3_CTS GPIO_GPIO13 #define IRQ_UART3_DCD GPIO_GPIO18 #define IRQ_UART3_DSR GPIO_GPIO17 #define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22 #define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0 /*--- PCMCIA ---*/ #define GPIO_CF_CD 24 #define GPIO_CF_IRQ 1 /*--- SmartCard ---*/ #define GPIO_SMART_CARD GPIO_GPIO10 #define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 /*--- ucb1x00 GPIO ---*/ #define SIMPAD_UCB1X00_GPIO_BASE (GPIO_MAX + 1) #define SIMPAD_UCB1X00_GPIO_PROG1 (SIMPAD_UCB1X00_GPIO_BASE) #define SIMPAD_UCB1X00_GPIO_PROG2 (SIMPAD_UCB1X00_GPIO_BASE + 1) #define SIMPAD_UCB1X00_GPIO_UP (SIMPAD_UCB1X00_GPIO_BASE + 2) #define SIMPAD_UCB1X00_GPIO_DOWN (SIMPAD_UCB1X00_GPIO_BASE + 3) #define SIMPAD_UCB1X00_GPIO_LEFT (SIMPAD_UCB1X00_GPIO_BASE + 4) #define SIMPAD_UCB1X00_GPIO_RIGHT (SIMPAD_UCB1X00_GPIO_BASE + 5) #define SIMPAD_UCB1X00_GPIO_6 (SIMPAD_UCB1X00_GPIO_BASE + 6) #define SIMPAD_UCB1X00_GPIO_7 (SIMPAD_UCB1X00_GPIO_BASE + 7) #define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8) #define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9) /*--- CS3 Latch ---*/ #define SIMPAD_CS3_GPIO_BASE (GPIO_MAX + 11) #define SIMPAD_CS3_VCC_5V_EN (SIMPAD_CS3_GPIO_BASE) #define SIMPAD_CS3_VCC_3V_EN (SIMPAD_CS3_GPIO_BASE + 1) #define SIMPAD_CS3_EN1 (SIMPAD_CS3_GPIO_BASE + 2) #define SIMPAD_CS3_EN0 (SIMPAD_CS3_GPIO_BASE + 3) #define SIMPAD_CS3_DISPLAY_ON (SIMPAD_CS3_GPIO_BASE + 4) #define SIMPAD_CS3_PCMCIA_BUFF_DIS (SIMPAD_CS3_GPIO_BASE + 5) #define SIMPAD_CS3_MQ_RESET (SIMPAD_CS3_GPIO_BASE + 6) #define SIMPAD_CS3_PCMCIA_RESET (SIMPAD_CS3_GPIO_BASE + 7) #define SIMPAD_CS3_DECT_POWER_ON (SIMPAD_CS3_GPIO_BASE + 8) #define SIMPAD_CS3_IRDA_SD (SIMPAD_CS3_GPIO_BASE + 9) #define SIMPAD_CS3_RS232_ON (SIMPAD_CS3_GPIO_BASE + 10) #define SIMPAD_CS3_SD_MEDIAQ (SIMPAD_CS3_GPIO_BASE + 11) #define SIMPAD_CS3_LED2_ON (SIMPAD_CS3_GPIO_BASE + 12) #define SIMPAD_CS3_IRDA_MODE (SIMPAD_CS3_GPIO_BASE + 13) #define SIMPAD_CS3_ENABLE_5V (SIMPAD_CS3_GPIO_BASE + 14) #define SIMPAD_CS3_RESET_SIMCARD (SIMPAD_CS3_GPIO_BASE + 15) #define SIMPAD_CS3_PCMCIA_BVD1 (SIMPAD_CS3_GPIO_BASE + 16) #define SIMPAD_CS3_PCMCIA_BVD2 (SIMPAD_CS3_GPIO_BASE + 17) #define SIMPAD_CS3_PCMCIA_VS1 (SIMPAD_CS3_GPIO_BASE + 18) #define SIMPAD_CS3_PCMCIA_VS2 (SIMPAD_CS3_GPIO_BASE + 19) #define SIMPAD_CS3_LOCK_IND (SIMPAD_CS3_GPIO_BASE + 20) #define SIMPAD_CS3_CHARGING_STATE (SIMPAD_CS3_GPIO_BASE + 21) #define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22) #define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23) #define CS3_BASE IOMEM(0xf1000000) long simpad_get_cs3_ro(void); long simpad_get_cs3_shadow(void); void simpad_set_cs3_bit(int value); void simpad_clear_cs3_bit(int value); #define VCC_5V_EN 0x0001 /* For 5V PCMCIA */ #define VCC_3V_EN 0x0002 /* FOR 3.3V PCMCIA */ #define EN1 0x0004 /* This is only for EPROM's */ #define EN0 0x0008 /* Both should be enable for 3.3V or 5V */ #define DISPLAY_ON 0x0010 #define PCMCIA_BUFF_DIS 0x0020 #define MQ_RESET 0x0040 #define PCMCIA_RESET 0x0080 #define DECT_POWER_ON 0x0100 #define IRDA_SD 0x0200 /* Shutdown for powersave */ #define RS232_ON 0x0400 #define SD_MEDIAQ 0x0800 /* Shutdown for powersave */ #define LED2_ON 0x1000 #define IRDA_MODE 0x2000 /* Fast/Slow IrDA mode */ #define ENABLE_5V 0x4000 /* Enable 5V circuit */ #define RESET_SIMCARD 0x8000 #define PCMCIA_BVD1 0x01 #define PCMCIA_BVD2 0x02 #define PCMCIA_VS1 0x04 #define PCMCIA_VS2 0x08 #define LOCK_IND 0x10 #define CHARGING_STATE 0x20 #define PCMCIA_SHORT 0x40 /*--- Battery ---*/ struct simpad_battery { unsigned char ac_status; /* line connected yes/no */ unsigned char status; /* battery loading yes/no */ unsigned char percentage; /* percentage loaded */ unsigned short life; /* life till empty */ }; /* These should match the apm_bios.h definitions */ #define SIMPAD_AC_STATUS_AC_OFFLINE 0x00 #define SIMPAD_AC_STATUS_AC_ONLINE 0x01 #define SIMPAD_AC_STATUS_AC_BACKUP 0x02 /* What does this mean? */ #define SIMPAD_AC_STATUS_AC_UNKNOWN 0xff /* These bitfields are rarely "or'd" together */ #define SIMPAD_BATT_STATUS_HIGH 0x01 #define SIMPAD_BATT_STATUS_LOW 0x02 #define SIMPAD_BATT_STATUS_CRITICAL 0x04 #define SIMPAD_BATT_STATUS_CHARGING 0x08 #define SIMPAD_BATT_STATUS_CHARGE_MAIN 0x10 #define SIMPAD_BATT_STATUS_DEAD 0x20 /* Battery will not charge */ #define SIMPAD_BATT_NOT_INSTALLED 0x20 /* For expansion pack batteries */ #define SIMPAD_BATT_STATUS_FULL 0x40 /* Battery fully charged (and connected to AC) */ #define SIMPAD_BATT_STATUS_NOBATT 0x80 #define SIMPAD_BATT_STATUS_UNKNOWN 0xff extern int simpad_get_battery(struct simpad_battery* ); #endif // __ASM_ARCH_SIMPAD_H PK ! �˝�x x shannon.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _INCLUDE_SHANNON_H #define _INCLUDE_SHANNON_H /* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, * written by <forsyth@vitanuova.com> */ #define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ #define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ /* lcd lower = GPIO 2-9 */ #define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ #define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ #define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ #define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ #define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ #define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 #define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ #define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ #define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 #define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ #define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ #define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ #define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ #define SHANNON_GPIO_DISP_EN 22 /* out */ /* XXX GPIO 23 unaccounted for */ #define SHANNON_GPIO_EJECT_0 24 /* in */ #define SHANNON_GPIO_EJECT_1 25 /* in */ #define SHANNON_GPIO_RDY_0 26 /* in */ #define SHANNON_GPIO_RDY_1 27 /* in */ /* MCP UCB codec GPIO pins... */ #define SHANNON_UCB_GPIO_BACKLIGHT 9 #define SHANNON_UCB_GPIO_BRIGHT_MASK 7 #define SHANNON_UCB_GPIO_BRIGHT 6 #define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f #define SHANNON_UCB_GPIO_CONTRAST 0 #endif PK ! �+=`� � collie.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-sa1100/include/mach/collie.h * * This file contains the hardware specific definitions for Collie * Only include this file from SA1100-specific files. * * ChangeLog: * 04-06-2001 Lineo Japan, Inc. * 04-16-2001 SHARP Corporation * 07-07-2002 Chris Larson <clarson@digi.com> * */ #ifndef __ASM_ARCH_COLLIE_H #define __ASM_ARCH_COLLIE_H #include "hardware.h" /* Gives GPIO_MAX */ extern void locomolcd_power(int on); #define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) #define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0) #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 #define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7) #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 #define COLLIE_SCOOP_IO_DIR (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \ COLLIE_SCP_LB_VOL_CHG) #define COLLIE_SCOOP_IO_OUT (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R) /* GPIOs for gpiolib */ #define COLLIE_GPIO_ON_KEY (0) #define COLLIE_GPIO_AC_IN (1) #define COLLIE_GPIO_SDIO_INT (11) #define COLLIE_GPIO_CF_IRQ (14) #define COLLIE_GPIO_nREMOCON_INT (15) #define COLLIE_GPIO_UCB1x00_RESET (16) #define COLLIE_GPIO_nMIC_ON (17) #define COLLIE_GPIO_nREMOCON_ON (18) #define COLLIE_GPIO_CO (20) #define COLLIE_GPIO_MCP_CLK (21) #define COLLIE_GPIO_CF_CD (22) #define COLLIE_GPIO_UCB1x00_IRQ (23) #define COLLIE_GPIO_WAKEUP (24) #define COLLIE_GPIO_GA_INT (25) #define COLLIE_GPIO_MAIN_BAT_LOW (26) /* GPIO definitions for direct register access */ #define _COLLIE_GPIO_ON_KEY GPIO_GPIO(0) #define _COLLIE_GPIO_AC_IN GPIO_GPIO(1) #define _COLLIE_GPIO_nREMOCON_INT GPIO_GPIO(15) #define _COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO(16) #define _COLLIE_GPIO_nMIC_ON GPIO_GPIO(17) #define _COLLIE_GPIO_nREMOCON_ON GPIO_GPIO(18) #define _COLLIE_GPIO_CO GPIO_GPIO(20) #define _COLLIE_GPIO_WAKEUP GPIO_GPIO(24) /* Interrupts */ #define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0 #define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1 #define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11 #define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14 #define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15 #define COLLIE_IRQ_GPIO_CO IRQ_GPIO20 #define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22 #define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23 #define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24 #define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25 #define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26 /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ #define COLLIE_TC35143_GPIO_BASE (GPIO_MAX + 13) #define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 #define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 #define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 #define COLLIE_GPIO_IR_ON (COLLIE_TC35143_GPIO_BASE + 3) #define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 #define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 #define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 #define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 #define COLLIE_GPIO_MBAT_ON (COLLIE_TC35143_GPIO_BASE + 7) #define COLLIE_GPIO_BBAT_ON (COLLIE_TC35143_GPIO_BASE + 8) #define COLLIE_GPIO_TMP_ON (COLLIE_TC35143_GPIO_BASE + 9) #define COLLIE_TC35143_GPIO_IN (UCB_IO_0 | UCB_IO_2 | UCB_IO_5) #define COLLIE_TC35143_GPIO_OUT (UCB_IO_1 | UCB_IO_3 | UCB_IO_4 \ | UCB_IO_6) #endif PK ! �8� generic.hnu �[��� #include "../../generic.h" PK ! �*��� � serial.hnu �[��� /* * Copyright (C) 2009 Texas Instruments * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /* OMAP2 serial ports */ #define OMAP2_UART1_BASE 0x4806a000 #define OMAP2_UART2_BASE 0x4806c000 #define OMAP2_UART3_BASE 0x4806e000 /* OMAP3 serial ports */ #define OMAP3_UART1_BASE OMAP2_UART1_BASE #define OMAP3_UART2_BASE OMAP2_UART2_BASE #define OMAP3_UART3_BASE 0x49020000 #define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */ #define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */ /* OMAP4 serial ports */ #define OMAP4_UART1_BASE OMAP2_UART1_BASE #define OMAP4_UART2_BASE OMAP2_UART2_BASE #define OMAP4_UART3_BASE 0x48020000 #define OMAP4_UART4_BASE 0x4806e000 /* TI81XX serial ports */ #define TI81XX_UART1_BASE 0x48020000 #define TI81XX_UART2_BASE 0x48022000 #define TI81XX_UART3_BASE 0x48024000 /* AM3505/3517 UART4 */ #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ /* AM33XX serial port */ #define AM33XX_UART1_BASE 0x44E09000 /* OMAP5 serial ports */ #define OMAP5_UART1_BASE OMAP2_UART1_BASE #define OMAP5_UART2_BASE OMAP2_UART2_BASE #define OMAP5_UART3_BASE OMAP4_UART3_BASE #define OMAP5_UART4_BASE OMAP4_UART4_BASE #define OMAP5_UART5_BASE 0x48066000 #define OMAP5_UART6_BASE 0x48068000 /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 #define OMAP_PORT_SHIFT 2 #define ZOOM_PORT_SHIFT 1 #define OMAP24XX_BASE_BAUD (48000000/16) #ifndef __ASSEMBLER__ struct omap_board_data; struct omap_uart_port_info; extern void omap_serial_init(void); extern void omap_serial_board_init(struct omap_uart_port_info *platform_data); extern void omap_serial_init_port(struct omap_board_data *bdata, struct omap_uart_port_info *platform_data); #endif PK ! �/�� � se.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HITACHI_SE_H #define __ASM_SH_HITACHI_SE_H /* * linux/include/asm-sh/hitachi_se.h * * Copyright (C) 2000 Kazumoto Kojima * * Hitachi SolutionEngine support */ #include <linux/sh_intc.h> /* Box specific addresses. */ #define PA_ROM 0x00000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0x01000000 /* EPROM */ #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_EXT1 0x04000000 #define PA_EXT1_SIZE 0x04000000 #define PA_EXT2 0x08000000 #define PA_EXT2_SIZE 0x04000000 #define PA_SDRAM 0x0c000000 #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0x12000000 #define PA_EXT4_SIZE 0x02000000 #define PA_EXT5 0x14000000 #define PA_EXT5_SIZE 0x04000000 #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ #define PA_83902 0xb0000000 /* DP83902A */ #define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ #define PA_83902_RST 0xb0080000 /* DP83902A reset port */ #define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ #define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ #define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ #define PA_LED 0xb0c00000 /* LED */ #if defined(CONFIG_CPU_SUBTYPE_SH7705) #define PA_BCR 0xb0e00000 #else #define PA_BCR 0xb1400000 /* FPGA */ #endif #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define BCR_ILCRA (PA_BCR + 0) #define BCR_ILCRB (PA_BCR + 2) #define BCR_ILCRC (PA_BCR + 4) #define BCR_ILCRD (PA_BCR + 6) #define BCR_ILCRE (PA_BCR + 8) #define BCR_ILCRF (PA_BCR + 10) #define BCR_ILCRG (PA_BCR + 12) #if defined(CONFIG_CPU_SUBTYPE_SH7709) #define INTC_IRR0 0xa4000004UL #define INTC_IRR1 0xa4000006UL #define INTC_IRR2 0xa4000008UL #define INTC_ICR0 0xfffffee0UL #define INTC_ICR1 0xa4000010UL #define INTC_ICR2 0xa4000012UL #define INTC_INTER 0xa4000014UL #define INTC_IPRC 0xa4000016UL #define INTC_IPRD 0xa4000018UL #define INTC_IPRE 0xa400001aUL #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #endif #if defined(CONFIG_CPU_SUBTYPE_SH7705) #define IRQ_STNIC evt2irq(0x380) #define IRQ_CFCARD evt2irq(0x3c0) #else #define IRQ_STNIC evt2irq(0x340) #define IRQ_CFCARD evt2irq(0x2e0) #endif /* SH Ether support (SH7710/SH7712) */ /* Base address */ #define SH_ETH0_BASE 0xA7000000 #define SH_ETH1_BASE 0xA7000400 #define SH_TSU_BASE 0xA7000800 /* PHY ID */ #if defined(CONFIG_CPU_SUBTYPE_SH7710) # define PHY_ID 0x00 #elif defined(CONFIG_CPU_SUBTYPE_SH7712) # define PHY_ID 0x01 #endif /* Ether IRQ */ #define SH_ETH0_IRQ evt2irq(0xc00) #define SH_ETH1_IRQ evt2irq(0xc20) #define SH_TSU_IRQ evt2irq(0xc40) void init_se_IRQ(void); #define __IO_PREFIX se #include <asm/io_generic.h> #endif /* __ASM_SH_HITACHI_SE_H */ PK ! L � � se7722.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7722_H #define __ASM_SH_SE7722_H /* * linux/include/asm-sh/se7722.h * * Copyright (C) 2007 Nobuhiro Iwamatsu * * Hitachi UL SolutionEngine 7722 Support. */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ #define PA_FROM 0xa1000000 /* Flash-ROM */ #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_PERIPHERAL 0xB0000000 #define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ #define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ /* GPIO */ #define FPGA_IN 0xb1840000UL #define FPGA_OUT 0xb1840004UL #define PORT_PECR 0xA4050108UL #define PORT_PJCR 0xA4050110UL #define PORT_PSELD 0xA4050154UL #define PORT_PSELB 0xA4050150UL #define PORT_PSELC 0xA4050152UL #define PORT_PKCR 0xA4050112UL #define PORT_PHCR 0xA405010EUL #define PORT_PLCR 0xA4050114UL #define PORT_PMCR 0xA4050116UL #define PORT_PRCR 0xA405011CUL #define PORT_PXCR 0xA4050148UL #define PORT_PSELA 0xA405014EUL #define PORT_PYCR 0xA405014AUL #define PORT_PZCR 0xA405014CUL #define PORT_HIZCRA 0xA4050158UL #define PORT_HIZCRC 0xA405015CUL /* IRQ */ #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ #define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ #define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ #define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ #define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ #define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ #define SE7722_FPGA_IRQ_NR 6 struct irq_domain; /* arch/sh/boards/se/7722/irq.c */ extern struct irq_domain *se7722_irq_domain; void init_se7722_IRQ(void); #define __IO_PREFIX se7722 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7722_H */ PK ! �!�Z Z se7780.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7780_H #define __ASM_SH_SE7780_H /* * linux/include/asm-sh/se7780.h * * Copyright (C) 2006,2007 Nobuhiro Iwamatsu * * Hitachi UL SolutionEngine 7780 Support. */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0xa1000000 /* Flash-ROM */ #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */ #define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */ #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ #define PA_SDRAM_SIZE 0x08000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */ #define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */ #define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */ #define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */ #define DISP_CHAR_RAM (7 << 3) #define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0) #define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1) #define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2) #define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3) #define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4) #define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5) #define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6) #define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7) #define DISP_UDC_RAM (5 << 3) #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ /* FPGA register address and bit */ #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */ #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */ #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */ #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */ #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */ #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */ #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */ #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */ #define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */ #define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */ #define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */ #define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */ #define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */ #define PA_LED FPGA_DBG_LED #define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */ #define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */ #define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */ /* FPGA INTSEL position */ /* INTSEL1 */ #define IRQPOS_SMC91CX (0 * 4) #define IRQPOS_SM501 (1 * 4) /* INTSEL2 */ #define IRQPOS_EXTINT1 (0 * 4) #define IRQPOS_EXTINT2 (1 * 4) #define IRQPOS_EXTINT3 (2 * 4) #define IRQPOS_EXTINT4 (3 * 4) /* INTSEL3 */ #define IRQPOS_PCCPW (0 * 4) /* IDE interrupt */ #define IRQ_IDE0 evt2irq(0xa60) /* iVDR */ /* SMC interrupt */ #define SMC_IRQ evt2irq(0x300) /* SM501 interrupt */ #define SM501_IRQ evt2irq(0x200) /* interrupt pin */ #define IRQPIN_EXTINT1 0 /* IRQ0 pin */ #define IRQPIN_EXTINT2 1 /* IRQ1 pin */ #define IRQPIN_EXTINT3 2 /* IRQ2 pin */ #define IRQPIN_SMC91CX 3 /* IRQ3 pin */ #define IRQPIN_EXTINT4 4 /* IRQ4 pin */ #define IRQPIN_PCC0 5 /* IRQ5 pin */ #define IRQPIN_PCC2 6 /* IRQ6 pin */ #define IRQPIN_SM501 7 /* IRQ7 pin */ #define IRQPIN_PCCPW 7 /* IRQ7 pin */ /* arch/sh/boards/se/7780/irq.c */ void init_se7780_IRQ(void); #define __IO_PREFIX se7780 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7780_H */ PK ! ��> mrshpc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_SE_MRSHPC_H #define __MACH_SE_MRSHPC_H #include <linux/io.h> static inline void __init mrshpc_setup_windows(void) { if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) return; /* Not detected */ if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ } else { __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ } /* * PC-Card window open * flag == COMMON/ATTRIBUTE/IO */ /* common window open */ __raw_writew(0x8a84, MRSHPC_MW0CR1); if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) /* common mode & bus width 16bit SWAP = 1*/ __raw_writew(0x0b00, MRSHPC_MW0CR2); else /* common mode & bus width 16bit SWAP = 0*/ __raw_writew(0x0300, MRSHPC_MW0CR2); /* attribute window open */ __raw_writew(0x8a85, MRSHPC_MW1CR1); if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) /* attribute mode & bus width 16bit SWAP = 1*/ __raw_writew(0x0a00, MRSHPC_MW1CR2); else /* attribute mode & bus width 16bit SWAP = 0*/ __raw_writew(0x0200, MRSHPC_MW1CR2); /* I/O window open */ __raw_writew(0x8a86, MRSHPC_IOWCR1); __raw_writew(0x0008, MRSHPC_CDCR); /* I/O card mode */ if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) __raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ else __raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ __raw_writew(0x2000, MRSHPC_ICR); __raw_writeb(0x00, PA_MRSHPC_MW2 + 0x206); __raw_writeb(0x42, PA_MRSHPC_MW2 + 0x200); } #endif /* __MACH_SE_MRSHPC_H */ PK ! ]%��� � se7721.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2008 Renesas Solutions Corp. * * Hitachi UL SolutionEngine 7721 Support. */ #ifndef __ASM_SH_SE7721_H #define __ASM_SH_SE7721_H #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 2 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ #define PA_FROM 0xa1000000 /* Flash-ROM */ #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */ #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_PERIPHERAL 0xB8000000 #define PA_PCIC PA_PERIPHERAL #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define PA_LED 0xB6800000 /* 8bit LED */ #define PA_FPGA 0xB7000000 /* FPGA base address */ #define MRSHPC_IRQ0 evt2irq(0x340) #define FPGA_ILSR1 (PA_FPGA + 0x02) #define FPGA_ILSR2 (PA_FPGA + 0x03) #define FPGA_ILSR3 (PA_FPGA + 0x04) #define FPGA_ILSR4 (PA_FPGA + 0x05) #define FPGA_ILSR5 (PA_FPGA + 0x06) #define FPGA_ILSR6 (PA_FPGA + 0x07) #define FPGA_ILSR7 (PA_FPGA + 0x08) #define FPGA_ILSR8 (PA_FPGA + 0x09) void init_se7721_IRQ(void); #define __IO_PREFIX se7721 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7721_H */ PK ! �(� � se7724.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7724_H #define __ASM_SH_SE7724_H /* * linux/include/asm-sh/se7724.h * * Copyright (C) 2009 Renesas Solutions Corp. * * Kuninori Morimoto <morimoto.kuninori@renesas.com> * * Hitachi UL SolutionEngine 7724 Support. * * Based on se7722.h * Copyright (C) 2007 Nobuhiro Iwamatsu */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* SH Eth */ #define SH_ETH_ADDR (0xA4600000) #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0) #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8) #define PA_LED (0xba203000) /* 8bit LED */ #define IRQ_MODE (0xba200010) #define IRQ0_SR (0xba200014) #define IRQ1_SR (0xba200018) #define IRQ2_SR (0xba20001c) #define IRQ0_MR (0xba200020) #define IRQ1_MR (0xba200024) #define IRQ2_MR (0xba200028) /* IRQ */ #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #define IRQ2_IRQ evt2irq(0x640) /* Bits in IRQ012 registers */ #define SE7724_FPGA_IRQ_BASE 220 /* IRQ0 */ #define IRQ0_BASE SE7724_FPGA_IRQ_BASE #define IRQ0_KEY (IRQ0_BASE + 12) #define IRQ0_RMII (IRQ0_BASE + 13) #define IRQ0_SMC (IRQ0_BASE + 14) #define IRQ0_MASK 0x7fff #define IRQ0_END IRQ0_SMC /* IRQ1 */ #define IRQ1_BASE (IRQ0_END + 1) #define IRQ1_TS (IRQ1_BASE + 0) #define IRQ1_MASK 0x0001 #define IRQ1_END IRQ1_TS /* IRQ2 */ #define IRQ2_BASE (IRQ1_END + 1) #define IRQ2_USB0 (IRQ1_BASE + 0) #define IRQ2_USB1 (IRQ1_BASE + 1) #define IRQ2_MASK 0x0003 #define IRQ2_END IRQ2_USB1 #define SE7724_FPGA_IRQ_NR (IRQ2_END - IRQ0_BASE) /* arch/sh/boards/se/7724/irq.c */ void init_se7724_IRQ(void); #define __IO_PREFIX se7724 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7724_H */ PK ! HX%9% % se7206.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SE7206_H #define __ASM_SH_SE7206_H #define PA_SMSC 0x30000000 #define PA_MRSHPC 0x34000000 #define PA_LED 0x31400000 void init_se7206_IRQ(void); #define __IO_PREFIX se7206 #include <asm/io_generic.h> #endif /* __ASM_SH_SE7206_H */ PK ! ]��)l l se7343.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HITACHI_SE7343_H #define __ASM_SH_HITACHI_SE7343_H /* * include/asm-sh/se/se7343.h * * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> * * SH-Mobile SolutionEngine 7343 support */ #include <linux/sh_intc.h> /* Box specific addresses. */ /* Area 0 */ #define PA_ROM 0x00000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ #define PA_FROM 0x00400000 /* Flash ROM */ #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ #define PA_SRAM 0x00800000 /* SRAM */ #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ /* Area 1 */ #define PA_EXT1 0x04000000 #define PA_EXT1_SIZE 0x04000000 /* Area 2 */ #define PA_EXT2 0x08000000 #define PA_EXT2_SIZE 0x04000000 /* Area 3 */ #define PA_SDRAM 0x0c000000 #define PA_SDRAM_SIZE 0x04000000 /* Area 4 */ #define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ #define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define PA_LED 0xb0C00000 /* LED */ #define LED_SHIFT 0 #define PA_DIPSW 0xb0900000 /* Dip switch 31 */ /* Area 5 */ #define PA_EXT5 0x14000000 #define PA_EXT5_SIZE 0x04000000 /* Area 6 */ #define PA_LCD1 0xb8000000 #define PA_LCD2 0xb8800000 #define PORT_PACR 0xA4050100 #define PORT_PBCR 0xA4050102 #define PORT_PCCR 0xA4050104 #define PORT_PDCR 0xA4050106 #define PORT_PECR 0xA4050108 #define PORT_PFCR 0xA405010A #define PORT_PGCR 0xA405010C #define PORT_PHCR 0xA405010E #define PORT_PJCR 0xA4050110 #define PORT_PKCR 0xA4050112 #define PORT_PLCR 0xA4050114 #define PORT_PMCR 0xA4050116 #define PORT_PNCR 0xA4050118 #define PORT_PQCR 0xA405011A #define PORT_PRCR 0xA405011C #define PORT_PSCR 0xA405011E #define PORT_PTCR 0xA4050140 #define PORT_PUCR 0xA4050142 #define PORT_PVCR 0xA4050144 #define PORT_PWCR 0xA4050146 #define PORT_PYCR 0xA4050148 #define PORT_PZCR 0xA405014A #define PORT_PSELA 0xA405014C #define PORT_PSELB 0xA405014E #define PORT_PSELC 0xA4050150 #define PORT_PSELD 0xA4050152 #define PORT_PSELE 0xA4050154 #define PORT_HIZCRA 0xA4050156 #define PORT_HIZCRB 0xA4050158 #define PORT_HIZCRC 0xA405015C #define PORT_DRVCR 0xA4050180 #define PORT_PADR 0xA4050120 #define PORT_PBDR 0xA4050122 #define PORT_PCDR 0xA4050124 #define PORT_PDDR 0xA4050126 #define PORT_PEDR 0xA4050128 #define PORT_PFDR 0xA405012A #define PORT_PGDR 0xA405012C #define PORT_PHDR 0xA405012E #define PORT_PJDR 0xA4050130 #define PORT_PKDR 0xA4050132 #define PORT_PLDR 0xA4050134 #define PORT_PMDR 0xA4050136 #define PORT_PNDR 0xA4050138 #define PORT_PQDR 0xA405013A #define PORT_PRDR 0xA405013C #define PORT_PTDR 0xA4050160 #define PORT_PUDR 0xA4050162 #define PORT_PVDR 0xA4050164 #define PORT_PWDR 0xA4050166 #define PORT_PYDR 0xA4050168 #define FPGA_IN 0xb1400000 #define FPGA_OUT 0xb1400002 #define IRQ0_IRQ evt2irq(0x600) #define IRQ1_IRQ evt2irq(0x620) #define IRQ4_IRQ evt2irq(0x680) #define IRQ5_IRQ evt2irq(0x6a0) #define SE7343_FPGA_IRQ_MRSHPC0 0 #define SE7343_FPGA_IRQ_MRSHPC1 1 #define SE7343_FPGA_IRQ_MRSHPC2 2 #define SE7343_FPGA_IRQ_MRSHPC3 3 #define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */ #define SE7343_FPGA_IRQ_USB 8 #define SE7343_FPGA_IRQ_UARTA 10 #define SE7343_FPGA_IRQ_UARTB 11 #define SE7343_FPGA_IRQ_NR 12 struct irq_domain; /* arch/sh/boards/se/7343/irq.c */ extern struct irq_domain *se7343_irq_domain; void init_7343se_IRQ(void); #endif /* __ASM_SH_HITACHI_SE7343_H */ PK ! ���#' ' se7751.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_HITACHI_7751SE_H #define __ASM_SH_HITACHI_7751SE_H /* * linux/include/asm-sh/hitachi_7751se.h * * Copyright (C) 2000 Kazumoto Kojima * * Hitachi SolutionEngine support * Modified for 7751 Solution Engine by * Ian da Silva and Jeremy Siegel, 2001. */ #include <linux/sh_intc.h> /* Box specific addresses. */ #define PA_ROM 0x00000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0x01000000 /* EPROM */ #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_EXT1 0x04000000 #define PA_EXT1_SIZE 0x04000000 #define PA_EXT2 0x08000000 #define PA_EXT2_SIZE 0x04000000 #define PA_SDRAM 0x0c000000 #define PA_SDRAM_SIZE 0x04000000 #define PA_EXT4 0x12000000 #define PA_EXT4_SIZE 0x02000000 #define PA_EXT5 0x14000000 #define PA_EXT5_SIZE 0x04000000 #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ #define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ #define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ #define PA_LED 0xba000000 /* LED */ #define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ #define MRSHPC_MODE (PA_MRSHPC + 4) #define MRSHPC_OPTION (PA_MRSHPC + 6) #define MRSHPC_CSR (PA_MRSHPC + 8) #define MRSHPC_ISR (PA_MRSHPC + 10) #define MRSHPC_ICR (PA_MRSHPC + 12) #define MRSHPC_CPWCR (PA_MRSHPC + 14) #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) #define MRSHPC_CDCR (PA_MRSHPC + 28) #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) #define BCR_ILCRA (PA_BCR + 0) #define BCR_ILCRB (PA_BCR + 2) #define BCR_ILCRC (PA_BCR + 4) #define BCR_ILCRD (PA_BCR + 6) #define BCR_ILCRE (PA_BCR + 8) #define BCR_ILCRF (PA_BCR + 10) #define BCR_ILCRG (PA_BCR + 12) #define IRQ_79C973 evt2irq(0x3a0) void init_7751se_IRQ(void); #define __IO_PREFIX sh7751se #include <asm/io_generic.h> #endif /* __ASM_SH_HITACHI_7751SE_H */ PK ! ��>�'. '. ixp4xx-regs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h * * Register definitions for IXP4xx chipset. This file contains * register location and bit definitions only. Platform specific * definitions and helper function declarations are in platform.h * and machine-name.h. * * Copyright (C) 2002 Intel Corporation. * Copyright (C) 2003-2004 MontaVista Software, Inc. */ #ifndef _ASM_ARM_IXP4XX_H_ #define _ASM_ARM_IXP4XX_H_ /* * IXP4xx Linux Memory Map: * * Phy Size Virt Description * ========================================================================= * * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM * * 0x48000000 0x04000000 ioremap'd PCI Memory Space * * 0x50000000 0x10000000 ioremap'd EXP BUS * * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals * * 0xC0000000 0x00001000 0xFEF13000 PCI CFG * * 0xC4000000 0x00001000 0xFEF14000 EXP CFG * * 0x60000000 0x00004000 0xFEF15000 QMgr */ /* * Queue Manager */ #define IXP4XX_QMGR_BASE_PHYS 0x60000000 /* * Peripheral space, including debug UART. Must be section-aligned so that * it can be used with the low-level debug code. */ #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000) #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 /* * PCI Config registers */ #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000) #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 /* * Expansion BUS Configuration registers */ #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 #define IXP4XX_EXP_CS0_OFFSET 0x00 #define IXP4XX_EXP_CS1_OFFSET 0x04 #define IXP4XX_EXP_CS2_OFFSET 0x08 #define IXP4XX_EXP_CS3_OFFSET 0x0C #define IXP4XX_EXP_CS4_OFFSET 0x10 #define IXP4XX_EXP_CS5_OFFSET 0x14 #define IXP4XX_EXP_CS6_OFFSET 0x18 #define IXP4XX_EXP_CS7_OFFSET 0x1C #define IXP4XX_EXP_CFG0_OFFSET 0x20 #define IXP4XX_EXP_CFG1_OFFSET 0x24 #define IXP4XX_EXP_CFG2_OFFSET 0x28 #define IXP4XX_EXP_CFG3_OFFSET 0x2C /* * Expansion Bus Controller registers. */ #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) /* * Peripheral Space Register Region Base Addresses */ #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) /* ixp46X only */ #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) /* The UART is explicitly put in the beginning of fixmap */ #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) /* ixp46X only */ #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) /* * Constants to make it easy to access Timer Control/Status registers */ #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ /* * Operating System Timer Register Definitions. */ #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) /* * Timer register values and bit definitions */ #define IXP4XX_OST_ENABLE 0x00000001 #define IXP4XX_OST_ONE_SHOT 0x00000002 /* Low order bits of reload value ignored */ #define IXP4XX_OST_RELOAD_MASK 0x00000003 #define IXP4XX_OST_DISABLED 0x00000000 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 #define IXP4XX_WDT_KEY 0x0000482E #define IXP4XX_WDT_RESET_ENABLE 0x00000001 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 /* * Constants to make it easy to access PCI Control/Status registers */ #define PCI_NP_AD_OFFSET 0x00 #define PCI_NP_CBE_OFFSET 0x04 #define PCI_NP_WDATA_OFFSET 0x08 #define PCI_NP_RDATA_OFFSET 0x0c #define PCI_CRP_AD_CBE_OFFSET 0x10 #define PCI_CRP_WDATA_OFFSET 0x14 #define PCI_CRP_RDATA_OFFSET 0x18 #define PCI_CSR_OFFSET 0x1c #define PCI_ISR_OFFSET 0x20 #define PCI_INTEN_OFFSET 0x24 #define PCI_DMACTRL_OFFSET 0x28 #define PCI_AHBMEMBASE_OFFSET 0x2c #define PCI_AHBIOBASE_OFFSET 0x30 #define PCI_PCIMEMBASE_OFFSET 0x34 #define PCI_AHBDOORBELL_OFFSET 0x38 #define PCI_PCIDOORBELL_OFFSET 0x3C #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 /* * PCI Control/Status Registers */ #define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) #define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) #define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) #define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) #define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) #define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) #define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) #define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) #define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) #define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET) #define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) #define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) #define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) #define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) #define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) #define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) #define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) #define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) #define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) #define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) #define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) #define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) #define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) /* * PCI register values and bit definitions */ /* CSR bit definitions */ #define PCI_CSR_HOST 0x00000001 #define PCI_CSR_ARBEN 0x00000002 #define PCI_CSR_ADS 0x00000004 #define PCI_CSR_PDS 0x00000008 #define PCI_CSR_ABE 0x00000010 #define PCI_CSR_DBT 0x00000020 #define PCI_CSR_ASE 0x00000100 #define PCI_CSR_IC 0x00008000 /* ISR (Interrupt status) Register bit definitions */ #define PCI_ISR_PSE 0x00000001 #define PCI_ISR_PFE 0x00000002 #define PCI_ISR_PPE 0x00000004 #define PCI_ISR_AHBE 0x00000008 #define PCI_ISR_APDC 0x00000010 #define PCI_ISR_PADC 0x00000020 #define PCI_ISR_ADB 0x00000040 #define PCI_ISR_PDB 0x00000080 /* INTEN (Interrupt Enable) Register bit definitions */ #define PCI_INTEN_PSE 0x00000001 #define PCI_INTEN_PFE 0x00000002 #define PCI_INTEN_PPE 0x00000004 #define PCI_INTEN_AHBE 0x00000008 #define PCI_INTEN_APDC 0x00000010 #define PCI_INTEN_PADC 0x00000020 #define PCI_INTEN_ADB 0x00000040 #define PCI_INTEN_PDB 0x00000080 /* * Shift value for byte enable on NP cmd/byte enable register */ #define IXP4XX_PCI_NP_CBE_BESL 4 /* * PCI commands supported by NP access unit */ #define NP_CMD_IOREAD 0x2 #define NP_CMD_IOWRITE 0x3 #define NP_CMD_CONFIGREAD 0xa #define NP_CMD_CONFIGWRITE 0xb #define NP_CMD_MEMREAD 0x6 #define NP_CMD_MEMWRITE 0x7 /* * Constants for CRP access into local config space */ #define CRP_AD_CBE_BESL 20 #define CRP_AD_CBE_WRITE 0x00010000 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ #endif PK ! k�:� � udc.hnu �[��� /* * arch/arm/mach-ixp4xx/include/mach/udc.h * */ #include <linux/platform_data/pxa2xx_udc.h> extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); PK ! �^~6W5 W5 io.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/io.h * * Author: Deepak Saxena <dsaxena@plexity.net> * * Copyright (C) 2002-2005 MontaVista Software, Inc. */ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H #include <linux/bitops.h> #include <mach/hardware.h> extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); /* * IXP4xx provides two methods of accessing PCI memory space: * * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). * To access PCI via this space, we simply ioremap() the BAR * into the kernel and we can use the standard read[bwl]/write[bwl] * macros. This is the preffered method due to speed but it * limits the system to just 64MB of PCI memory. This can be * problematic if using video cards and other memory-heavy targets. * * 2) If > 64MB of memory space is required, the IXP4xx can use indirect * registers to access the whole 4 GB of PCI memory space (as we do below * for I/O transactions). This allows currently for up to 1 GB (0x10000000 * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that * every PCI access requires three local register accesses plus a spinlock, * but in some cases the performance hit is acceptable. In addition, you * cannot mmap() PCI devices in this case. */ #ifdef CONFIG_IXP4XX_INDIRECT_PCI /* * In the case of using indirect PCI, we simply return the actual PCI * address and our read/write implementation use that to drive the * access registers. If something outside of PCI is ioremap'd, we * fallback to the default. */ extern unsigned long pcibios_min_mem; static inline int is_pci_memory(u32 addr) { return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF); } #define writeb(v, p) __indirect_writeb(v, p) #define writew(v, p) __indirect_writew(v, p) #define writel(v, p) __indirect_writel(v, p) #define writeb_relaxed(v, p) __indirect_writeb(v, p) #define writew_relaxed(v, p) __indirect_writew(v, p) #define writel_relaxed(v, p) __indirect_writel(v, p) #define writesb(p, v, l) __indirect_writesb(p, v, l) #define writesw(p, v, l) __indirect_writesw(p, v, l) #define writesl(p, v, l) __indirect_writesl(p, v, l) #define readb(p) __indirect_readb(p) #define readw(p) __indirect_readw(p) #define readl(p) __indirect_readl(p) #define readb_relaxed(p) __indirect_readb(p) #define readw_relaxed(p) __indirect_readw(p) #define readl_relaxed(p) __indirect_readl(p) #define readsb(p, v, l) __indirect_readsb(p, v, l) #define readsw(p, v, l) __indirect_readsw(p, v, l) #define readsl(p, v, l) __indirect_readsl(p, v, l) static inline void __indirect_writeb(u8 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) { __raw_writeb(value, p); return; } n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } static inline void __indirect_writesb(volatile void __iomem *bus_addr, const void *p, int count) { const u8 *vaddr = p; while (count--) writeb(*vaddr++, bus_addr); } static inline void __indirect_writew(u16 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) { __raw_writew(value, p); return; } n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } static inline void __indirect_writesw(volatile void __iomem *bus_addr, const void *p, int count) { const u16 *vaddr = p; while (count--) writew(*vaddr++, bus_addr); } static inline void __indirect_writel(u32 value, volatile void __iomem *p) { u32 addr = (__force u32)p; if (!is_pci_memory(addr)) { __raw_writel(value, p); return; } ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); } static inline void __indirect_writesl(volatile void __iomem *bus_addr, const void *p, int count) { const u32 *vaddr = p; while (count--) writel(*vaddr++, bus_addr); } static inline u8 __indirect_readb(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) return __raw_readb(p); n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) return 0xff; return data >> (8*n); } static inline void __indirect_readsb(const volatile void __iomem *bus_addr, void *p, u32 count) { u8 *vaddr = p; while (count--) *vaddr++ = readb(bus_addr); } static inline u16 __indirect_readw(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) return __raw_readw(p); n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) return 0xffff; return data>>(8*n); } static inline void __indirect_readsw(const volatile void __iomem *bus_addr, void *p, u32 count) { u16 *vaddr = p; while (count--) *vaddr++ = readw(bus_addr); } static inline u32 __indirect_readl(const volatile void __iomem *p) { u32 addr = (__force u32)p; u32 data; if (!is_pci_memory(addr)) return __raw_readl(p); if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) return 0xffffffff; return data; } static inline void __indirect_readsl(const volatile void __iomem *bus_addr, void *p, u32 count) { u32 *vaddr = p; while (count--) *vaddr++ = readl(bus_addr); } /* * We can use the built-in functions b/c they end up calling writeb/readb */ #define memset_io(c,v,l) _memset_io((c),(v),(l)) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) #endif /* CONFIG_IXP4XX_INDIRECT_PCI */ #ifndef CONFIG_PCI #define __io(v) __typesafe_io(v) #else /* * IXP4xx does not have a transparent cpu -> PCI I/O translation * window. Instead, it has a set of registers that must be tweaked * with the proper byte lanes, command types, and address for the * transaction. This means that we need to override the default * I/O functions. */ #define outb outb static inline void outb(u8 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } #define outsb outsb static inline void outsb(u32 io_addr, const void *p, u32 count) { const u8 *vaddr = p; while (count--) outb(*vaddr++, io_addr); } #define outw outw static inline void outw(u16 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } #define outsw outsw static inline void outsw(u32 io_addr, const void *p, u32 count) { const u16 *vaddr = p; while (count--) outw(cpu_to_le16(*vaddr++), io_addr); } #define outl outl static inline void outl(u32 value, u32 addr) { ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); } #define outsl outsl static inline void outsl(u32 io_addr, const void *p, u32 count) { const u32 *vaddr = p; while (count--) outl(cpu_to_le32(*vaddr++), io_addr); } #define inb inb static inline u8 inb(u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) return 0xff; return data >> (8*n); } #define insb insb static inline void insb(u32 io_addr, void *p, u32 count) { u8 *vaddr = p; while (count--) *vaddr++ = inb(io_addr); } #define inw inw static inline u16 inw(u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) return 0xffff; return data>>(8*n); } #define insw insw static inline void insw(u32 io_addr, void *p, u32 count) { u16 *vaddr = p; while (count--) *vaddr++ = le16_to_cpu(inw(io_addr)); } #define inl inl static inline u32 inl(u32 addr) { u32 data; if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) return 0xffffffff; return data; } #define insl insl static inline void insl(u32 io_addr, void *p, u32 count) { u32 *vaddr = p; while (count--) *vaddr++ = le32_to_cpu(inl(io_addr)); } #define PIO_OFFSET 0x10000UL #define PIO_MASK 0x0ffffUL #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) #define ioread8(p) ioread8(p) static inline u8 ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(addr); #else return (unsigned int)__indirect_readb(addr); #endif } #define ioread8_rep(p, v, c) ioread8_rep(p, v, c) static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) insb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); #else __indirect_readsb(addr, vaddr, count); #endif } #define ioread16(p) ioread16(p) static inline u16 ioread16(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)inw(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu((__force __le16)__raw_readw(addr)); #else return (unsigned int)__indirect_readw(addr); #endif } #define ioread16_rep(p, v, c) ioread16_rep(p, v, c) static inline void ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) insw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); #else __indirect_readsw(addr, vaddr, count); #endif } #define ioread32(p) ioread32(p) static inline u32 ioread32(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)inl(port & PIO_MASK); else { #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu((__force __le32)__raw_readl(addr)); #else return (unsigned int)__indirect_readl(addr); #endif } } #define ioread32_rep(p, v, c) ioread32_rep(p, v, c) static inline void ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) insl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); #else __indirect_readsl(addr, vaddr, count); #endif } #define iowrite8(v, p) iowrite8(v, p) static inline void iowrite8(u8 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outb(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, addr); #else __indirect_writeb(value, addr); #endif } #define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outsb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); #else __indirect_writesb(addr, vaddr, count); #endif } #define iowrite16(v, p) iowrite16(v, p) static inline void iowrite16(u16 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outw(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); #else __indirect_writew(value, addr); #endif } #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outsw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); #else __indirect_writesw(addr, vaddr, count); #endif } #define iowrite32(v, p) iowrite32(v, p) static inline void iowrite32(u32 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outl(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel((u32 __force)cpu_to_le32(value), addr); #else __indirect_writel(value, addr); #endif } #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outsl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); #else __indirect_writesl(addr, vaddr, count); #endif } #define ioport_map(port, nr) ioport_map(port, nr) static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) { return ((void __iomem*)((port) + PIO_OFFSET)); } #define ioport_unmap(addr) ioport_unmap(addr) static inline void ioport_unmap(void __iomem *addr) { } #endif /* CONFIG_PCI */ #endif /* __ASM_ARM_ARCH_IO_H */ PK ! �=8-� � platform.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-ixp4xx/include/mach/platform.h * * Constants and functions that are useful to IXP4xx platform-specific code * and device drivers. * * Copyright (C) 2004 MontaVista Software, Inc. */ #ifndef __ASM_ARCH_HARDWARE_H__ #error "Do not include this directly, instead #include <mach/hardware.h>" #endif #ifndef __ASSEMBLY__ #include <linux/reboot.h> #include <linux/platform_data/eth_ixp4xx.h> #include <asm/types.h> #ifndef __ARMEB__ #define REG_OFFSET 0 #else #define REG_OFFSET 3 #endif /* * Expansion bus memory regions */ #define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000) /* * The expansion bus on the IXP4xx can be configured for either 16 or * 32MB windows and the CS offset for each region changes based on the * current configuration. This means that we cannot simply hardcode * each offset. ixp4xx_sys_init() looks at the expansion bus configuration * as setup by the bootloader to determine our window size. */ extern unsigned long ixp4xx_exp_bus_size; #define IXP4XX_EXP_BUS_BASE(region)\ (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size)) #define IXP4XX_EXP_BUS_END(region)\ (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1) /* Those macros can be used to adjust timing and configure * other features for each region. */ #define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16) #define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20) #define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22) #define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26) #define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28) #define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10) #define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14) #define IXP4XX_EXP_BUS_CS_EN (1L << 31) #define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6) #define IXP4XX_EXP_BUS_HRDY_POL (1L << 5) #define IXP4XX_EXP_BUS_MUX_EN (1L << 4) #define IXP4XX_EXP_BUS_SPLT_EN (1L << 3) #define IXP4XX_EXP_BUS_WR_EN (1L << 1) #define IXP4XX_EXP_BUS_BYTE_EN (1L << 0) #define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00 #define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01 #define IXP4XX_EXP_BUS_CYCLES_HPI 0x02 #define IXP4XX_FLASH_WRITABLE (0x2) #define IXP4XX_FLASH_DEFAULT (0xbcd23c40) #define IXP4XX_FLASH_WRITE (0xbcd23c42) /* * Clock Speed Definitions. */ #define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */ #define IXP4XX_UART_XTAL 14745600 /* * Frequency of clock used for primary clocksource */ extern unsigned long ixp4xx_timer_freq; /* * Functions used by platform-level setup code */ extern void ixp4xx_map_io(void); extern void ixp4xx_init_early(void); extern void ixp4xx_init_irq(void); extern void ixp4xx_sys_init(void); extern void ixp4xx_timer_init(void); extern void ixp4xx_restart(enum reboot_mode, const char *); extern void ixp4xx_pci_preinit(void); struct pci_sys_data; extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); extern struct pci_ops ixp4xx_ops; #endif // __ASSEMBLY__ PK ! ���) ) h3xxx.hnu �[��� PK ! � _� � ` uncompress.hnu �[��� PK ! ]_��2 2 1 irqs.hnu �[��� PK ! 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