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PK ! �!��� � include/mach/uncompress.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-rpc/include/mach/uncompress.h * * Copyright (C) 1996 Russell King */ #define VIDMEM ((char *)SCREEN_START) #include <linux/io.h> #include <mach/hardware.h> #include <asm/setup.h> #include <asm/page.h> int video_size_row; unsigned char bytes_per_char_h; extern unsigned long con_charconvtable[256]; struct param_struct { unsigned long page_size; unsigned long nr_pages; unsigned long ramdisk_size; unsigned long mountrootrdonly; unsigned long rootdev; unsigned long video_num_cols; unsigned long video_num_rows; unsigned long video_x; unsigned long video_y; unsigned long memc_control_reg; unsigned char sounddefault; unsigned char adfsdrives; unsigned char bytes_per_char_h; unsigned char bytes_per_char_v; unsigned long unused[256/4-11]; }; static const unsigned long palette_4[16] = { 0x00000000, 0x000000cc, 0x0000cc00, /* Green */ 0x0000cccc, /* Yellow */ 0x00cc0000, /* Blue */ 0x00cc00cc, /* Magenta */ 0x00cccc00, /* Cyan */ 0x00cccccc, /* White */ 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff }; #define palette_setpixel(p) *(unsigned long *)(IO_START+0x00400000) = 0x10000000|((p) & 255) #define palette_write(v) *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff) /* * params_phys is a linker defined symbol - see * arch/arm/boot/compressed/Makefile */ extern __attribute__((pure)) struct param_struct *params(void); #define params (params()) #ifndef STANDALONE_DEBUG unsigned long video_num_cols; unsigned long video_num_rows; unsigned long video_x; unsigned long video_y; unsigned char bytes_per_char_v; int white; /* * This does not append a newline */ static inline void putc(int c) { extern void ll_write_char(char *, char c, char white); int x,y; char *ptr; x = video_x; y = video_y; if (c == '\n') { if (++y >= video_num_rows) y--; } else if (c == '\r') { x = 0; } else { ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h); ll_write_char(ptr, c, white); if (++x >= video_num_cols) { x = 0; if ( ++y >= video_num_rows ) { y--; } } } video_x = x; video_y = y; } static inline void flush(void) { } /* * Setup for decompression */ static void arch_decomp_setup(void) { int i; struct tag *t = (struct tag *)params; unsigned int nr_pages = 0, page_size = PAGE_SIZE; if (t->hdr.tag == ATAG_CORE) { for (; t->hdr.size; t = tag_next(t)) { if (t->hdr.tag == ATAG_VIDEOTEXT) { video_num_rows = t->u.videotext.video_lines; video_num_cols = t->u.videotext.video_cols; video_x = t->u.videotext.x; video_y = t->u.videotext.y; } else if (t->hdr.tag == ATAG_VIDEOLFB) { bytes_per_char_h = t->u.videolfb.lfb_depth; bytes_per_char_v = 8; } else if (t->hdr.tag == ATAG_MEM) { page_size = PAGE_SIZE; nr_pages += (t->u.mem.size / PAGE_SIZE); } } } else { nr_pages = params->nr_pages; page_size = params->page_size; video_num_rows = params->video_num_rows; video_num_cols = params->video_num_cols; video_x = params->video_x; video_y = params->video_y; bytes_per_char_h = params->bytes_per_char_h; bytes_per_char_v = params->bytes_per_char_v; } video_size_row = video_num_cols * bytes_per_char_h; if (bytes_per_char_h == 4) for (i = 0; i < 256; i++) con_charconvtable[i] = (i & 128 ? 1 << 0 : 0) | (i & 64 ? 1 << 4 : 0) | (i & 32 ? 1 << 8 : 0) | (i & 16 ? 1 << 12 : 0) | (i & 8 ? 1 << 16 : 0) | (i & 4 ? 1 << 20 : 0) | (i & 2 ? 1 << 24 : 0) | (i & 1 ? 1 << 28 : 0); else for (i = 0; i < 16; i++) con_charconvtable[i] = (i & 8 ? 1 << 0 : 0) | (i & 4 ? 1 << 8 : 0) | (i & 2 ? 1 << 16 : 0) | (i & 1 ? 1 << 24 : 0); palette_setpixel(0); if (bytes_per_char_h == 1) { palette_write (0); palette_write (0x00ffffff); for (i = 2; i < 256; i++) palette_write (0); white = 1; } else { for (i = 0; i < 256; i++) palette_write (i < 16 ? palette_4[i] : 0); white = 7; } if (nr_pages * page_size < 4096*1024) error("<4M of mem\n"); } #endif PK ! �_ _ include/mach/irqs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-rpc/include/mach/irqs.h * * Copyright (C) 1996 Russell King */ #define IRQ_PRINTER 0 #define IRQ_BATLOW 1 #define IRQ_FLOPPYINDEX 2 #define IRQ_VSYNCPULSE 3 #define IRQ_POWERON 4 #define IRQ_TIMER0 5 #define IRQ_TIMER1 6 #define IRQ_IMMEDIATE 7 #define IRQ_EXPCARDFIQ 8 #define IRQ_HARDDISK 9 #define IRQ_SERIALPORT 10 #define IRQ_FLOPPYDISK 12 #define IRQ_EXPANSIONCARD 13 #define IRQ_KEYBOARDTX 14 #define IRQ_KEYBOARDRX 15 #define IRQ_DMA0 16 #define IRQ_DMA1 17 #define IRQ_DMA2 18 #define IRQ_DMA3 19 #define IRQ_DMAS0 20 #define IRQ_DMAS1 21 #define FIQ_FLOPPYDATA 0 #define FIQ_ECONET 2 #define FIQ_SERIALPORT 4 #define FIQ_EXPANSIONCARD 6 #define FIQ_FORCE 7 /* * This is the offset of the FIQ "IRQ" numbers */ #define FIQ_START 64 #define NR_IRQS 128 PK ! y煴 � include/mach/hardware.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-rpc/include/mach/hardware.h * * Copyright (C) 1996-1999 Russell King. * * This file contains the hardware definitions of the RiscPC series machines. */ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H #include <mach/memory.h> /* * What hardware must be present */ #define HAS_IOMD #define HAS_VIDC20 /* Hardware addresses of major areas. * *_START is the physical address * *_SIZE is the size of the region * *_BASE is the virtual address */ #define RPC_RAM_SIZE 0x10000000 #define RPC_RAM_START 0x10000000 #define EASI_SIZE 0x08000000 /* EASI I/O */ #define EASI_START 0x08000000 #define EASI_BASE IOMEM(0xe5000000) #define IO_START 0x03000000 /* I/O */ #define IO_SIZE 0x01000000 #define IO_BASE IOMEM(0xe0000000) #define SCREEN_START 0x02000000 /* VRAM */ #define SCREEN_END 0xdfc00000 #define SCREEN_BASE 0xdf800000 #define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000) /* * IO Addresses */ #define ECARD_EASI_BASE (EASI_BASE) #define VIDC_BASE (IO_BASE + 0x00400000) #define EXPMASK_BASE (IO_BASE + 0x00360000) #define ECARD_IOC4_BASE (IO_BASE + 0x00270000) #define ECARD_IOC_BASE (IO_BASE + 0x00240000) #define IOMD_BASE (IO_BASE + 0x00200000) #define IOC_BASE (IO_BASE + 0x00200000) #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000) #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000) #define PCIO_BASE (IO_BASE + 0x00010000) #define ECARD_MEMC_BASE (IO_BASE + 0x00000000) #define vidc_writel(val) __raw_writel(val, VIDC_BASE) #define NETSLOT_BASE 0x0302b000 #define NETSLOT_SIZE 0x00001000 #define PODSLOT_IOC0_BASE 0x03240000 #define PODSLOT_IOC4_BASE 0x03270000 #define PODSLOT_IOC_SIZE (1 << 14) #define PODSLOT_MEMC_BASE 0x03000000 #define PODSLOT_MEMC_SIZE (1 << 14) #define PODSLOT_EASI_BASE 0x08000000 #define PODSLOT_EASI_SIZE (1 << 24) #define EXPMASK_STATUS (EXPMASK_BASE + 0x00) #define EXPMASK_ENABLE (EXPMASK_BASE + 0x04) #endif PK ! �D�M M include/mach/memory.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-rpc/include/mach/memory.h * * Copyright (C) 1996,1997,1998 Russell King. * * Changelog: * 20-Oct-1996 RMK Created * 31-Dec-1997 RMK Fixed definitions to reduce warnings * 11-Jan-1998 RMK Uninlined to reduce hits on cache * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt * 21-Mar-1999 RMK Renamed to memory.h * RMK Added TASK_SIZE and PAGE_OFFSET */ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H /* * Cache flushing area - ROM */ #define FLUSH_BASE_PHYS 0x00000000 #define FLUSH_BASE 0xdf000000 /* * Sparsemem support. Each section is a maximum of 64MB. The sections * are offset by 128MB and can cover 128MB, so that gives us a maximum * of 29 physmem bits. */ #define MAX_PHYSMEM_BITS 29 #define SECTION_SIZE_BITS 26 #endif PK ! ���G� � include/mach/acornfb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-rpc/include/mach/acornfb.h * * Copyright (C) 1999 Russell King * * AcornFB architecture specific code */ #define acornfb_bandwidth(var) ((var)->pixclock * 8 / (var)->bits_per_pixel) static inline int acornfb_valid_pixrate(struct fb_var_screeninfo *var) { u_long limit; if (!var->pixclock) return 0; /* * Limits below are taken from RISC OS bandwidthlimit file */ if (current_par.using_vram) { if (current_par.vram_half_sam == 2048) limit = 6578; else limit = 13157; } else { limit = 26315; } return acornfb_bandwidth(var) >= limit; } /* * Try to find the best PLL parameters for the pixel clock. * This algorithm seems to give best predictable results, * and produces the same values as detailed in the VIDC20 * data sheet. */ static inline u_int acornfb_vidc20_find_pll(u_int pixclk) { u_int r, best_r = 2, best_v = 2; int best_d = 0x7fffffff; for (r = 2; r <= 32; r++) { u_int rr, v, p; int d; rr = 41667 * r; v = (rr + pixclk / 2) / pixclk; if (v > 32 || v < 2) continue; p = (rr + v / 2) / v; d = pixclk - p; if (d < 0) d = -d; if (d < best_d) { best_d = d; best_v = v - 1; best_r = r - 1; } if (d == 0) break; } return best_v << 8 | best_r; } static inline void acornfb_vidc20_find_rates(struct vidc_timing *vidc, struct fb_var_screeninfo *var) { u_int div; /* Select pixel-clock divisor to keep PLL in range */ div = var->pixclock / 9090; /*9921*/ /* Limit divisor */ if (div == 0) div = 1; if (div > 8) div = 8; /* Encode divisor to VIDC20 setting */ switch (div) { case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break; case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break; case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break; case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break; case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break; case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break; case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break; case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break; } /* * With VRAM, the FIFO can be set to the highest possible setting * because there are no latency considerations for other memory * accesses. However, in 64 bit bus mode the FIFO preload value * must not be set to VIDC20_CTRL_FIFO_28 because this will let * the FIFO overflow. See VIDC20 manual page 33 (6.0 Setting the * FIFO preload value). */ if (current_par.using_vram) { if (current_par.vram_half_sam == 2048) vidc->control |= VIDC20_CTRL_FIFO_24; else vidc->control |= VIDC20_CTRL_FIFO_28; } else { unsigned long bandwidth = acornfb_bandwidth(var); /* Encode bandwidth as VIDC20 setting */ if (bandwidth > 33334) /* < 30.0MB/s */ vidc->control |= VIDC20_CTRL_FIFO_16; else if (bandwidth > 26666) /* < 37.5MB/s */ vidc->control |= VIDC20_CTRL_FIFO_20; else if (bandwidth > 22222) /* < 45.0MB/s */ vidc->control |= VIDC20_CTRL_FIFO_24; else /* > 45.0MB/s */ vidc->control |= VIDC20_CTRL_FIFO_28; } /* Find the PLL values */ vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div); } #define acornfb_default_control() (VIDC20_CTRL_PIX_VCLK) #define acornfb_default_econtrol() (VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3)) PK ! �Ƞ � include/mach/io.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-rpc/include/mach/io.h * * Copyright (C) 1997 Russell King * * Modifications: * 06-Dec-1997 RMK Created. */ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H #include <mach/hardware.h> #define IO_SPACE_LIMIT 0xffff /* * We need PC style IO addressing for: * - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7) * - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a) * - 8250 serial (only for compile) * * These peripherals are found in an area of MMIO which looks very much * like an ISA bus, but with registers at the low byte of each word. */ #define __io(a) (PCIO_BASE + ((a) << 2)) #endif PK ! ƙl�X X include/mach/entry-macro.Snu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #include <mach/hardware.h> #include <asm/hardware/entry-macro-iomd.S> .equ ioc_base_high, IOC_BASE & 0xff000000 .equ ioc_base_low, IOC_BASE & 0x00ff0000 .macro get_irqnr_preamble, base, tmp mov \base, #ioc_base_high @ point at IOC .if ioc_base_low orr \base, \base, #ioc_base_low .endif .endm PK ! ��P� � include/mach/isa-dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-rpc/include/mach/isa-dma.h * * Copyright (C) 1997 Russell King */ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H #define MAX_DMA_CHANNELS 8 #define DMA_0 0 #define DMA_1 1 #define DMA_2 2 #define DMA_3 3 #define DMA_S0 4 #define DMA_S1 5 #define DMA_VIRTUAL_FLOPPY 6 #define DMA_VIRTUAL_SOUND 7 #define DMA_FLOPPY DMA_VIRTUAL_FLOPPY #define IOMD_DMA_BOUNDARY (PAGE_SIZE - 1) #endif /* _ASM_ARCH_DMA_H */ PK ! ��� � Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only # # Makefile for the linux kernel. # # Object file lists. obj-y :=dma.o ecard.o ecard-loader.o fiq.o floppydma.o io-acorn.o irq.o \ riscpc.o time.o PK ! ��Fm} } Makefile.bootnu �[��� # SPDX-License-Identifier: GPL-2.0-only zreladdr-y += 0x10008000 params_phys-y := 0x10000100 initrd_phys-y := 0x18000000 PK ! �!��� � include/mach/uncompress.hnu �[��� PK ! �_ _ � include/mach/irqs.hnu �[��� PK ! y煴 � z include/mach/hardware.hnu �[��� PK ! �D�M M u include/mach/memory.hnu �[��� PK ! ���G� � include/mach/acornfb.hnu �[��� PK ! �Ƞ � - include/mach/io.hnu �[��� PK ! ƙl�X X �/ include/mach/entry-macro.Snu �[��� PK ! ��P� � �1 include/mach/isa-dma.hnu �[��� PK ! ��� � �3 Makefilenu �[��� PK ! ��Fm} } �4 Makefile.bootnu �[��� PK D �5
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