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PK ! �3h� � include/mach/addr-map.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_MACH_ADDR_MAP_H #define __ASM_MACH_ADDR_MAP_H /* * Chip Selects */ #define PXA_CS0_PHYS 0x00000000 #define PXA_CS1_PHYS 0x04000000 #define PXA_CS2_PHYS 0x08000000 #define PXA_CS3_PHYS 0x0C000000 #define PXA_CS4_PHYS 0x10000000 #define PXA_CS5_PHYS 0x14000000 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ #define PXA3xx_CS2_PHYS 0x10000000 #define PXA3xx_CS3_PHYS 0x14000000 /* * Peripheral Bus */ #define PERIPH_PHYS 0x40000000 #define PERIPH_VIRT IOMEM(0xf2000000) #define PERIPH_SIZE 0x02000000 /* * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) */ #define PXA2XX_SMEMC_PHYS 0x48000000 #define PXA3XX_SMEMC_PHYS 0x4a000000 #define SMEMC_VIRT IOMEM(0xf6000000) #define SMEMC_SIZE 0x00100000 /* * Dynamic Memory Controller (only on PXA3xx) */ #define DMEMC_PHYS 0x48100000 #define DMEMC_VIRT IOMEM(0xf6100000) #define DMEMC_SIZE 0x00100000 /* * Reserved space for low level debug virtual addresses within * 0xf6200000..0xf6201000 */ /* * DFI Bus for NAND, PXA3xx only */ #define NAND_PHYS 0x43100000 #define NAND_VIRT IOMEM(0xf6300000) #define NAND_SIZE 0x00100000 /* * Internal Memory Controller (PXA27x and later) */ #define IMEMC_PHYS 0x58000000 #define IMEMC_VIRT IOMEM(0xfe000000) #define IMEMC_SIZE 0x00100000 #endif /* __ASM_MACH_ADDR_MAP_H */ PK ! c}� k k include/mach/palmld.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * GPIOs and interrupts for Palm LifeDrive Handheld Computer * * Authors: Alex Osborne <ato@meshy.org> * Marek Vasut <marek.vasut@gmail.com> */ #ifndef _INCLUDE_PALMLD_H_ #define _INCLUDE_PALMLD_H_ #include "irqs.h" /* PXA_GPIO_TO_IRQ */ /** HERE ARE GPIOs **/ /* GPIOs */ #define GPIO_NR_PALMLD_GPIO_RESET 1 #define GPIO_NR_PALMLD_POWER_DETECT 4 #define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10 #define GPIO_NR_PALMLD_POWER_SWITCH 12 #define GPIO_NR_PALMLD_EARPHONE_DETECT 13 #define GPIO_NR_PALMLD_LOCK_SWITCH 15 /* SD/MMC */ #define GPIO_NR_PALMLD_SD_DETECT_N 14 #define GPIO_NR_PALMLD_SD_POWER 114 #define GPIO_NR_PALMLD_SD_READONLY 116 /* TOUCHSCREEN */ #define GPIO_NR_PALMLD_WM9712_IRQ 27 /* IRDA */ #define GPIO_NR_PALMLD_IR_DISABLE 108 /* LCD/BACKLIGHT */ #define GPIO_NR_PALMLD_BL_POWER 19 #define GPIO_NR_PALMLD_LCD_POWER 96 /* LCD BORDER */ #define GPIO_NR_PALMLD_BORDER_SWITCH 21 #define GPIO_NR_PALMLD_BORDER_SELECT 22 /* BLUETOOTH */ #define GPIO_NR_PALMLD_BT_POWER 17 #define GPIO_NR_PALMLD_BT_RESET 83 /* PCMCIA (WiFi) */ #define GPIO_NR_PALMLD_PCMCIA_READY 38 #define GPIO_NR_PALMLD_PCMCIA_POWER 36 #define GPIO_NR_PALMLD_PCMCIA_RESET 81 /* LEDs */ #define GPIO_NR_PALMLD_LED_GREEN 52 #define GPIO_NR_PALMLD_LED_AMBER 94 /* IDE */ #define GPIO_NR_PALMLD_IDE_RESET 98 #define GPIO_NR_PALMLD_IDE_PWEN 115 /* USB */ #define GPIO_NR_PALMLD_USB_DETECT_N 3 #define GPIO_NR_PALMLD_USB_READY 86 #define GPIO_NR_PALMLD_USB_RESET 88 #define GPIO_NR_PALMLD_USB_INT 106 #define GPIO_NR_PALMLD_USB_POWER 118 /* 20, 53 and 86 are usb related too */ /* INTERRUPTS */ #define IRQ_GPIO_PALMLD_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET) #define IRQ_GPIO_PALMLD_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N) #define IRQ_GPIO_PALMLD_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ) #define IRQ_GPIO_PALMLD_IDE_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ) /** HERE ARE INIT VALUES **/ /* IO mappings */ #define PALMLD_USB_PHYS PXA_CS2_PHYS #define PALMLD_USB_VIRT 0xf0000000 #define PALMLD_USB_SIZE 0x00100000 #define PALMLD_IDE_PHYS 0x20000000 #define PALMLD_IDE_VIRT 0xf1000000 #define PALMLD_IDE_SIZE 0x00100000 #define PALMLD_PHYS_IO_START 0x40000000 #define PALMLD_STR_BASE 0xa0200000 /* BATTERY */ #define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ #define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ #define PALMLD_BAT_MAX_CURRENT 0 /* unknown */ #define PALMLD_BAT_MIN_CURRENT 0 /* unknown */ #define PALMLD_BAT_MAX_CHARGE 1 /* unknown */ #define PALMLD_BAT_MIN_CHARGE 1 /* unknown */ #define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */ #define PALMLD_BAT_MEASURE_DELAY (HZ * 1) /* BACKLIGHT */ #define PALMLD_MAX_INTENSITY 0xFE #define PALMLD_DEFAULT_INTENSITY 0x7E #define PALMLD_LIMIT_MASK 0x7F #define PALMLD_PRESCALER 0x3F #define PALMLD_PERIOD_NS 3500 #endif PK ! �L�� � include/mach/balloon3.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/include/asm-arm/arch-pxa/balloon3.h * * Authors: Nick Bane and Wookey * Created: Oct, 2005 * Copyright: Toby Churchill Ltd * Cribbed from mainstone.c, by Nicholas Pitre */ #ifndef ASM_ARCH_BALLOON3_H #define ASM_ARCH_BALLOON3_H #include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ enum balloon3_features { BALLOON3_FEATURE_OHCI, BALLOON3_FEATURE_MMC, BALLOON3_FEATURE_CF, BALLOON3_FEATURE_AUDIO, BALLOON3_FEATURE_TOPPOLY, }; #define BALLOON3_FPGA_PHYS PXA_CS4_PHYS #define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ #define BALLOON3_FPGA_LENGTH 0x01000000 #define BALLOON3_FPGA_SETnCLR (0x1000) /* FPGA / CPLD registers for CF socket */ #define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) #define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) /* FPGA / CPLD version register */ #define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c) /* FPGA / CPLD registers for NAND flash */ #define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) #define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) #define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) #define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014) #define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) /* fpga/cpld interrupt control register */ #define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C) #define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c) #define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000) #define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004) #define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c) /* CF Status Register bits (read-only) bits */ #define BALLOON3_CF_nIRQ (1 << 0) #define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1) /* CF Control Set Register bits / CF Control Clear Register bits (write-only) */ #define BALLOON3_CF_RESET (1 << 0) #define BALLOON3_CF_ENABLE (1 << 1) #define BALLOON3_CF_ADD_ENABLE (1 << 2) /* CF Interrupt sources */ #define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) #define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) /* NAND Control register */ #define BALLOON3_NAND_CONTROL_FLWP (1 << 7) #define BALLOON3_NAND_CONTROL_FLSE (1 << 6) #define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5) #define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4) #define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3) #define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2) #define BALLOON3_NAND_CONTROL_FLALE (1 << 1) #define BALLOON3_NAND_CONTROL_FLCLE (1 << 0) /* NAND Status register */ #define BALLOON3_NAND_STAT_RNB (1 << 0) /* NAND Control2 register */ #define BALLOON3_NAND_CONTROL2_16BIT (1 << 0) /* GPIOs for irqs */ #define BALLOON3_GPIO_AUX_NIRQ (94) #define BALLOON3_GPIO_CODEC_IRQ (95) /* Timer and Idle LED locations */ #define BALLOON3_GPIO_LED_NAND (9) #define BALLOON3_GPIO_LED_IDLE (10) /* backlight control */ #define BALLOON3_GPIO_RUN_BACKLIGHT (99) #define BALLOON3_GPIO_S0_CD (105) /* NAND */ #define BALLOON3_GPIO_RUN_NAND (102) /* PCF8574A Leds */ #define BALLOON3_PCF_GPIO_BASE 160 #define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0) #define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1) #define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2) #define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3) #define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4) #define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5) #define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6) #define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7) /* FPGA Interrupt Mask/Acknowledge Register */ #define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */ #define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */ /* CPLD (and FPGA) interface definitions */ #define CPLD_LCD0_DATA_SET 0x00 #define CPLD_LCD0_DATA_CLR 0x10 #define CPLD_LCD0_COMMAND_SET 0x01 #define CPLD_LCD0_COMMAND_CLR 0x11 #define CPLD_LCD1_DATA_SET 0x02 #define CPLD_LCD1_DATA_CLR 0x12 #define CPLD_LCD1_COMMAND_SET 0x03 #define CPLD_LCD1_COMMAND_CLR 0x13 #define CPLD_MISC_SET 0x07 #define CPLD_MISC_CLR 0x17 #define CPLD_MISC_LOON_NRESET_BIT 0 #define CPLD_MISC_LOON_UNSUSP_BIT 1 #define CPLD_MISC_RUN_5V_BIT 2 #define CPLD_MISC_CHG_D0_BIT 3 #define CPLD_MISC_CHG_D1_BIT 4 #define CPLD_MISC_DAC_NCS_BIT 5 #define CPLD_LCD_SET 0x08 #define CPLD_LCD_CLR 0x18 #define CPLD_LCD_BACKLIGHT_EN_0_BIT 0 #define CPLD_LCD_BACKLIGHT_EN_1_BIT 1 #define CPLD_LCD_LED_RED_BIT 4 #define CPLD_LCD_LED_GREEN_BIT 5 #define CPLD_LCD_NRESET_BIT 7 #define CPLD_LCD_RO_SET 0x09 #define CPLD_LCD_RO_CLR 0x19 #define CPLD_LCD_RO_LCD0_nWAIT_BIT 0 #define CPLD_LCD_RO_LCD1_nWAIT_BIT 1 #define CPLD_SERIAL_SET 0x0a #define CPLD_SERIAL_CLR 0x1a #define CPLD_SERIAL_GSM_RI_BIT 0 #define CPLD_SERIAL_GSM_CTS_BIT 1 #define CPLD_SERIAL_GSM_DTR_BIT 2 #define CPLD_SERIAL_LPR_CTS_BIT 3 #define CPLD_SERIAL_TC232_CTS_BIT 4 #define CPLD_SERIAL_TC232_DSR_BIT 5 #define CPLD_SROUTING_SET 0x0b #define CPLD_SROUTING_CLR 0x1b #define CPLD_SROUTING_MSP430_LPR 0 #define CPLD_SROUTING_MSP430_TC232 1 #define CPLD_SROUTING_MSP430_GSM 2 #define CPLD_SROUTING_LOON_LPR (0 << 4) #define CPLD_SROUTING_LOON_TC232 (1 << 4) #define CPLD_SROUTING_LOON_GSM (2 << 4) #define CPLD_AROUTING_SET 0x0c #define CPLD_AROUTING_CLR 0x1c #define CPLD_AROUTING_MIC2PHONE_BIT 0 #define CPLD_AROUTING_PHONE2INT_BIT 1 #define CPLD_AROUTING_PHONE2EXT_BIT 2 #define CPLD_AROUTING_LOONL2INT_BIT 3 #define CPLD_AROUTING_LOONL2EXT_BIT 4 #define CPLD_AROUTING_LOONR2PHONE_BIT 5 #define CPLD_AROUTING_LOONR2INT_BIT 6 #define CPLD_AROUTING_LOONR2EXT_BIT 7 /* Balloon3 Interrupts */ #define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) #define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ) #define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ) #define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) extern int balloon3_has(enum balloon3_features feature); #endif PK ! 8��M M include/mach/vpac270.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * GPIOs and interrupts for Voipac PXA270 * * Copyright (C) 2010 * Marek Vasut <marek.vasut@gmail.com> */ #ifndef _INCLUDE_VPAC270_H_ #define _INCLUDE_VPAC270_H_ #define GPIO1_VPAC270_USER_BTN 1 #define GPIO15_VPAC270_LED_ORANGE 15 #define GPIO81_VPAC270_BKL_ON 81 #define GPIO83_VPAC270_NL_ON 83 #define GPIO52_VPAC270_SD_READONLY 52 #define GPIO53_VPAC270_SD_DETECT_N 53 #define GPIO84_VPAC270_PCMCIA_CD 84 #define GPIO35_VPAC270_PCMCIA_RDY 35 #define GPIO107_VPAC270_PCMCIA_PPEN 107 #define GPIO11_VPAC270_PCMCIA_RESET 11 #define GPIO17_VPAC270_CF_CD 17 #define GPIO12_VPAC270_CF_RDY 12 #define GPIO16_VPAC270_CF_RESET 16 #define GPIO41_VPAC270_UDC_DETECT 41 #define GPIO114_VPAC270_ETH_IRQ 114 #define GPIO36_VPAC270_IDE_IRQ 36 #define GPIO113_VPAC270_TS_IRQ 113 #endif PK ! ���� � include/mach/palmtx.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * GPIOs and interrupts for Palm T|X Handheld Computer * * Based on palmld-gpio.h by Alex Osborne * * Authors: Marek Vasut <marek.vasut@gmail.com> * Cristiano P. <cristianop@users.sourceforge.net> * Jan Herman <2hp@seznam.cz> */ #ifndef _INCLUDE_PALMTX_H_ #define _INCLUDE_PALMTX_H_ #include "irqs.h" /* PXA_GPIO_TO_IRQ */ /** HERE ARE GPIOs **/ /* GPIOs */ #define GPIO_NR_PALMTX_GPIO_RESET 1 #define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */ #define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10 #define GPIO_NR_PALMTX_EARPHONE_DETECT 107 /* SD/MMC */ #define GPIO_NR_PALMTX_SD_DETECT_N 14 #define GPIO_NR_PALMTX_SD_POWER 114 /* probably */ #define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */ /* TOUCHSCREEN */ #define GPIO_NR_PALMTX_WM9712_IRQ 27 /* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ #define GPIO_NR_PALMTX_IR_DISABLE 40 /* USB */ #define GPIO_NR_PALMTX_USB_DETECT_N 13 #define GPIO_NR_PALMTX_USB_PULLUP 93 /* LCD/BACKLIGHT */ #define GPIO_NR_PALMTX_BL_POWER 84 #define GPIO_NR_PALMTX_LCD_POWER 96 /* LCD BORDER */ #define GPIO_NR_PALMTX_BORDER_SWITCH 98 #define GPIO_NR_PALMTX_BORDER_SELECT 22 /* BLUETOOTH */ #define GPIO_NR_PALMTX_BT_POWER 17 #define GPIO_NR_PALMTX_BT_RESET 83 /* PCMCIA (WiFi) */ #define GPIO_NR_PALMTX_PCMCIA_POWER1 94 #define GPIO_NR_PALMTX_PCMCIA_POWER2 108 #define GPIO_NR_PALMTX_PCMCIA_RESET 79 #define GPIO_NR_PALMTX_PCMCIA_READY 116 /* NAND Flash ... this GPIO may be incorrect! */ #define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 /* INTERRUPTS */ #define IRQ_GPIO_PALMTX_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N) #define IRQ_GPIO_PALMTX_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ) #define IRQ_GPIO_PALMTX_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT) #define IRQ_GPIO_PALMTX_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET) /** HERE ARE INIT VALUES **/ /* Various addresses */ #define PALMTX_PCMCIA_PHYS 0x28000000 #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) #define PALMTX_PCMCIA_SIZE 0x100000 #define PALMTX_PHYS_RAM_START 0xa0000000 #define PALMTX_PHYS_IO_START 0x40000000 #define PALMTX_STR_BASE 0xa0200000 #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ #define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ #define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24)) #define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25)) #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) /* TOUCHSCREEN */ #define AC97_LINK_FRAME 21 /* BATTERY */ #define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ #define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ #define PALMTX_BAT_MAX_CURRENT 0 /* unknown */ #define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ #define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ #define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ #define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */ #define PALMTX_BAT_MEASURE_DELAY (HZ * 1) /* BACKLIGHT */ #define PALMTX_MAX_INTENSITY 0xFE #define PALMTX_DEFAULT_INTENSITY 0x7E #define PALMTX_LIMIT_MASK 0x7F #define PALMTX_PRESCALER 0x3F #define PALMTX_PERIOD_NS 3500 #endif PK ! _��� include/mach/tosa.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Hardware specific definitions for Sharp SL-C6000x series of PDAs * * Copyright (c) 2005 Dirk Opfer * * Based on Sharp's 2.4 kernel patches */ #ifndef _ASM_ARCH_TOSA_H_ #define _ASM_ARCH_TOSA_H_ 1 #include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ /* TOSA Chip selects */ #define TOSA_LCDC_PHYS PXA_CS4_PHYS /* Internel Scoop */ #define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000) /* Jacket Scoop */ #define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) #define TOSA_NR_IRQS (IRQ_BOARD_START + TC6393XB_NR_IRQS) /* * SCOOP2 internal GPIOs */ #define TOSA_SCOOP_GPIO_BASE PXA_NR_BUILTIN_GPIO #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 #define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1) #define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) #define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) #define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) #define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 #define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6) #define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7) #define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 /* GPIO Direction 1 : output mode / 0:input mode */ #define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \ TOSA_SCOOP_AUD_PWR_ON) /* * SCOOP2 jacket GPIOs */ #define TOSA_SCOOP_JC_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) #define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0) #define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) #define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) #define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) #define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4) #define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5) #define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 #define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) #define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 /* GPIO Direction 1 : output mode / 0:input mode */ #define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL) /* * TC6393XB GPIOs */ #define TOSA_TC6393XB_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 2 * 12) #define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) #define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) #define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3) #define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4) #define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6) #define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7) #define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9) #define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10) #define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11) #define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12) #define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14) #define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15) /* * PXA GPIOs */ #define TOSA_GPIO_POWERON (0) #define TOSA_GPIO_RESET (1) #define TOSA_GPIO_AC_IN (2) #define TOSA_GPIO_RECORD_BTN (3) #define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */ #define TOSA_GPIO_USB_IN (5) #define TOSA_GPIO_JACKET_DETECT (7) #define TOSA_GPIO_nSD_DETECT (9) #define TOSA_GPIO_nSD_INT (10) #define TOSA_GPIO_TC6393XB_CLK (11) #define TOSA_GPIO_BAT1_CRG (12) #define TOSA_GPIO_CF_CD (13) #define TOSA_GPIO_BAT0_CRG (14) #define TOSA_GPIO_TC6393XB_INT (15) #define TOSA_GPIO_BAT0_LOW (17) #define TOSA_GPIO_TC6393XB_RDY (18) #define TOSA_GPIO_ON_RESET (19) #define TOSA_GPIO_EAR_IN (20) #define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ #define TOSA_GPIO_ON_KEY (22) #define TOSA_GPIO_VGA_LINE (27) #define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ #define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ #define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ #define TOSA_GPIO_IRDA_TX (47) #define TOSA_GPIO_TG_SPI_SCLK (81) #define TOSA_GPIO_TG_SPI_CS (82) #define TOSA_GPIO_TG_SPI_MOSI (83) #define TOSA_GPIO_BAT1_LOW (84) #define TOSA_GPIO_HP_IN GPIO_EAR_IN #define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW #define TOSA_KEY_STROBE_NUM (11) #define TOSA_KEY_SENSE_NUM (7) #define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000) #define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f) #define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0) #define TOSA_GPIO_ALL_SENSE_RSHIFT (5) #define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a)) #define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a)) #define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000) #define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff) #define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00) #define TOSA_GPIO_KEY_SENSE(a) (69+(a)) #define TOSA_GPIO_KEY_STROBE(a) (58+(a)) /* * Interrupts */ #define TOSA_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP) #define TOSA_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN) #define TOSA_IRQ_GPIO_RECORD_BTN PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN) #define TOSA_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC) #define TOSA_IRQ_GPIO_USB_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN) #define TOSA_IRQ_GPIO_JACKET_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT) #define TOSA_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT) #define TOSA_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT) #define TOSA_IRQ_GPIO_BAT1_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG) #define TOSA_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD) #define TOSA_IRQ_GPIO_BAT0_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG) #define TOSA_IRQ_GPIO_TC6393XB_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT) #define TOSA_IRQ_GPIO_BAT0_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW) #define TOSA_IRQ_GPIO_EAR_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN) #define TOSA_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ) #define TOSA_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY) #define TOSA_IRQ_GPIO_VGA_LINE PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE) #define TOSA_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT) #define TOSA_IRQ_GPIO_JC_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ) #define TOSA_IRQ_GPIO_BAT_LOCKED PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED) #define TOSA_IRQ_GPIO_BAT1_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW) #define TOSA_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(69+(a)) #define TOSA_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW) #define TOSA_KEY_SYNC KEY_102ND /* ??? */ #ifndef CONFIG_TOSA_USE_EXT_KEYCODES #define TOSA_KEY_RECORD KEY_YEN #define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA #define TOSA_KEY_CANCEL KEY_ESC #define TOSA_KEY_CENTER KEY_HIRAGANA #define TOSA_KEY_OK KEY_HENKAN #define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA #define TOSA_KEY_HOMEPAGE KEY_HANGEUL #define TOSA_KEY_LIGHT KEY_MUHENKAN #define TOSA_KEY_MENU KEY_HANJA #define TOSA_KEY_FN KEY_RIGHTALT #define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU #else #define TOSA_KEY_RECORD KEY_RECORD #define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK #define TOSA_KEY_CANCEL KEY_CANCEL #define TOSA_KEY_CENTER KEY_SELECT /* ??? */ #define TOSA_KEY_OK KEY_OK #define TOSA_KEY_CALENDAR KEY_CALENDAR #define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE #define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE #define TOSA_KEY_MENU KEY_MENU #define TOSA_KEY_FN KEY_FN #define TOSA_KEY_MAIL KEY_MAIL #endif #endif /* _ASM_ARCH_TOSA_H_ */ PK ! �v�L L include/mach/corgi.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Hardware specific definitions for SL-C7xx series of PDAs * * Copyright (c) 2004-2005 Richard Purdie * * Based on Sharp's 2.4 kernel patches */ #ifndef __ASM_ARCH_CORGI_H #define __ASM_ARCH_CORGI_H 1 #include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ /* * Corgi (Non Standard) GPIO Definitions */ #define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */ #define CORGI_GPIO_AC_IN (1) /* Charger Detection */ #define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */ #define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */ #define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */ #define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */ #define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */ #define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */ #define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */ #define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */ #define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */ #define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */ #define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */ #define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */ #define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ #define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ #define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ #define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */ #define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ #define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ #define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ #define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */ #define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */ #define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */ #define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */ /* * Corgi Keyboard Definitions */ #define CORGI_KEY_STROBE_NUM (12) #define CORGI_KEY_SENSE_NUM (8) #define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc) #define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000) #define CORGI_GPIO_HIGH_SENSE_RSHIFT (26) #define CORGI_GPIO_LOW_SENSE_BIT (0x00000003) #define CORGI_GPIO_LOW_SENSE_LSHIFT (6) #define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a)) #define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a)) #define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0) #define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000) #define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f) #define CORGI_GPIO_KEY_SENSE(a) (58+(a)) #define CORGI_GPIO_KEY_STROBE(a) (66+(a)) /* * Corgi Interrupts */ #define CORGI_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(0) #define CORGI_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) #define CORGI_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(3) #define CORGI_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(4) #define CORGI_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) #define CORGI_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) #define CORGI_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(10) #define CORGI_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(11) #define CORGI_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) #define CORGI_IRQ_GPIO_CHRG_FULL PXA_GPIO_TO_IRQ(16) /* Battery fully charged */ #define CORGI_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) #define CORGI_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */ /* * Corgi SCOOP GPIOs and Config */ #define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11 #define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */ #define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */ #define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14 #define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15 #define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16 #define CORGI_SCP_APM_ON SCOOP_GPCR_PA17 #define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18 #define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19 #define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \ CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \ CORGI_SCP_MIC_BIAS ) #define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) #define CORGI_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0) #define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */ #define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */ #define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3) #define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4) #define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5) #define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6) #define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7) #define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8) #endif /* __ASM_ARCH_CORGI_H */ PK ! ��J� � include/mach/uncompress.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/uncompress.h * * Author: Nicolas Pitre * Copyright: (C) 2001 MontaVista Software Inc. */ #include <linux/serial_reg.h> #include <asm/mach-types.h> #define FFUART_BASE (0x40100000) #define BTUART_BASE (0x40200000) #define STUART_BASE (0x40700000) unsigned long uart_base; unsigned int uart_shift; unsigned int uart_is_pxa; static inline unsigned char uart_read(int offset) { return *(volatile unsigned char *)(uart_base + (offset << uart_shift)); } static inline void uart_write(unsigned char val, int offset) { *(volatile unsigned char *)(uart_base + (offset << uart_shift)) = val; } static inline int uart_is_enabled(void) { /* assume enabled by default for non-PXA uarts */ return uart_is_pxa ? uart_read(UART_IER) & UART_IER_UUE : 1; } static inline void putc(char c) { if (!uart_is_enabled()) return; while (!(uart_read(UART_LSR) & UART_LSR_THRE)) barrier(); uart_write(c, UART_TX); } /* * This does not append a newline */ static inline void flush(void) { } static inline void arch_decomp_setup(void) { /* initialize to default */ uart_base = FFUART_BASE; uart_shift = 2; uart_is_pxa = 1; if (machine_is_littleton() || machine_is_intelmote2() || machine_is_csb726() || machine_is_stargate2() || machine_is_cm_x300() || machine_is_balloon3()) uart_base = STUART_BASE; if (machine_is_arcom_zeus()) { uart_base = 0x10000000; /* nCS4 */ uart_shift = 1; uart_is_pxa = 0; } } PK ! V��_/ / include/mach/irqs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/irqs.h * * Author: Nicolas Pitre * Created: Jun 15, 2001 * Copyright: MontaVista Software Inc. */ #ifndef __ASM_MACH_IRQS_H #define __ASM_MACH_IRQS_H #include <asm/irq.h> #define PXA_ISA_IRQ(x) (x) #define PXA_IRQ(x) (NR_IRQS_LEGACY + (x)) #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ #define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ #define IRQ_USB PXA_IRQ(11) /* USB Service */ #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ #define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ #define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ #define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ #define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ #define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ #define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ #define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ #define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ #define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ #define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ #define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ #define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ #define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ #define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */ #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ #define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ #define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ #define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ #define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ #define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ #define PXA_GPIO_IRQ_BASE PXA_IRQ(96) #define PXA_NR_BUILTIN_GPIO (192) #define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) /* * The following interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use * these. * By default, no board IRQ is reserved. It should be finished in * custom board since sparse IRQ is already enabled. */ #define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO) #define PXA_NR_IRQS (IRQ_BOARD_START) #ifndef __ASSEMBLY__ struct irq_data; struct pt_regs; void pxa_mask_irq(struct irq_data *); void pxa_unmask_irq(struct irq_data *); void icip_handle_irq(struct pt_regs *); void ichp_handle_irq(struct pt_regs *); void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int)); #endif #endif /* __ASM_MACH_IRQS_H */ PK ! Éc c include/mach/magician.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * GPIO and IRQ definitions for HTC Magician PDA phones * * Copyright (c) 2007 Philipp Zabel */ #ifndef _MAGICIAN_H_ #define _MAGICIAN_H_ #include <linux/gpio.h> #include <mach/irqs.h> /* * PXA GPIOs */ #define GPIO0_MAGICIAN_KEY_POWER 0 #define GPIO9_MAGICIAN_UNKNOWN 9 #define GPIO10_MAGICIAN_GSM_IRQ 10 #define GPIO11_MAGICIAN_GSM_OUT1 11 #define GPIO13_MAGICIAN_CPLD_IRQ 13 #define GPIO14_MAGICIAN_TSC2046_CS 14 #define GPIO18_MAGICIAN_UNKNOWN 18 #define GPIO22_MAGICIAN_VIBRA_EN 22 #define GPIO26_MAGICIAN_GSM_POWER 26 #define GPIO27_MAGICIAN_USBC_PUEN 27 #define GPIO30_MAGICIAN_BQ24022_nCHARGE_EN 30 #define GPIO37_MAGICIAN_KEY_HANGUP 37 #define GPIO38_MAGICIAN_KEY_CONTACTS 38 #define GPIO40_MAGICIAN_GSM_OUT2 40 #define GPIO48_MAGICIAN_UNKNOWN 48 #define GPIO56_MAGICIAN_UNKNOWN 56 #define GPIO57_MAGICIAN_CAM_RESET 57 #define GPIO75_MAGICIAN_SAMSUNG_POWER 75 #define GPIO83_MAGICIAN_nIR_EN 83 #define GPIO86_MAGICIAN_GSM_RESET 86 #define GPIO87_MAGICIAN_GSM_SELECT 87 #define GPIO90_MAGICIAN_KEY_CALENDAR 90 #define GPIO91_MAGICIAN_KEY_CAMERA 91 #define GPIO93_MAGICIAN_KEY_UP 93 #define GPIO94_MAGICIAN_KEY_DOWN 94 #define GPIO95_MAGICIAN_KEY_LEFT 95 #define GPIO96_MAGICIAN_KEY_RIGHT 96 #define GPIO97_MAGICIAN_KEY_ENTER 97 #define GPIO98_MAGICIAN_KEY_RECORD 98 #define GPIO99_MAGICIAN_HEADPHONE_IN 99 #define GPIO100_MAGICIAN_KEY_VOL_UP 100 #define GPIO101_MAGICIAN_KEY_VOL_DOWN 101 #define GPIO102_MAGICIAN_KEY_PHONE 102 #define GPIO103_MAGICIAN_LED_KP 103 #define GPIO104_MAGICIAN_LCD_VOFF_EN 104 #define GPIO105_MAGICIAN_LCD_VON_EN 105 #define GPIO106_MAGICIAN_LCD_DCDC_NRESET 106 #define GPIO107_MAGICIAN_DS1WM_IRQ 107 #define GPIO108_MAGICIAN_GSM_READY 108 #define GPIO114_MAGICIAN_UNKNOWN 114 #define GPIO115_MAGICIAN_nPEN_IRQ 115 #define GPIO116_MAGICIAN_nCAM_EN 116 #define GPIO119_MAGICIAN_UNKNOWN 119 #define GPIO120_MAGICIAN_UNKNOWN 120 /* * CPLD IRQs */ #define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) #define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) #define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3) #define MAGICIAN_NR_IRQS (IRQ_BOARD_START + 8) /* * CPLD EGPIOs */ #define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO #define MAGICIAN_EGPIO(reg,bit) \ (MAGICIAN_EGPIO_BASE + 8*reg + bit) /* output */ #define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2) #define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5) #define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6) #define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7) #define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0) #define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1) #define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2) #define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3) #define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4) #define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5) #define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6) #define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7) #define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0) #define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1) #define EGPIO_MAGICIAN_IR_RX_SHUTDOWN MAGICIAN_EGPIO(2, 2) #define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3) #define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4) #define EGPIO_MAGICIAN_BQ24022_ISET2 MAGICIAN_EGPIO(2, 5) #define EGPIO_MAGICIAN_NICD_CHARGE MAGICIAN_EGPIO(2, 6) #define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7) /* input */ /* USB or AC charger type */ #define EGPIO_MAGICIAN_CABLE_TYPE MAGICIAN_EGPIO(4, 0) /* * Vbus is detected * FIXME behaves like (6,3), may differ for host/device */ #define EGPIO_MAGICIAN_CABLE_VBUS MAGICIAN_EGPIO(4, 1) #define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0) #define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1) #define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2) #define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3) #define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4) #define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1) /* FIXME behaves like (4,1), may differ for host/device */ #define EGPIO_MAGICIAN_CABLE_INSERTED MAGICIAN_EGPIO(6, 3) #endif /* _MAGICIAN_H_ */ PK ! S_�: : include/mach/bitfield.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * FILE bitfield.h * * Version 1.1 * Author Copyright (c) Marc A. Viredaz, 1998 * DEC Western Research Laboratory, Palo Alto, CA * Date April 1998 (April 1997) * System Advanced RISC Machine (ARM) * Language C or ARM Assembly * Purpose Definition of macros to operate on bit fields. */ #ifndef __BITFIELD_H #define __BITFIELD_H #ifndef __ASSEMBLY__ #define UData(Data) ((unsigned long) (Data)) #else #define UData(Data) (Data) #endif /* * MACRO: Fld * * Purpose * The macro "Fld" encodes a bit field, given its size and its shift value * with respect to bit 0. * * Note * A more intuitive way to encode bit fields would have been to use their * mask. However, extracting size and shift value information from a bit * field's mask is cumbersome and might break the assembler (255-character * line-size limit). * * Input * Size Size of the bit field, in number of bits. * Shft Shift value of the bit field with respect to bit 0. * * Output * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) /* * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit * * Purpose * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return * the size, shift value, mask, aligned mask, and first bit of a * bit field. * * Input * Field Encoded bit field (using the macro "Fld"). * * Output * FSize Size of the bit field, in number of bits. * FShft Shift value of the bit field with respect to bit 0. * FMsk Mask for the bit field. * FAlnMsk Mask for the bit field, aligned on bit 0. * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) #define FShft(Field) ((Field) & 0x0000FFFF) #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) #define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) #define F1stBit(Field) (UData (1) << FShft (Field)) /* * MACRO: FInsrt * * Purpose * The macro "FInsrt" inserts a value into a bit field by shifting the * former appropriately. * * Input * Value Bit-field value. * Field Encoded bit field (using the macro "Fld"). * * Output * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ (UData (Value) << FShft (Field)) /* * MACRO: FExtr * * Purpose * The macro "FExtr" extracts the value of a bit field by masking and * shifting it appropriately. * * Input * Data Data containing the bit-field to be extracted. * Field Encoded bit field (using the macro "Fld"). * * Output * FExtr Bit-field value. */ #define FExtr(Data, Field) \ ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) #endif /* __BITFIELD_H */ PK ! �0�A A include/mach/hx4700.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * GPIO and IRQ definitions for HP iPAQ hx4700 * * Copyright (c) 2008 Philipp Zabel */ #ifndef _HX4700_H_ #define _HX4700_H_ #include <linux/gpio.h> #include <linux/mfd/asic3.h> #include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ #define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO #define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) #define HX4700_NR_IRQS (IRQ_BOARD_START + 70) /* * PXA GPIOs */ #define GPIO0_HX4700_nKEY_POWER 0 #define GPIO12_HX4700_ASIC3_IRQ 12 #define GPIO13_HX4700_W3220_IRQ 13 #define GPIO14_HX4700_nWLAN_IRQ 14 #define GPIO18_HX4700_RDY 18 #define GPIO22_HX4700_LCD_RL 22 #define GPIO27_HX4700_CODEC_ON 27 #define GPIO32_HX4700_RS232_ON 32 #define GPIO52_HX4700_CPU_nBATT_FAULT 52 #define GPIO58_HX4700_TSC2046_nPENIRQ 58 #define GPIO59_HX4700_LCD_PC1 59 #define GPIO60_HX4700_CF_RNB 60 #define GPIO61_HX4700_W3220_nRESET 61 #define GPIO62_HX4700_LCD_nRESET 62 #define GPIO63_HX4700_CPU_SS_nRESET 63 #define GPIO65_HX4700_TSC2046_PEN_PU 65 #define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66 #define GPIO67_HX4700_EUART_PS 67 #define GPIO70_HX4700_LCD_SLIN1 70 #define GPIO71_HX4700_ASIC3_nRESET 71 #define GPIO72_HX4700_BQ24022_nCHARGE_EN 72 #define GPIO73_HX4700_LCD_UD_1 73 #define GPIO75_HX4700_EARPHONE_nDET 75 #define GPIO76_HX4700_USBC_PUEN 76 #define GPIO81_HX4700_CPU_GP_nRESET 81 #define GPIO82_HX4700_EUART_RESET 82 #define GPIO83_HX4700_WLAN_nRESET 83 #define GPIO84_HX4700_LCD_SQN 84 #define GPIO85_HX4700_nPCE1 85 #define GPIO88_HX4700_TSC2046_CS 88 #define GPIO91_HX4700_FLASH_VPEN 91 #define GPIO92_HX4700_HP_DRIVER 92 #define GPIO93_HX4700_EUART_INT 93 #define GPIO94_HX4700_KEY_MAIL 94 #define GPIO95_HX4700_BATT_OFF 95 #define GPIO96_HX4700_BQ24022_ISET2 96 #define GPIO97_HX4700_nBL_DETECT 97 #define GPIO99_HX4700_KEY_CONTACTS 99 #define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */ #define GPIO102_HX4700_SYNAPTICS_POWER_ON 102 #define GPIO103_HX4700_SYNAPTICS_INT 103 #define GPIO105_HX4700_nIR_ON 105 #define GPIO106_HX4700_CPU_BT_nRESET 106 #define GPIO107_HX4700_SPK_nSD 107 #define GPIO109_HX4700_CODEC_nPDN 109 #define GPIO110_HX4700_LCD_LVDD_3V3_ON 110 #define GPIO111_HX4700_LCD_AVDD_3V3_ON 111 #define GPIO112_HX4700_LCD_N2V7_7V3_ON 112 #define GPIO114_HX4700_CF_RESET 114 #define GPIO116_HX4700_CPU_HW_nRESET 116 /* * ASIC3 GPIOs */ #define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32) #define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48) #define GPIOC0_LED_RED (GPIOC_BASE + 0) #define GPIOC1_LED_GREEN (GPIOC_BASE + 1) #define GPIOC2_LED_BLUE (GPIOC_BASE + 2) #define GPIOC3_nSD_CS (GPIOC_BASE + 3) #define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */ #define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */ #define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */ #define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */ #define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */ #define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */ #define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */ #define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */ #define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */ #define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */ #define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */ #define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */ #define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */ #define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1) #define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2) #define GPIOD3_nKEY_HOME (GPIOD_BASE + 3) #define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */ #define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */ #define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6) #define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7) #define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */ #define GPIOD9_nAC_IN (GPIOD_BASE + 9) #define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */ #define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */ #define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */ #define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */ #define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14) #define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */ /* * EGPIOs */ #define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */ #define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */ #define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */ #define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */ #define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */ #define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */ #define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */ #define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */ #define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */ #endif /* _HX4700_H_ */ PK ! ���# �# include/mach/regs-lcd.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_REGS_LCD_H #define __ASM_ARCH_REGS_LCD_H #include <mach/bitfield.h> /* * LCD Controller Registers and Bits Definitions */ #define LCCR0 (0x000) /* LCD Controller Control Register 0 */ #define LCCR1 (0x004) /* LCD Controller Control Register 1 */ #define LCCR2 (0x008) /* LCD Controller Control Register 2 */ #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ #define LCSR (0x038) /* LCD Controller Status Register 0 */ #define LCSR1 (0x034) /* LCD Controller Status Register 1 */ #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ #define TMEDCR (0x044) /* TMED Control Register */ #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ #define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ #define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ #define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ #define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ #define CMDCR (0x100) /* Command Control Register */ #define PRSR (0x104) /* Panel Read Status Register */ #define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) #define LCCR3_PDFOR_0 (0 << 30) #define LCCR3_PDFOR_1 (1 << 30) #define LCCR3_PDFOR_2 (2 << 30) #define LCCR3_PDFOR_3 (3 << 30) #define LCCR4_PAL_FOR_0 (0 << 15) #define LCCR4_PAL_FOR_1 (1 << 15) #define LCCR4_PAL_FOR_2 (2 << 15) #define LCCR4_PAL_FOR_3 (3 << 15) #define LCCR4_PAL_FOR_MASK (3 << 15) #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ #define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ #define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ #define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ #define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ #define LCCR0_SFM (1 << 4) /* Start of frame mask */ #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ #define LCCR0_EFM (1 << 6) /* End of Frame mask */ #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ #define LCCR0_DIS (1 << 10) /* LCD Disable */ #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ #define LCCR0_PDD_S 12 #define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ #define LCCR0_LCDT (1 << 22) /* LCD panel type */ #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ #define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW)) #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW)) #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW)) #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP)) #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ #define LCCR3_API_S 16 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ #define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) #define LCCR3_ACB Fld (8, 8) /* AC Bias */ #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) #define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ #define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ #define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ #define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ #define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ #define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ #define LCSR_LDD (1 << 0) /* LCD Disable Done */ #define LCSR_SOF (1 << 1) /* Start of frame */ #define LCSR_BER (1 << 2) /* Bus error */ #define LCSR_ABC (1 << 3) /* AC Bias count */ #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ #define LCSR_OU (1 << 6) /* output FIFO underrun */ #define LCSR_QD (1 << 7) /* quick disable */ #define LCSR_EOF (1 << 8) /* end of frame */ #define LCSR_BS (1 << 9) /* branch status */ #define LCSR_SINT (1 << 10) /* subsequent interrupt */ #define LCSR_RD_ST (1 << 11) /* read status */ #define LCSR_CMD_INT (1 << 12) /* command interrupt */ #define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ #define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ #define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ #define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ /* overlay control registers */ #define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ #define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ #define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ #define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ #define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ #define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ #define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ /* smartpanel related */ #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ #define PRSR_A0 (1 << 8) /* Read Data Source */ #define PRSR_ST_OK (1 << 9) /* Status OK */ #define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ #define SMART_CMD_A0 (0x1 << 8) #define SMART_CMD_READ_STATUS_REG (0x0 << 9) #define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) #define SMART_CMD_WRITE_COMMAND (0x1 << 9) #define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) #define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) #define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) #define SMART_CMD_NOOP (0x4 << 9) #define SMART_CMD_INTERRUPT (0x5 << 9) #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) /* SMART_DELAY() is introduced for software controlled delay primitive which * can be inserted between command sequences, unused command 0x6 is used here * and delay ranges from 0ms ~ 255ms */ #define SMART_CMD_DELAY (0x6 << 9) #define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) #endif /* __ASM_ARCH_REGS_LCD_H */ PK ! ���Y" Y" include/mach/pxa3xx-regs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h * * PXA3xx specific register definitions * * Copyright (C) 2007 Marvell International Ltd. */ #ifndef __ASM_ARCH_PXA3XX_REGS_H #define __ASM_ARCH_PXA3XX_REGS_H #include <mach/hardware.h> /* * Oscillator Configuration Register (OSCC) */ #define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */ #define OSCC_PEN (1 << 11) /* 13MHz POUT */ /* * Service Power Management Unit (MPMU) */ #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) /* * Slave Power Management Unit */ #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ #define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ #define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ #define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ #define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ #define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ /* * Application Subsystem Configuration bits. */ #define ASCR_RDH (1 << 31) #define ASCR_D1S (1 << 2) #define ASCR_D2S (1 << 1) #define ASCR_D3S (1 << 0) /* * Application Reset Status bits. */ #define ARSR_GPR (1 << 3) #define ARSR_LPMR (1 << 2) #define ARSR_WDT (1 << 1) #define ARSR_HWR (1 << 0) /* * Application Subsystem Wake-Up bits. */ #define ADXER_WRTC (1 << 31) /* RTC */ #define ADXER_WOST (1 << 30) /* OS Timer */ #define ADXER_WTSI (1 << 29) /* Touchscreen */ #define ADXER_WUSBH (1 << 28) /* USB host */ #define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ #define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ #define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ #define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ #define ADXER_WKP (1 << 21) /* Keypad */ #define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ #define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ #define ADXER_WOTG (1 << 16) /* USBOTG input */ #define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ #define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ #define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ #define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ #define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ #define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ #define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ #define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ #define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ #define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ #define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ #define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ #define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ #define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ #define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ #define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ /* * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. */ #define ADXR_L2 (1 << 8) #define ADXR_R5 (1 << 5) #define ADXR_R4 (1 << 4) #define ADXR_R3 (1 << 3) #define ADXR_R2 (1 << 2) #define ADXR_R1 (1 << 1) #define ADXR_R0 (1 << 0) /* * Values for PWRMODE CP15 register */ #define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ #define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ #define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ #define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ #define PXA3xx_PM_S0D0C1 0x01 /* * Application Subsystem Clock */ #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ #define CKENB __REG(0x41340010) /* B Clock Enable Register */ #define CKENC __REG(0x41340024) /* C Clock Enable Register */ #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ #define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ #define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ #define ACCR_SMCFS(x) (((x) & 0x7) << 23) #define ACCR_SFLFS(x) (((x) & 0x3) << 18) #define ACCR_XSPCLK(x) (((x) & 0x3) << 16) #define ACCR_HSS(x) (((x) & 0x3) << 14) #define ACCR_DMCFS(x) (((x) & 0x3) << 12) #define ACCR_XN(x) (((x) & 0x7) << 8) #define ACCR_XL(x) ((x) & 0x1f) /* * Clock Enable Bit */ #define CKEN_LCD 1 /* < LCD Clock Enable */ #define CKEN_USBH 2 /* < USB host clock enable */ #define CKEN_CAMERA 3 /* < Camera interface clock enable */ #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ #define CKEN_SMC 9 /* < Static Memory Controller clock enable */ #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ #define CKEN_BOOT 11 /* < Boot rom clock enable */ #define CKEN_MMC1 12 /* < MMC1 Clock enable */ #define CKEN_MMC2 13 /* < MMC2 clock enable */ #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ #define CKEN_CIR 15 /* < Consumer IR Clock Enable */ #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ #define CKEN_TPM 19 /* < TPM clock enable */ #define CKEN_UDC 20 /* < UDC clock enable */ #define CKEN_BTUART 21 /* < BTUART clock enable */ #define CKEN_FFUART 22 /* < FFUART clock enable */ #define CKEN_STUART 23 /* < STUART clock enable */ #define CKEN_AC97 24 /* < AC97 clock enable */ #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ #define CKEN_SSP1 26 /* < SSP1 clock enable */ #define CKEN_SSP2 27 /* < SSP2 clock enable */ #define CKEN_SSP3 28 /* < SSP3 clock enable */ #define CKEN_SSP4 29 /* < SSP4 clock enable */ #define CKEN_MSL0 30 /* < MSL0 clock enable */ #define CKEN_PWM0 32 /* < PWM[0] clock enable */ #define CKEN_PWM1 33 /* < PWM[1] clock enable */ #define CKEN_I2C 36 /* < I2C clock enable */ #define CKEN_INTC 38 /* < Interrupt controller clock enable */ #define CKEN_GPIO 39 /* < GPIO clock enable */ #define CKEN_1WIRE 40 /* < 1-wire clock enable */ #define CKEN_HSIO2 41 /* < HSIO2 clock enable */ #define CKEN_MINI_IM 48 /* < Mini-IM */ #define CKEN_MINI_LCD 49 /* < Mini LCD */ #define CKEN_MMC3 5 /* < MMC3 Clock Enable */ #define CKEN_MVED 43 /* < MVED clock enable */ /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ #define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ #define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ #endif /* __ASM_ARCH_PXA3XX_REGS_H */ PK ! M}ɡn n include/mach/mfp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/mfp.h * * Multi-Function Pin Definitions * * Copyright (C) 2007 Marvell International Ltd. * * 2007-8-21: eric miao <eric.miao@marvell.com> * initial version */ #ifndef __ASM_ARCH_MFP_H #define __ASM_ARCH_MFP_H #include <plat/mfp.h> #endif /* __ASM_ARCH_MFP_H */ PK ! �%� � � include/mach/mtd-xip.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * MTD primitives for XIP support. Architecture specific functions * * Do not include this file directly. It's included from linux/mtd/xip.h * * Author: Nicolas Pitre * Created: Nov 2, 2004 * Copyright: (C) 2004 MontaVista Software, Inc. */ #ifndef __ARCH_PXA_MTD_XIP_H__ #define __ARCH_PXA_MTD_XIP_H__ #include <mach/regs-ost.h> /* restored July 2017, this did not build since 2011! */ #define ICIP io_p2v(0x40d00000) #define ICMR io_p2v(0x40d00004) #define xip_irqpending() (readl(ICIP) & readl(ICMR)) /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ #define xip_currtime() readl(OSCR) #define xip_elapsed_since(x) (signed)((readl(OSCR) - (x)) / 4) /* * xip_cpu_idle() is used when waiting for a delay equal or larger than * the system timer tick period. This should put the CPU into idle mode * to save power and to be woken up only when some interrupts are pending. * As above, this should not rely upon standard kernel code. */ #define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1)) #endif /* __ARCH_PXA_MTD_XIP_H__ */ PK ! ī;�# # include/mach/hardware.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/hardware.h * * Author: Nicolas Pitre * Created: Jun 15, 2001 * Copyright: MontaVista Software Inc. */ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H #include <mach/addr-map.h> /* * Workarounds for at least 2 errata so far require this. * The mapping is set in mach-pxa/generic.c. */ #define UNCACHED_PHYS_0 0xfe000000 #define UNCACHED_PHYS_0_SIZE 0x00100000 /* * Intel PXA2xx internal register mapping: * * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff * * Note that not all PXA2xx chips implement all those addresses, and the * kernel only maps the minimum needed range of this mapping. */ #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) #ifndef __ASSEMBLY__ # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) /* With indexed regs we don't want to feed the index through io_p2v() especially if it is a variable, otherwise horrible code will result. */ # define __REG2(x,y) \ (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) # define __PREG(x) (io_v2p((u32)&(x))) #else # define __REG(x) io_p2v(x) # define __PREG(x) io_v2p(x) #endif #ifndef __ASSEMBLY__ #include <asm/cputype.h> /* * CPU Stepping CPU_ID JTAG_ID * * PXA210 B0 0x69052922 0x2926C013 * PXA210 B1 0x69052923 0x3926C013 * PXA210 B2 0x69052924 0x4926C013 * PXA210 C0 0x69052D25 0x5926C013 * * PXA250 A0 0x69052100 0x09264013 * PXA250 A1 0x69052101 0x19264013 * PXA250 B0 0x69052902 0x29264013 * PXA250 B1 0x69052903 0x39264013 * PXA250 B2 0x69052904 0x49264013 * PXA250 C0 0x69052D05 0x59264013 * * PXA255 A0 0x69052D06 0x69264013 * * PXA26x A0 0x69052903 0x39264013 * PXA26x B0 0x69052D05 0x59264013 * * PXA27x A0 0x69054110 0x09265013 * PXA27x A1 0x69054111 0x19265013 * PXA27x B0 0x69054112 0x29265013 * PXA27x B1 0x69054113 0x39265013 * PXA27x C0 0x69054114 0x49265013 * PXA27x C5 0x69054117 0x79265013 * * PXA30x A0 0x69056880 0x0E648013 * PXA30x A1 0x69056881 0x1E648013 * PXA31x A0 0x69056890 0x0E649013 * PXA31x A1 0x69056891 0x1E649013 * PXA31x A2 0x69056892 0x2E649013 * PXA32x B1 0x69056825 0x5E642013 * PXA32x B2 0x69056826 0x6E642013 * * PXA930 B0 0x69056835 0x5E643013 * PXA930 B1 0x69056837 0x7E643013 * PXA930 B2 0x69056838 0x8E643013 * * PXA935 A0 0x56056931 0x1E653013 * PXA935 B0 0x56056936 0x6E653013 * PXA935 B1 0x56056938 0x8E653013 */ #ifdef CONFIG_PXA25x #define __cpu_is_pxa210(id) \ ({ \ unsigned int _id = (id) & 0xf3f0; \ _id == 0x2120; \ }) #define __cpu_is_pxa250(id) \ ({ \ unsigned int _id = (id) & 0xf3ff; \ _id <= 0x2105; \ }) #define __cpu_is_pxa255(id) \ ({ \ unsigned int _id = (id) & 0xffff; \ _id == 0x2d06; \ }) #define __cpu_is_pxa25x(id) \ ({ \ unsigned int _id = (id) & 0xf300; \ _id == 0x2100; \ }) #else #define __cpu_is_pxa210(id) (0) #define __cpu_is_pxa250(id) (0) #define __cpu_is_pxa255(id) (0) #define __cpu_is_pxa25x(id) (0) #endif #ifdef CONFIG_PXA27x #define __cpu_is_pxa27x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x411; \ }) #else #define __cpu_is_pxa27x(id) (0) #endif #ifdef CONFIG_CPU_PXA300 #define __cpu_is_pxa300(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x688; \ }) #else #define __cpu_is_pxa300(id) (0) #endif #ifdef CONFIG_CPU_PXA310 #define __cpu_is_pxa310(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x689; \ }) #else #define __cpu_is_pxa310(id) (0) #endif #ifdef CONFIG_CPU_PXA320 #define __cpu_is_pxa320(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x603 || _id == 0x682; \ }) #else #define __cpu_is_pxa320(id) (0) #endif #ifdef CONFIG_CPU_PXA930 #define __cpu_is_pxa930(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x683; \ }) #else #define __cpu_is_pxa930(id) (0) #endif #ifdef CONFIG_CPU_PXA935 #define __cpu_is_pxa935(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x693; \ }) #else #define __cpu_is_pxa935(id) (0) #endif #define cpu_is_pxa210() \ ({ \ __cpu_is_pxa210(read_cpuid_id()); \ }) #define cpu_is_pxa250() \ ({ \ __cpu_is_pxa250(read_cpuid_id()); \ }) #define cpu_is_pxa255() \ ({ \ __cpu_is_pxa255(read_cpuid_id()); \ }) #define cpu_is_pxa25x() \ ({ \ __cpu_is_pxa25x(read_cpuid_id()); \ }) #define cpu_is_pxa27x() \ ({ \ __cpu_is_pxa27x(read_cpuid_id()); \ }) #define cpu_is_pxa300() \ ({ \ __cpu_is_pxa300(read_cpuid_id()); \ }) #define cpu_is_pxa310() \ ({ \ __cpu_is_pxa310(read_cpuid_id()); \ }) #define cpu_is_pxa320() \ ({ \ __cpu_is_pxa320(read_cpuid_id()); \ }) #define cpu_is_pxa930() \ ({ \ __cpu_is_pxa930(read_cpuid_id()); \ }) #define cpu_is_pxa935() \ ({ \ __cpu_is_pxa935(read_cpuid_id()); \ }) /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x */ #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) #define __cpu_is_pxa2xx(id) \ ({ \ unsigned int _id = (id) >> 13 & 0x7; \ _id <= 0x2; \ }) #else #define __cpu_is_pxa2xx(id) (0) #endif #ifdef CONFIG_PXA3xx #define __cpu_is_pxa3xx(id) \ ({ \ __cpu_is_pxa300(id) \ || __cpu_is_pxa310(id) \ || __cpu_is_pxa320(id) \ || __cpu_is_pxa93x(id); \ }) #else #define __cpu_is_pxa3xx(id) (0) #endif #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) #define __cpu_is_pxa93x(id) \ ({ \ __cpu_is_pxa930(id) \ || __cpu_is_pxa935(id); \ }) #else #define __cpu_is_pxa93x(id) (0) #endif #define cpu_is_pxa2xx() \ ({ \ __cpu_is_pxa2xx(read_cpuid_id()); \ }) #define cpu_is_pxa3xx() \ ({ \ __cpu_is_pxa3xx(read_cpuid_id()); \ }) #define cpu_is_pxa93x() \ ({ \ __cpu_is_pxa93x(read_cpuid_id()); \ }) /* * return current memory and LCD clock frequency in units of 10kHz */ extern unsigned int get_memclk_frequency_10khz(void); #endif #endif /* _ASM_ARCH_HARDWARE_H */ PK ! ��� � include/mach/reset.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_RESET_H #define __ASM_ARCH_RESET_H #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ #define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */ #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ #define RESET_STATUS_ALL (0xf) extern unsigned int reset_status; extern void clear_reset_status(unsigned int mask); /** * init_gpio_reset() - register GPIO as reset generator * @gpio: gpio nr * @output: set gpio as output instead of input during normal work * @level: output level */ extern int init_gpio_reset(int gpio, int output, int level); #endif /* __ASM_ARCH_RESET_H */ PK ! �� �� � include/mach/regs-ac97.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_REGS_AC97_H #define __ASM_ARCH_REGS_AC97_H #include <mach/hardware.h> /* * AC97 Controller registers */ #define POCR __REG(0x40500000) /* PCM Out Control Register */ #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ #define PICR __REG(0x40500004) /* PCM In Control Register */ #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ #define MCCR __REG(0x40500008) /* Mic In Control Register */ #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ #define GCR __REG(0x4050000C) /* Global Control Register */ #ifdef CONFIG_PXA3xx #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ #endif #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ #define POSR __REG(0x40500010) /* PCM Out Status Register */ #define POSR_FIFOE (1 << 4) /* FIFO error */ #define POSR_FSR (1 << 2) /* FIFO Service Request */ #define PISR __REG(0x40500014) /* PCM In Status Register */ #define PISR_FIFOE (1 << 4) /* FIFO error */ #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ #define PISR_FSR (1 << 2) /* FIFO Service Request */ #define MCSR __REG(0x40500018) /* Mic In Status Register */ #define MCSR_FIFOE (1 << 4) /* FIFO error */ #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ #define MCSR_FSR (1 << 2) /* FIFO Service Request */ #define GSR __REG(0x4050001C) /* Global Status Register */ #define GSR_CDONE (1 << 19) /* Command Done */ #define GSR_SDONE (1 << 18) /* Status Done */ #define GSR_RDCS (1 << 15) /* Read Completion Status */ #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ #define GSR_PCR (1 << 8) /* Primary Codec Ready */ #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ #define CAR __REG(0x40500020) /* CODEC Access Register */ #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ #define MOCR __REG(0x40500100) /* Modem Out Control Register */ #define MOCR_FEIE (1 << 3) /* FIFO Error */ #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ #define MICR __REG(0x40500108) /* Modem In Control Register */ #define MICR_FEIE (1 << 3) /* FIFO Error */ #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ #define MOSR __REG(0x40500110) /* Modem Out Status Register */ #define MOSR_FIFOE (1 << 4) /* FIFO error */ #define MOSR_FSR (1 << 2) /* FIFO Service Request */ #define MISR __REG(0x40500118) /* Modem In Status Register */ #define MISR_FIFOE (1 << 4) /* FIFO error */ #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ #define MISR_FSR (1 << 2) /* FIFO Service Request */ #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ #endif /* __ASM_ARCH_REGS_AC97_H */ PK ! ��:��" �" include/mach/pxa2xx-regs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h * * Taken from pxa-regs.h by Russell King * * Author: Nicolas Pitre * Copyright: MontaVista Software Inc. */ #ifndef __PXA2XX_REGS_H #define __PXA2XX_REGS_H #include <mach/hardware.h> /* * Power Manager */ #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ #define PCMD(x) __REG2(0x40F00080, (x)<<2) #define PCMD0 __REG(0x40F00080 + 0 * 4) #define PCMD1 __REG(0x40F00080 + 1 * 4) #define PCMD2 __REG(0x40F00080 + 2 * 4) #define PCMD3 __REG(0x40F00080 + 3 * 4) #define PCMD4 __REG(0x40F00080 + 4 * 4) #define PCMD5 __REG(0x40F00080 + 5 * 4) #define PCMD6 __REG(0x40F00080 + 6 * 4) #define PCMD7 __REG(0x40F00080 + 7 * 4) #define PCMD8 __REG(0x40F00080 + 8 * 4) #define PCMD9 __REG(0x40F00080 + 9 * 4) #define PCMD10 __REG(0x40F00080 + 10 * 4) #define PCMD11 __REG(0x40F00080 + 11 * 4) #define PCMD12 __REG(0x40F00080 + 12 * 4) #define PCMD13 __REG(0x40F00080 + 13 * 4) #define PCMD14 __REG(0x40F00080 + 14 * 4) #define PCMD15 __REG(0x40F00080 + 15 * 4) #define PCMD16 __REG(0x40F00080 + 16 * 4) #define PCMD17 __REG(0x40F00080 + 17 * 4) #define PCMD18 __REG(0x40F00080 + 18 * 4) #define PCMD19 __REG(0x40F00080 + 19 * 4) #define PCMD20 __REG(0x40F00080 + 20 * 4) #define PCMD21 __REG(0x40F00080 + 21 * 4) #define PCMD22 __REG(0x40F00080 + 22 * 4) #define PCMD23 __REG(0x40F00080 + 23 * 4) #define PCMD24 __REG(0x40F00080 + 24 * 4) #define PCMD25 __REG(0x40F00080 + 25 * 4) #define PCMD26 __REG(0x40F00080 + 26 * 4) #define PCMD27 __REG(0x40F00080 + 27 * 4) #define PCMD28 __REG(0x40F00080 + 28 * 4) #define PCMD29 __REG(0x40F00080 + 29 * 4) #define PCMD30 __REG(0x40F00080 + 30 * 4) #define PCMD31 __REG(0x40F00080 + 31 * 4) #define PCMD_MBC (1<<12) #define PCMD_DCE (1<<11) #define PCMD_LC (1<<10) /* FIXME: PCMD_SQC need be checked. */ #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, bit 9 should be 0 all day. */ #define PVCR_VCSA (0x1<<14) #define PVCR_CommandDelay (0xf80) #define PCFR_PI2C_EN (0x1 << 6) #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ #define PSSR_RDH (1 << 5) /* Read Disable Hold */ #define PSSR_PH (1 << 4) /* Peripheral Control Hold */ #define PSSR_STS (1 << 3) /* Standby Mode Status */ #define PSSR_VFS (1 << 2) /* VDD Fault Status */ #define PSSR_BFS (1 << 1) /* Battery Fault Status */ #define PSSR_SSS (1 << 0) /* Software Sleep Status */ #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ #define PCFR_RO (1 << 15) /* RDH Override */ #define PCFR_PO (1 << 14) /* PH Override */ #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ #define PCFR_DS (1 << 3) /* Deep Sleep Mode */ #define PCFR_FS (1 << 2) /* Float Static Chip Selects */ #define PCFR_FP (1 << 1) /* Float PCMCIA controls */ #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ #define RCSR_GPR (1 << 3) /* GPIO Reset */ #define RCSR_SMR (1 << 2) /* Sleep Mode */ #define RCSR_WDR (1 << 1) /* Watchdog Reset */ #define RCSR_HWR (1 << 0) /* Hardware Reset */ #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ /* * PXA2xx specific Core clock definitions */ #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */ #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ #define CKEN io_p2v(0x41300004) /* Clock Enable Register */ #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ #define CCCR_CPDIS_BIT (31) #define CCCR_PPDIS_BIT (30) #define CCCR_LCD_26_BIT (27) #define CCCR_A_BIT (25) #define CCSR_N2_MASK CCCR_N_MASK #define CCSR_M_MASK CCCR_M_MASK #define CCSR_L_MASK CCCR_L_MASK #define CCSR_N2_SHIFT 7 #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ #define CKEN_MEMC (22) /* Memory Controller Clock Enable */ #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ #define CKEN_IM (20) /* Internal Memory Clock Enable */ #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ #define CKEN_USIM (18) /* USIM Unit Clock Enable */ #define CKEN_MSL (17) /* MSL Unit Clock Enable */ #define CKEN_LCD (16) /* LCD Unit Clock Enable */ #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ #define CKEN_I2C (14) /* I2C Unit Clock Enable */ #define CKEN_FICP (13) /* FICP Unit Clock Enable */ #define CKEN_MMC (12) /* MMC Unit Clock Enable */ #define CKEN_USB (11) /* USB Unit Clock Enable */ #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ #define CKEN_I2S (8) /* I2S Unit Clock Enable */ #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ #define CKEN_STUART (5) /* STUART Unit Clock Enable */ #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ #define CKEN_SSP (3) /* SSP Unit Clock Enable */ #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ #define CKEN_PWM1 (1) /* PWM1 Clock Enable */ #define CKEN_PWM0 (0) /* PWM0 Clock Enable */ #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ /* PWRMODE register M field values */ #define PWRMODE_IDLE 0x1 #define PWRMODE_STANDBY 0x2 #define PWRMODE_SLEEP 0x3 #define PWRMODE_DEEPSLEEP 0x7 #endif PK ! ��AL� � include/mach/smemc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Static memory controller register definitions for PXA CPUs * * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> */ #ifndef __SMEMC_REGS_H #define __SMEMC_REGS_H #define PXA2XX_SMEMC_BASE 0x48000000 #define PXA3XX_SMEMC_BASE 0x4a000000 #define SMEMC_VIRT IOMEM(0xf6000000) #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ #define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */ #define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ #define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */ #define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */ #define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */ #define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */ #define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */ #define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */ #define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */ #define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */ #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */ #define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ #define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */ #define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */ #define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */ #define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */ #define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */ #define CSMSADRCFG (SMEMC_VIRT + 0xA0) /* Chip Select Configuration Register */ /* * More handy macros for PCMCIA * * Arg is socket number */ #define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */ #define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */ #define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */ /* MECR register defines */ #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ #endif PK ! � ��7 7 include/mach/regs-uart.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_REGS_UART_H #define __ASM_ARCH_REGS_UART_H /* * UARTs */ /* Full Function UART (FFUART) */ #define FFUART FFRBR #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ /* Bluetooth UART (BTUART) */ #define BTUART BTRBR #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ /* Standard UART (STUART) */ #define STUART STRBR #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ #define STMSR __REG(0x40700018) /* Reserved */ #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ /* Hardware UART (HWUART) */ #define HWUART HWRBR #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ #define IER_DMAE (1 << 7) /* DMA Requests Enable */ #define IER_UUE (1 << 6) /* UART Unit Enable */ #define IER_NRZE (1 << 5) /* NRZ coding Enable */ #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ #define IIR_TOD (1 << 3) /* Time Out Detected */ #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ #define FCR_ITL_1 (0) #define FCR_ITL_8 (FCR_ITL1) #define FCR_ITL_16 (FCR_ITL2) #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ #define LCR_SB (1 << 6) /* Set Break */ #define LCR_STKYP (1 << 5) /* Sticky Parity */ #define LCR_EPS (1 << 4) /* Even Parity Select */ #define LCR_PEN (1 << 3) /* Parity Enable */ #define LCR_STB (1 << 2) /* Stop Bit */ #define LCR_WLS1 (1 << 1) /* Word Length Select */ #define LCR_WLS0 (1 << 0) /* Word Length Select */ #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ #define LSR_TEMT (1 << 6) /* Transmitter Empty */ #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ #define LSR_BI (1 << 4) /* Break Interrupt */ #define LSR_FE (1 << 3) /* Framing Error */ #define LSR_PE (1 << 2) /* Parity Error */ #define LSR_OE (1 << 1) /* Overrun Error */ #define LSR_DR (1 << 0) /* Data Ready */ #define MCR_LOOP (1 << 4) #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ #define MCR_RTS (1 << 1) /* Request to Send */ #define MCR_DTR (1 << 0) /* Data Terminal Ready */ #define MSR_DCD (1 << 7) /* Data Carrier Detect */ #define MSR_RI (1 << 6) /* Ring Indicator */ #define MSR_DSR (1 << 5) /* Data Set Ready */ #define MSR_CTS (1 << 4) /* Clear To Send */ #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ /* * IrSR (Infrared Selection Register) */ #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ #endif /* __ASM_ARCH_REGS_UART_H */ PK ! 4��� � include/mach/eseries-gpio.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * eseries-gpio.h * * Copyright (C) Ian Molton <spyro@f2s.com> */ /* e-series power button */ #define GPIO_ESERIES_POWERBTN 0 /* UDC GPIO definitions */ #define GPIO_E7XX_USB_DISC 13 #define GPIO_E7XX_USB_PULLUP 3 #define GPIO_E800_USB_DISC 4 #define GPIO_E800_USB_PULLUP 84 /* e740 PCMCIA GPIO definitions */ /* Note: PWR1 seems to be inverted */ #define GPIO_E740_PCMCIA_CD0 8 #define GPIO_E740_PCMCIA_CD1 44 #define GPIO_E740_PCMCIA_RDY0 11 #define GPIO_E740_PCMCIA_RDY1 6 #define GPIO_E740_PCMCIA_RST0 27 #define GPIO_E740_PCMCIA_RST1 24 #define GPIO_E740_PCMCIA_PWR0 20 #define GPIO_E740_PCMCIA_PWR1 23 /* e750 PCMCIA GPIO definitions */ #define GPIO_E750_PCMCIA_CD0 8 #define GPIO_E750_PCMCIA_RDY0 12 #define GPIO_E750_PCMCIA_RST0 27 #define GPIO_E750_PCMCIA_PWR0 20 /* e800 PCMCIA GPIO definitions */ #define GPIO_E800_PCMCIA_RST0 69 #define GPIO_E800_PCMCIA_RST1 72 #define GPIO_E800_PCMCIA_PWR0 20 #define GPIO_E800_PCMCIA_PWR1 73 /* e7xx IrDA power control */ #define GPIO_E7XX_IR_OFF 38 /* e740 audio control GPIOs */ #define GPIO_E740_WM9705_nAVDD2 16 #define GPIO_E740_MIC_ON 40 #define GPIO_E740_AMP_ON 41 /* e750 audio control GPIOs */ #define GPIO_E750_HP_AMP_OFF 4 #define GPIO_E750_SPK_AMP_OFF 7 #define GPIO_E750_HP_DETECT 37 /* e800 audio control GPIOs */ #define GPIO_E800_HP_DETECT 81 #define GPIO_E800_HP_AMP_OFF 82 #define GPIO_E800_SPK_AMP_ON 83 /* ASIC related GPIOs */ #define GPIO_ESERIES_TMIO_IRQ 5 #define GPIO_ESERIES_TMIO_PCLR 19 #define GPIO_ESERIES_TMIO_SUSPEND 45 #define GPIO_E800_ANGELX_IRQ 8 PK ! �D/� � include/mach/audio.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ARCH_AUDIO_H__ #define __ASM_ARCH_AUDIO_H__ #include <sound/core.h> #include <sound/pcm.h> #include <sound/ac97_codec.h> /* * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95) * a -1 value means no gpio will be used for reset * @codec_pdata: AC97 codec platform_data * reset_gpio should only be specified for pxa27x CPUs where a silicon * bug prevents correct operation of the reset line. If not specified, * the default behaviour on these CPUs is to consider gpio 113 as the * AC97 reset line, which is the default on most boards. */ typedef struct { int (*startup)(struct snd_pcm_substream *, void *); void (*shutdown)(struct snd_pcm_substream *, void *); void (*suspend)(void *); void (*resume)(void *); void *priv; int reset_gpio; void *codec_pdata[AC97_BUS_MAX_DEVICES]; } pxa2xx_audio_ops_t; extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); #endif PK ! �ۓ~ ~ include/mach/dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/dma.h * * Author: Nicolas Pitre * Created: Jun 15, 2001 * Copyright: MontaVista Software, Inc. */ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H #include <mach/hardware.h> /* DMA Controller Registers Definitions */ #define DMAC_REGS_VIRT io_p2v(0x40000000) #endif /* _ASM_ARCH_DMA_H */ PK ! ^�� M M include/mach/palmtc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/include/asm-arm/arch-pxa/palmtc-gpio.h * * GPIOs and interrupts for Palm Tungsten|C Handheld Computer * * Authors: Alex Osborne <bobofdoom@gmail.com> * Marek Vasut <marek.vasut@gmail.com> * Holger Bocklet <bitz.email@gmx.net> */ #ifndef _INCLUDE_PALMTC_H_ #define _INCLUDE_PALMTC_H_ #include "irqs.h" /* PXA_GPIO_TO_IRQ */ /** HERE ARE GPIOs **/ /* GPIOs */ #define GPIO_NR_PALMTC_EARPHONE_DETECT 2 #define GPIO_NR_PALMTC_CRADLE_DETECT 5 #define GPIO_NR_PALMTC_HOTSYNC_BUTTON 7 /* SD/MMC */ #define GPIO_NR_PALMTC_SD_DETECT_N 12 #define GPIO_NR_PALMTC_SD_POWER 32 #define GPIO_NR_PALMTC_SD_READONLY 54 /* WLAN */ #define GPIO_NR_PALMTC_PCMCIA_READY 13 #define GPIO_NR_PALMTC_PCMCIA_PWRREADY 14 #define GPIO_NR_PALMTC_PCMCIA_POWER1 15 #define GPIO_NR_PALMTC_PCMCIA_POWER2 33 #define GPIO_NR_PALMTC_PCMCIA_POWER3 55 #define GPIO_NR_PALMTC_PCMCIA_RESET 78 /* UDC */ #define GPIO_NR_PALMTC_USB_DETECT_N 4 #define GPIO_NR_PALMTC_USB_POWER 36 /* LCD/BACKLIGHT */ #define GPIO_NR_PALMTC_BL_POWER 16 #define GPIO_NR_PALMTC_LCD_POWER 44 #define GPIO_NR_PALMTC_LCD_BLANK 38 /* UART */ #define GPIO_NR_PALMTC_RS232_POWER 37 /* IRDA */ #define GPIO_NR_PALMTC_IR_DISABLE 45 /* IRQs */ #define IRQ_GPIO_PALMTC_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N) #define IRQ_GPIO_PALMTC_WLAN_READY PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY) /* UCB1400 GPIOs */ #define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00) #define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01) #define GPIO_NR_PALMTC_SPEAKER_ENABLE (0x80 | 0x03) #define GPIO_NR_PALMTC_VIBRA_POWER (0x80 | 0x05) #define GPIO_NR_PALMTC_LED_POWER (0x80 | 0x07) /** HERE ARE INIT VALUES **/ #define PALMTC_UCB1400_GPIO_OFFSET 0x80 /* BATTERY */ #define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ #define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ #define PALMTC_BAT_MAX_CURRENT 0 /* unknown */ #define PALMTC_BAT_MIN_CURRENT 0 /* unknown */ #define PALMTC_BAT_MAX_CHARGE 1 /* unknown */ #define PALMTC_BAT_MIN_CHARGE 1 /* unknown */ #define PALMTC_MAX_LIFE_MINS 240 /* on-life in minutes */ #define PALMTC_BAT_MEASURE_DELAY (HZ * 1) /* BACKLIGHT */ #define PALMTC_MAX_INTENSITY 0xFE #define PALMTC_DEFAULT_INTENSITY 0x7E #define PALMTC_LIMIT_MASK 0x7F #define PALMTC_PRESCALER 0x3F #define PALMTC_PERIOD_NS 3500 #endif PK ! � �S� � include/mach/poodle.hnu �[��� /* * arch/arm/mach-pxa/include/mach/poodle.h * * May be copied or modified under the terms of the GNU General Public * License. See linux/COPYING for more information. * * Based on: * arch/arm/mach-sa1100/include/mach/collie.h * * ChangeLog: * 04-06-2001 Lineo Japan, Inc. * 04-16-2001 SHARP Corporation * Update to 2.6 John Lenz */ #ifndef __ASM_ARCH_POODLE_H #define __ASM_ARCH_POODLE_H 1 #include "irqs.h" /* PXA_GPIO_TO_IRQ */ /* * GPIOs */ /* PXA GPIOs */ #define POODLE_GPIO_ON_KEY (0) #define POODLE_GPIO_AC_IN (1) #define POODLE_GPIO_CO 16 #define POODLE_GPIO_TP_INT (5) #define POODLE_GPIO_TP_CS (24) #define POODLE_GPIO_WAKEUP (11) /* change battery */ #define POODLE_GPIO_GA_INT (10) #define POODLE_GPIO_IR_ON (22) #define POODLE_GPIO_HP_IN (4) #define POODLE_GPIO_CF_IRQ (17) #define POODLE_GPIO_CF_CD (14) #define POODLE_GPIO_CF_STSCHG (14) #define POODLE_GPIO_SD_PWR (33) #define POODLE_GPIO_SD_PWR1 (3) #define POODLE_GPIO_nSD_CLK (6) #define POODLE_GPIO_nSD_WP (7) #define POODLE_GPIO_nSD_INT (8) #define POODLE_GPIO_nSD_DETECT (9) #define POODLE_GPIO_MAIN_BAT_LOW (13) #define POODLE_GPIO_BAT_COVER (13) #define POODLE_GPIO_USB_PULLUP (20) #define POODLE_GPIO_ADC_TEMP_ON (21) #define POODLE_GPIO_BYPASS_ON (36) #define POODLE_GPIO_CHRG_ON (38) #define POODLE_GPIO_CHRG_FULL (16) #define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ /* PXA GPIOs */ #define POODLE_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(0) #define POODLE_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) #define POODLE_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(4) #define POODLE_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(16) #define POODLE_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) #define POODLE_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(11) #define POODLE_IRQ_GPIO_GA_INT PXA_GPIO_TO_IRQ(10) #define POODLE_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) #define POODLE_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) #define POODLE_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(8) #define POODLE_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) #define POODLE_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(13) /* SCOOP GPIOs */ #define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 #define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13 #define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18 #define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20 #define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21 #define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22 #define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) #define POODLE_SCOOP_IO_OUT ( 0 ) #define POODLE_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0) #define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2) #define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7) #define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9) #define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10) #define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11) #define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8) #define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10) #define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11) #define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12) #define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13) #define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */ extern struct platform_device poodle_locomo_device; #endif /* __ASM_ARCH_POODLE_H */ PK ! �U�� � include/mach/mainstone.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/mainstone.h * * Author: Nicolas Pitre * Created: Nov 14, 2002 * Copyright: MontaVista Software Inc. */ #ifndef ASM_ARCH_MAINSTONE_H #define ASM_ARCH_MAINSTONE_H #include <mach/irqs.h> #define MST_ETH_PHYS PXA_CS4_PHYS #define MST_FPGA_PHYS PXA_CS2_PHYS #define MST_FPGA_VIRT (0xf0000000) #define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT) #define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS) #ifndef __ASSEMBLY__ # define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x))) #else # define __MST_REG(x) MST_P2V(x) #endif /* board level registers in the FPGA */ #define MST_LEDDAT1 __MST_REG(0x08000010) #define MST_LEDDAT2 __MST_REG(0x08000014) #define MST_LEDCTRL __MST_REG(0x08000040) #define MST_GPSWR __MST_REG(0x08000060) #define MST_MSCWR1 __MST_REG(0x08000080) #define MST_MSCWR2 __MST_REG(0x08000084) #define MST_MSCWR3 __MST_REG(0x08000088) #define MST_MSCRD __MST_REG(0x08000090) #define MST_INTMSKENA __MST_REG(0x080000c0) #define MST_INTSETCLR __MST_REG(0x080000d0) #define MST_PCMCIA0 __MST_REG(0x080000e0) #define MST_PCMCIA1 __MST_REG(0x080000e4) #define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */ #define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */ #define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */ #define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */ #define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */ #define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */ #define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */ #define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ #define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ #define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */ #define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */ #define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */ #define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */ #define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */ #define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */ #define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */ #define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */ #define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */ #define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */ #define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */ #define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */ #define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */ #define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */ #define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */ #define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */ #define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */ #define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ #define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ #define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */ #define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */ #define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */ #define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */ #define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */ #define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */ #define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */ #define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ #define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ #define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */ #define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */ #define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */ #define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */ #define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */ #define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */ #define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */ #define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */ #define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */ #define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */ #define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */ #define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ #define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ #define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */ #define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */ #define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */ #define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */ #define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */ #define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */ #define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */ #define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */ #define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */ #define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */ #define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */ #define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */ #define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/ #define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */ #define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */ #define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ #define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ #define MST_PCMCIA_INPUTS \ (MST_PCMCIA_nIRQ | MST_PCMCIA_nSPKR_BVD2 | MST_PCMCIA_nSTSCHG_BVD1 | \ MST_PCMCIA_nVS2 | MST_PCMCIA_nVS1 | MST_PCMCIA_nCD) /* board specific IRQs */ #define MAINSTONE_NR_IRQS IRQ_BOARD_START #define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x)) #define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) #define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) #define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) #define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) #define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) #define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) #define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) #define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) #define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) #define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) #define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) #define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) #define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) #endif PK ! �"Թ � include/mach/lubbock.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/lubbock.h * * Author: Nicolas Pitre * Created: Jun 15, 2001 * Copyright: MontaVista Software Inc. */ #include <mach/irqs.h> #define LUBBOCK_ETH_PHYS PXA_CS3_PHYS #define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS #define LUBBOCK_FPGA_VIRT (0xf0000000) #define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT) #define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS) #ifndef __ASSEMBLY__ # define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x))) #else # define __LUB_REG(x) LUB_P2V(x) #endif /* FPGA register virtual addresses */ #define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) #define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) #define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) #define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) #define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090) #define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0) #define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) #define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) /* Board specific IRQs */ #define LUBBOCK_NR_IRQS IRQ_BOARD_START #define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x)) #define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) #define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) #define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ #define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) #define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) #define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) #define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ #define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) #define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32) PK ! L� include/mach/z2.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-pxa/include/mach/z2.h * * Author: Ken McGuire * Created: Feb 6, 2009 */ #ifndef ASM_ARCH_ZIPIT2_H #define ASM_ARCH_ZIPIT2_H /* LEDs */ #define GPIO10_ZIPITZ2_LED_WIFI 10 #define GPIO85_ZIPITZ2_LED_CHARGED 85 #define GPIO83_ZIPITZ2_LED_CHARGING 83 /* SD/MMC */ #define GPIO96_ZIPITZ2_SD_DETECT 96 /* GPIO Buttons */ #define GPIO1_ZIPITZ2_POWER_BUTTON 1 #define GPIO98_ZIPITZ2_LID_BUTTON 98 /* Libertas GSPI8686 WiFi */ #define GPIO14_ZIPITZ2_WIFI_POWER 14 #define GPIO24_ZIPITZ2_WIFI_CS 24 #define GPIO36_ZIPITZ2_WIFI_IRQ 36 /* LCD */ #define GPIO19_ZIPITZ2_LCD_RESET 19 #define GPIO88_ZIPITZ2_LCD_CS 88 /* MISC GPIOs */ #define GPIO0_ZIPITZ2_AC_DETECT 0 #define GPIO37_ZIPITZ2_HEADSET_DETECT 37 #endif PK ! :<; include/mach/regs-ost.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_MACH_REGS_OST_H #define __ASM_MACH_REGS_OST_H #include <mach/hardware.h> /* * OS Timer & Match Registers */ #define OSMR0 io_p2v(0x40A00000) /* */ #define OSMR1 io_p2v(0x40A00004) /* */ #define OSMR2 io_p2v(0x40A00008) /* */ #define OSMR3 io_p2v(0x40A0000C) /* */ #define OSMR4 io_p2v(0x40A00080) /* */ #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */ #define OMCR4 io_p2v(0x40A000C0) /* */ #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */ #define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ #define OSSR_M2 (1 << 2) /* Match status channel 2 */ #define OSSR_M1 (1 << 1) /* Match status channel 1 */ #define OSSR_M0 (1 << 0) /* Match status channel 0 */ #define OWER_WME (1 << 0) /* Watchdog Match Enable */ #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ #endif /* __ASM_MACH_REGS_OST_H */ PK ! �8� include/mach/generic.hnu �[��� #include "../../generic.h" PK ! �ct^% % include/mach/trizeps4.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /************************************************************************ * Include file for TRIZEPS4 SoM and ConXS eval-board * Copyright (c) Jürgen Schindele * 2006 ************************************************************************/ /* * Includes/Defines */ #ifndef _TRIPEPS4_H_ #define _TRIPEPS4_H_ #include "irqs.h" /* PXA_GPIO_TO_IRQ */ /* physical memory regions */ #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ #define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ #define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ #define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ /* Logic on ConXS-board CSFR register*/ #define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic on ConXS-board BOCR register*/ #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic on ConXS-board IRCR register*/ #define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic on ConXS-board UPSR register*/ #define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic on ConXS-board DICR register*/ #define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* virtual memory regions */ #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ #define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ #define TRIZEPS4_CFSR_VIRT 0xF0100000 #define TRIZEPS4_BOCR_VIRT 0xF0200000 #define TRIZEPS4_DICR_VIRT 0xF0300000 #define TRIZEPS4_IRCR_VIRT 0xF0400000 #define TRIZEPS4_UPSR_VIRT 0xF0500000 /* size of flash */ #define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ /* Ethernet Controller Davicom DM9000 */ #define GPIO_DM9000 101 #define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) /* UCB1400 audio / TS-controller */ #define GPIO_UCB1400 1 #define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) /* PCMCIA socket Compact Flash */ #define GPIO_PCD 11 /* PCMCIA Card Detect */ #define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) #define GPIO_PRDY 13 /* READY / nINT */ #define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) /* MMC socket */ #define GPIO_MMC_DET 12 #define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) /* DOC NAND chip */ #define GPIO_DOC_LOCK 94 #define GPIO_DOC_IRQ 93 #define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) /* SPI interface */ #define GPIO_SPI 53 #define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) /* LEDS using tx2 / rx2 */ #define GPIO_SYS_BUSY_LED 46 #define GPIO_HEARTBEAT_LED 47 /* Off-module PIC on ConXS board */ #define GPIO_PIC 0 #define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) #ifdef CONFIG_MACH_TRIZEPS_CONXS /* for CONXS base board define these registers */ #define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) #define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) #define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) #define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) #define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) #define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) #define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) #define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) #ifndef __ASSEMBLY__ static inline unsigned short CFSR_readw(void) { /* [Compact Flash Status Register] is read only */ return *((unsigned short *)CFSR_P2V(0x0C000000)); } static inline void BCR_writew(unsigned short value) { /* [Board Control Regsiter] is write only */ *((unsigned short *)BCR_P2V(0x0E000000)) = value; } static inline void DCR_writew(unsigned short value) { /* [Display Control Register] is write only */ *((unsigned short *)DCR_P2V(0x0E000000)) = value; } static inline void IRCR_writew(unsigned short value) { /* [InfraRed data Control Register] is write only */ *((unsigned short *)IRCR_P2V(0x0E000000)) = value; } #else #define ConXS_CFSR CFSR_P2V(0x0C000000) #define ConXS_BCR BCR_P2V(0x0E000000) #define ConXS_DCR DCR_P2V(0x0F800000) #define ConXS_IRCR IRCR_P2V(0x0F800000) #endif #else /* for whatever baseboard define function registers */ static inline unsigned short CFSR_readw(void) { return 0; } static inline void BCR_writew(unsigned short value) { ; } static inline void DCR_writew(unsigned short value) { ; } static inline void IRCR_writew(unsigned short value) { ; } #endif /* CONFIG_MACH_TRIZEPS_CONXS */ #define ConXS_CFSR_BVD_MASK 0x0003 #define ConXS_CFSR_BVD1 (1 << 0) #define ConXS_CFSR_BVD2 (1 << 1) #define ConXS_CFSR_VS_MASK 0x000C #define ConXS_CFSR_VS1 (1 << 2) #define ConXS_CFSR_VS2 (1 << 3) #define ConXS_CFSR_VS_5V (0x3 << 2) #define ConXS_CFSR_VS_3V3 0x0 #define ConXS_BCR_S0_POW_EN0 (1 << 0) #define ConXS_BCR_S0_POW_EN1 (1 << 1) #define ConXS_BCR_L_DISP (1 << 4) #define ConXS_BCR_CF_BUF_EN (1 << 5) #define ConXS_BCR_CF_RESET (1 << 7) #define ConXS_BCR_S0_VCC_3V3 0x1 #define ConXS_BCR_S0_VCC_5V0 0x2 #define ConXS_BCR_S0_VPP_12V 0x4 #define ConXS_BCR_S0_VPP_3V3 0x8 #define ConXS_IRCR_MODE (1 << 0) #define ConXS_IRCR_SD (1 << 1) #endif /* _TRIPEPS4_H_ */ PK ! ��Ul�6 �6 Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only if ARCH_PXA menu "Intel PXA2xx/PXA3xx Implementations" comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" config MACH_PXA25X_DT bool "Support PXA25x platforms from device tree" select PINCTRL select POWER_SUPPLY select PXA25x select USE_OF help Include support for Marvell PXA25x based platforms using the device tree. Needn't select any other machine while MACH_PXA25x_DT is enabled. config MACH_PXA27X_DT bool "Support PXA27x platforms from device tree" select PINCTRL select POWER_SUPPLY select PXA27x select USE_OF help Include support for Marvell PXA27x based platforms using the device tree. Needn't select any other machine while MACH_PXA27X_DT is enabled. config MACH_PXA3XX_DT bool "Support PXA3xx platforms from device tree" select CPU_PXA300 select PINCTRL select POWER_SUPPLY select PXA3xx select USE_OF help Include support for Marvell PXA3xx based platforms using the device tree. Needn't select any other machine while MACH_PXA3XX_DT is enabled. config ARCH_LUBBOCK bool "Intel DBPXA250 Development Platform (aka Lubbock)" select GPIO_REG select PXA25x select SA1111 config MACH_MAINSTONE bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)" select GPIO_REG select PXA27x config MACH_ZYLONITE bool select PXA3xx config MACH_ZYLONITE300 bool "PXA3xx Development Platform (aka Zylonite) PXA300/310" select CPU_PXA300 select CPU_PXA310 select MACH_ZYLONITE config MACH_ZYLONITE320 bool "PXA3xx Development Platform (aka Zylonite) PXA320" select CPU_PXA320 select MACH_ZYLONITE config MACH_LITTLETON bool "PXA3xx Form Factor Platform (aka Littleton)" select CPU_PXA300 select CPU_PXA310 select PXA3xx config MACH_TAVOREVB bool "PXA930 Evaluation Board (aka TavorEVB)" select CPU_PXA930 select CPU_PXA935 select PXA3xx select FB select FB_PXA config MACH_SAAR bool "PXA930 Handheld Platform (aka SAAR)" select CPU_PXA930 select CPU_PXA935 select PXA3xx select FB select FB_PXA comment "Third Party Dev Platforms (sorted by vendor name)" config ARCH_PXA_IDP bool "Accelent Xscale IDP" select PXA25x config ARCH_VIPER bool "Arcom/Eurotech VIPER SBC" select ARCOM_PCMCIA select I2C_GPIO if I2C=y select ISA select PXA25x config MACH_ARCOM_ZEUS bool "Arcom/Eurotech ZEUS SBC" select ARCOM_PCMCIA select ISA select PXA27x config MACH_BALLOON3 bool "Balloon 3 board" select IWMMXT select PXA27x config MACH_CSB726 bool "Enable Cogent CSB726 System On a Module" select IWMMXT select PXA27x help Say Y here if you intend to run this kernel on a Cogent CSB726 System On Module. config CSB726_CSB701 bool "Enable support for CSB701 baseboard" depends on MACH_CSB726 config MACH_CM_X300 bool "CompuLab CM-X300 modules" select CPU_PXA300 select CPU_PXA310 select PXA3xx config MACH_CAPC7117 bool "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM" select CPU_PXA320 select PXA3xx config ARCH_GUMSTIX bool "Gumstix XScale 255 boards" select PXA25x help Say Y here if you intend to run this kernel on Basix, Connex, ws-200ax, ws-400ax systems choice prompt "Gumstix Carrier/Expansion Board" depends on ARCH_GUMSTIX config GUMSTIX_AM200EPD bool "Enable AM200EPD board support" config GUMSTIX_AM300EPD bool "Enable AM300EPD board support" endchoice config MACH_INTELMOTE2 bool "Intel Mote 2 Platform" select IWMMXT select PXA27x config MACH_STARGATE2 bool "Intel Stargate 2 Platform" select IWMMXT select PXA27x config MACH_XCEP bool "Iskratel Electronics XCEP" select MTD select MTD_CFI select MTD_CFI_INTELEXT select MTD_PHYSMAP select PXA25x help PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. Tuned for usage in Libera instruments for particle accelerators. config TRIZEPS_PXA bool "PXA based Keith und Koep Trizeps DIMM-Modules" config MACH_TRIZEPS4 bool "Keith und Koep Trizeps4 DIMM-Module" depends on TRIZEPS_PXA select PXA27x select TRIZEPS_PCMCIA config MACH_TRIZEPS4WL bool "Keith und Koep Trizeps4-WL DIMM-Module" depends on TRIZEPS_PXA select MACH_TRIZEPS4 select PXA27x select TRIZEPS_PCMCIA choice prompt "Select base board for Trizeps module" depends on TRIZEPS_PXA config MACH_TRIZEPS_CONXS bool "ConXS Eval Board" config MACH_TRIZEPS_UCONXS bool "uConXS Eval Board" config MACH_TRIZEPS_ANY bool "another Board" endchoice config ARCOM_PCMCIA bool help Generic option for Arcom Viper/Zeus PCMCIA config TRIZEPS_PCMCIA bool help Enable PCMCIA support for Trizeps modules config MACH_LOGICPD_PXA270 bool "LogicPD PXA270 Card Engine Development Platform" select PXA27x config MACH_PCM027 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" select IWMMXT select PXA27x config MACH_PCM990_BASEBOARD bool "PHYTEC PCM-990 development board" depends on MACH_PCM027 choice prompt "display on pcm990" depends on MACH_PCM990_BASEBOARD config PCM990_DISPLAY_SHARP bool "sharp lq084v1dg21 stn display" config PCM990_DISPLAY_NEC bool "nec nl6448bc20_18d tft display" config PCM990_DISPLAY_NONE bool "no display" endchoice config MACH_COLIBRI bool "Toradex Colibri PXA270" select PXA27x config MACH_COLIBRI_PXA270_INCOME bool "Income s.r.o. PXA270 SBC" depends on MACH_COLIBRI select PXA27x config MACH_COLIBRI300 bool "Toradex Colibri PXA300/310" select CPU_PXA300 select CPU_PXA310 select PXA3xx config MACH_COLIBRI320 bool "Toradex Colibri PXA320" select CPU_PXA320 select PXA3xx config MACH_COLIBRI_EVALBOARD bool "Toradex Colibri Evaluation Carrier Board support" depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320 config MACH_VPAC270 bool "Voipac PXA270" select HAVE_PATA_PLATFORM select PXA27x help PXA270 based Single Board Computer. comment "End-user Products (sorted by vendor name)" config MACH_H4700 bool "HP iPAQ hx4700" select IWMMXT select PXA27x config MACH_H5000 bool "HP iPAQ h5000" select PXA25x config MACH_HIMALAYA bool "HTC Himalaya Support" select CPU_PXA26x config MACH_MAGICIAN bool "Enable HTC Magician Support" select IWMMXT select PXA27x config MACH_MIOA701 bool "Mitac Mio A701 Support" select IWMMXT select PXA27x help Say Y here if you intend to run this kernel on a MIO A701. Currently there is only basic support for this PDA. config PXA_EZX bool "Motorola EZX Platform" select IWMMXT select PXA27x config MACH_EZX_A780 bool "Motorola EZX A780" default y depends on PXA_EZX config MACH_EZX_E680 bool "Motorola EZX E680" default y depends on PXA_EZX config MACH_EZX_A1200 bool "Motorola EZX A1200" default y depends on PXA_EZX config MACH_EZX_A910 bool "Motorola EZX A910" default y depends on PXA_EZX config MACH_EZX_E6 bool "Motorola EZX E6" default y depends on PXA_EZX config MACH_EZX_E2 bool "Motorola EZX E2" default y depends on PXA_EZX config MACH_MP900C bool "Nec Mobilepro 900/c" select PXA25x config ARCH_PXA_PALM bool "PXA based Palm PDAs" config MACH_PALM27X bool config MACH_PALMTE2 bool "Palm Tungsten|E2" default y depends on ARCH_PXA_PALM select PXA25x help Say Y here if you intend to run this kernel on a Palm Tungsten|E2 handheld computer. config MACH_PALMTC bool "Palm Tungsten|C" default y depends on ARCH_PXA_PALM select PXA25x help Say Y here if you intend to run this kernel on a Palm Tungsten|C handheld computer. config MACH_PALMT5 bool "Palm Tungsten|T5" default y depends on ARCH_PXA_PALM select IWMMXT select MACH_PALM27X select PXA27x help Say Y here if you intend to run this kernel on a Palm Tungsten|T5 handheld computer. config MACH_PALMTX bool "Palm T|X" default y depends on ARCH_PXA_PALM select IWMMXT select MACH_PALM27X select PXA27x help Say Y here if you intend to run this kernel on a Palm T|X handheld computer. config MACH_PALMZ72 bool "Palm Zire 72" default y depends on ARCH_PXA_PALM select IWMMXT select MACH_PALM27X select PXA27x help Say Y here if you intend to run this kernel on Palm Zire 72 handheld computer. config MACH_PALMLD bool "Palm LifeDrive" default y depends on ARCH_PXA_PALM select IWMMXT select MACH_PALM27X select PXA27x help Say Y here if you intend to run this kernel on a Palm LifeDrive handheld computer. config PALM_TREO bool depends on ARCH_PXA_PALM config MACH_CENTRO bool "Palm Centro 685 (GSM)" default y depends on ARCH_PXA_PALM select IWMMXT select MACH_PALM27X select PALM_TREO select PXA27x help Say Y here if you intend to run this kernel on Palm Centro 685 (GSM) smartphone. config MACH_TREO680 bool "Palm Treo 680" default y depends on ARCH_PXA_PALM select IWMMXT select MACH_PALM27X select PALM_TREO select PXA27x help Say Y here if you intend to run this kernel on Palm Treo 680 smartphone. config PXA_SHARPSL bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" select SHARP_PARAM select SHARP_SCOOP help Say Y here if you intend to run this kernel on a Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita), SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) handheld computer. config PXA_SHARPSL_DETECT_MACH_ID bool "Detect machine ID at run-time in the decompressor" depends on PXA_SHARPSL help Say Y here if you want the zImage decompressor to detect the Zaurus machine ID at run-time. For latest kexec-based boot loader, this is not necessary. config MACH_POODLE bool "Enable Sharp SL-5600 (Poodle) Support" depends on PXA_SHARPSL select PXA25x select SHARP_LOCOMO config MACH_CORGI bool "Enable Sharp SL-C700 (Corgi) Support" depends on PXA_SHARPSL select PXA25x select PXA_SHARP_C7xx config MACH_SHEPHERD bool "Enable Sharp SL-C750 (Shepherd) Support" depends on PXA_SHARPSL select PXA25x select PXA_SHARP_C7xx config MACH_HUSKY bool "Enable Sharp SL-C760 (Husky) Support" depends on PXA_SHARPSL select PXA25x select PXA_SHARP_C7xx config MACH_AKITA bool "Enable Sharp SL-1000 (Akita) Support" depends on PXA_SHARPSL select I2C select I2C_PXA select MACH_SPITZ select PXA27x select PXA_SHARP_Cxx00 config MACH_SPITZ bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" depends on PXA_SHARPSL select PXA27x select PXA_SHARP_Cxx00 config MACH_BORZOI bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support" depends on PXA_SHARPSL select PXA27x select PXA_SHARP_Cxx00 config MACH_TOSA bool "Enable Sharp SL-6000x (Tosa) Support" depends on PXA_SHARPSL select PXA25x config TOSA_BT tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" depends on MACH_TOSA && NET select RFKILL help This is a simple driver that is able to control the state of built in bluetooth chip on tosa. config TOSA_USE_EXT_KEYCODES bool "Tosa keyboard: use extended keycodes" depends on MACH_TOSA help Say Y here to enable the tosa keyboard driver to generate extended (>= 127) keycodes. Be aware, that they can't be correctly interpreted by either console keyboard driver or by Kdrive keybd driver. Say Y only if you know, what you are doing! config MACH_ICONTROL bool "TMT iControl/SafeTCam based on the MXM-8x10 CoM" select CPU_PXA320 select PXA3xx config ARCH_PXA_ESERIES bool "PXA based Toshiba e-series PDAs" select FB_W100 select FB select PXA25x config MACH_E330 bool "Toshiba e330" default y depends on ARCH_PXA_ESERIES help Say Y here if you intend to run this kernel on a Toshiba e330 family PDA. config MACH_E350 bool "Toshiba e350" default y depends on ARCH_PXA_ESERIES help Say Y here if you intend to run this kernel on a Toshiba e350 family PDA. config MACH_E740 bool "Toshiba e740" default y depends on ARCH_PXA_ESERIES help Say Y here if you intend to run this kernel on a Toshiba e740 family PDA. config MACH_E750 bool "Toshiba e750" default y depends on ARCH_PXA_ESERIES help Say Y here if you intend to run this kernel on a Toshiba e750 family PDA. config MACH_E400 bool "Toshiba e400" default y depends on ARCH_PXA_ESERIES help Say Y here if you intend to run this kernel on a Toshiba e400 family PDA. config MACH_E800 bool "Toshiba e800" default y depends on ARCH_PXA_ESERIES help Say Y here if you intend to run this kernel on a Toshiba e800 family PDA. config MACH_ZIPIT2 bool "Zipit Z2 Handheld" select PXA27x endmenu config PXA25x bool select CPU_XSCALE help Select code specific to PXA21x/25x/26x variants config PXA27x bool select CPU_XSCALE help Select code specific to PXA27x variants config CPU_PXA26x bool select PXA25x help Select code specific to PXA26x (codename Dalhart) config PXA3xx bool select CPU_XSC3 help Select code specific to PXA3xx variants config CPU_PXA300 bool select PXA3xx help PXA300 (codename Monahans-L) config CPU_PXA310 bool select CPU_PXA300 select PXA310_ULPI if USB_ULPI help PXA310 (codename Monahans-LV) config CPU_PXA320 bool select PXA3xx help PXA320 (codename Monahans-P) config CPU_PXA930 bool select PXA3xx help PXA930 (codename Tavor-P) config CPU_PXA935 bool select CPU_PXA930 help PXA935 (codename Tavor-P65) config PXA_SHARP_C7xx bool select SHARPSL_PM help Enable support for all Sharp C7xx models config PXA_SHARP_Cxx00 bool select SHARPSL_PM help Enable common support for Sharp Cxx00 models config SHARPSL_PM bool select APM_EMULATION select SHARPSL_PM_MAX1111 config SHARPSL_PM_MAX1111 bool select HWMON select SENSORS_MAX1111 select SPI select SPI_MASTER config PXA310_ULPI bool config PXA_SYSTEMS_CPLDS tristate "Motherboard cplds" default ARCH_LUBBOCK || MACH_MAINSTONE help This driver supports the Lubbock and Mainstone multifunction chip found on the pxa25x development platform system (Lubbock) and pxa27x development platform system (Mainstone). This IO board supports the interrupts handling, ethernet controller, flash chips, etc ... endif PK ! �ak: : Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the linux kernel. # # Common support (must be linked before board specific support) obj-y += devices.o generic.o irq.o reset.o obj-$(CONFIG_PM) += pm.o sleep.o standby.o # Generic drivers that other drivers may depend upon # SoC-specific code obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o # NOTE: keep the order of boards in accordance to their order in Kconfig # Device Tree support obj-$(CONFIG_MACH_PXA25X_DT) += pxa-dt.o obj-$(CONFIG_MACH_PXA27X_DT) += pxa-dt.o obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o # Intel/Marvell Dev Platforms obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o obj-$(CONFIG_MACH_ZYLONITE300) += zylonite.o zylonite_pxa300.o obj-$(CONFIG_MACH_ZYLONITE320) += zylonite.o zylonite_pxa320.o obj-$(CONFIG_MACH_LITTLETON) += littleton.o obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o obj-$(CONFIG_MACH_SAAR) += saar.o # 3rd Party Dev Platforms obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_ARCH_VIPER) += viper.o obj-$(CONFIG_MACH_ARCOM_ZEUS) += zeus.o obj-$(CONFIG_MACH_BALLOON3) += balloon3.o obj-$(CONFIG_MACH_CSB726) += csb726.o obj-$(CONFIG_CSB726_CSB701) += csb701.o obj-$(CONFIG_MACH_CM_X300) += cm-x300.o obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o obj-$(CONFIG_MACH_INTELMOTE2) += stargate2.o obj-$(CONFIG_MACH_STARGATE2) += stargate2.o obj-$(CONFIG_MACH_XCEP) += xcep.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o obj-$(CONFIG_MACH_PCM027) += pcm027.o obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o obj-$(CONFIG_MACH_COLIBRI_EVALBOARD) += colibri-evalboard.o obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o obj-$(CONFIG_MACH_VPAC270) += vpac270.o # End-user Products obj-$(CONFIG_MACH_H4700) += hx4700.o obj-$(CONFIG_MACH_H5000) += h5000.o obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o obj-$(CONFIG_MACH_MAGICIAN) += magician.o obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o obj-$(CONFIG_PXA_EZX) += ezx.o obj-$(CONFIG_MACH_MP900C) += mp900.o obj-$(CONFIG_MACH_PALMTE2) += palmte2.o obj-$(CONFIG_MACH_PALMTC) += palmtc.o obj-$(CONFIG_MACH_PALM27X) += palm27x.o obj-$(CONFIG_MACH_PALMT5) += palmt5.o obj-$(CONFIG_MACH_PALMTX) += palmtx.o obj-$(CONFIG_MACH_PALMZ72) += palmz72.o obj-$(CONFIG_MACH_PALMLD) += palmld.o obj-$(CONFIG_PALM_TREO) += palmtreo.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_MACH_POODLE) += poodle.o obj-$(CONFIG_MACH_TOSA) += tosa.o obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o obj-$(CONFIG_MACH_ZIPIT2) += z2.o obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o obj-$(CONFIG_TOSA_BT) += tosa-bt.o PK ! �D�E E Makefile.bootnu �[��� # SPDX-License-Identifier: GPL-2.0-only zreladdr-y += 0xa0008000 PK ! �3h� � include/mach/addr-map.hnu �[��� PK ! c}� k k � include/mach/palmld.hnu �[��� PK ! �L�� � � include/mach/balloon3.hnu �[��� PK ! 8��M M �* include/mach/vpac270.hnu �[��� PK ! ���� � l. include/mach/palmtx.hnu �[��� PK ! _��� W; include/mach/tosa.hnu �[��� PK ! �v�L L �W include/mach/corgi.hnu �[��� PK ! ��J� � :j include/mach/uncompress.hnu �[��� PK ! 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