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PK ! ���� � include/mach/lcd_dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * arch/arm/mach-omap1/include/mach/lcd_dma.h * * Extracted from arch/arm/plat-omap/include/plat/dma.h * Copyright (C) 2003 Nokia Corporation * Author: Juha Yrjölä <juha.yrjola@nokia.com> */ #ifndef __MACH_OMAP1_LCD_DMA_H__ #define __MACH_OMAP1_LCD_DMA_H__ /* Hardware registers for LCD DMA */ #define OMAP1510_DMA_LCD_BASE (0xfffedb00) #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) #define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) #define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) #define OMAP1610_DMA_LCD_BASE (0xfffee300) #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) #define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) #define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) #define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) #define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) #define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) #define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) #define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) #define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) #define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) #define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) #define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) /* LCD DMA block numbers */ enum { OMAP_LCD_DMA_B1_TOP, OMAP_LCD_DMA_B1_BOTTOM, OMAP_LCD_DMA_B2_TOP, OMAP_LCD_DMA_B2_BOTTOM }; /* LCD DMA functions */ extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), void *data); extern void omap_free_lcd_dma(void); extern void omap_setup_lcd_dma(void); extern void omap_enable_lcd_dma(void); extern void omap_stop_lcd_dma(void); extern void omap_set_lcd_dma_ext_controller(int external); extern void omap_set_lcd_dma_single_transfer(int single); extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, int data_type); extern void omap_set_lcd_dma_b1_rotation(int rotate); extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); extern void omap_set_lcd_dma_b1_mirror(int mirror); extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); extern int omap_lcd_dma_running(void); #endif /* __MACH_OMAP1_LCD_DMA_H__ */ PK ! �}� � include/mach/uncompress.hnu �[��� /* * arch/arm/plat-omap/include/mach/uncompress.h * * Serial port stubs for kernel decompress status messages * * Initially based on: * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h * Copyright (C) 2000 RidgeRun, Inc. * Author: Greg Lonnon <glonnon@ridgerun.com> * * Rewritten by: * Author: <source@mvista.com> * 2004 (c) MontaVista Software, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include <linux/types.h> #include <linux/serial_reg.h> #include <asm/memory.h> #include <asm/mach-types.h> #include "serial.h" #define MDR1_MODE_MASK 0x07 volatile u8 *uart_base; int uart_shift; /* * Store the DEBUG_LL uart number into memory. * See also debug-macro.S, and serial.c for related code. */ static void set_omap_uart_info(unsigned char port) { /* * Get address of some.bss variable and round it down * a la CONFIG_AUTO_ZRELADDR. */ u32 ram_start = (u32)&uart_shift & 0xf8000000; u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS); *uart_info = port; } static inline void putc(int c) { if (!uart_base) return; /* Check for UART 16x mode */ if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) return; while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) barrier(); uart_base[UART_TX << uart_shift] = c; } static inline void flush(void) { } /* * Macros to configure UART1 and debug UART */ #define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \ if (machine_is_##mach()) { \ uart_base = (volatile u8 *)(dbg_uart); \ uart_shift = (dbg_shft); \ port = (dbg_id); \ set_omap_uart_info(port); \ break; \ } #define DEBUG_LL_OMAP7XX(p, mach) \ _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \ OMAP1UART##p) #define DEBUG_LL_OMAP1(p, mach) \ _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \ OMAP1UART##p) static inline void arch_decomp_setup(void) { int port = 0; /* * Initialize the port based on the machine ID from the bootloader. * Note that we're using macros here instead of switch statement * as machine_is functions are optimized out for the boards that * are not selected. */ do { /* omap7xx/8xx based boards using UART1 with shift 0 */ DEBUG_LL_OMAP7XX(1, herald); DEBUG_LL_OMAP7XX(1, omap_perseus2); /* omap15xx/16xx based boards using UART1 */ DEBUG_LL_OMAP1(1, ams_delta); DEBUG_LL_OMAP1(1, nokia770); DEBUG_LL_OMAP1(1, omap_h2); DEBUG_LL_OMAP1(1, omap_h3); DEBUG_LL_OMAP1(1, omap_innovator); DEBUG_LL_OMAP1(1, omap_osk); DEBUG_LL_OMAP1(1, omap_palmte); DEBUG_LL_OMAP1(1, omap_palmz71); /* omap15xx/16xx based boards using UART2 */ DEBUG_LL_OMAP1(2, omap_palmtt); /* omap15xx/16xx based boards using UART3 */ DEBUG_LL_OMAP1(3, sx1); } while (0); } PK ! �[��� � include/mach/omap7xx.hnu �[��� /* * Hardware definitions for TI OMAP7XX processor. * * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net> * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __ASM_ARCH_OMAP7XX_H #define __ASM_ARCH_OMAP7XX_H /* * ---------------------------------------------------------------------------- * Base addresses * ---------------------------------------------------------------------------- */ /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ #define OMAP7XX_DSP_BASE 0xE0000000 #define OMAP7XX_DSP_SIZE 0x50000 #define OMAP7XX_DSP_START 0xE0000000 #define OMAP7XX_DSPREG_BASE 0xE1000000 #define OMAP7XX_DSPREG_SIZE SZ_128K #define OMAP7XX_DSPREG_START 0xE1000000 #define OMAP7XX_SPI1_BASE 0xfffc0800 #define OMAP7XX_SPI2_BASE 0xfffc1000 /* * ---------------------------------------------------------------------------- * OMAP7XX specific configuration registers * ---------------------------------------------------------------------------- */ #define OMAP7XX_CONFIG_BASE 0xfffe1000 #define OMAP7XX_IO_CONF_0 0xfffe1070 #define OMAP7XX_IO_CONF_1 0xfffe1074 #define OMAP7XX_IO_CONF_2 0xfffe1078 #define OMAP7XX_IO_CONF_3 0xfffe107c #define OMAP7XX_IO_CONF_4 0xfffe1080 #define OMAP7XX_IO_CONF_5 0xfffe1084 #define OMAP7XX_IO_CONF_6 0xfffe1088 #define OMAP7XX_IO_CONF_7 0xfffe108c #define OMAP7XX_IO_CONF_8 0xfffe1090 #define OMAP7XX_IO_CONF_9 0xfffe1094 #define OMAP7XX_IO_CONF_10 0xfffe1098 #define OMAP7XX_IO_CONF_11 0xfffe109c #define OMAP7XX_IO_CONF_12 0xfffe10a0 #define OMAP7XX_IO_CONF_13 0xfffe10a4 #define OMAP7XX_MODE_1 0xfffe1010 #define OMAP7XX_MODE_2 0xfffe1014 /* CSMI specials: in terms of base + offset */ #define OMAP7XX_MODE2_OFFSET 0x14 /* * ---------------------------------------------------------------------------- * OMAP7XX traffic controller configuration registers * ---------------------------------------------------------------------------- */ #define OMAP7XX_FLASH_CFG_0 0xfffecc10 #define OMAP7XX_FLASH_ACFG_0 0xfffecc50 #define OMAP7XX_FLASH_CFG_1 0xfffecc14 #define OMAP7XX_FLASH_ACFG_1 0xfffecc54 /* * ---------------------------------------------------------------------------- * OMAP7XX DSP control registers * ---------------------------------------------------------------------------- */ #define OMAP7XX_ICR_BASE 0xfffbb800 #define OMAP7XX_DSP_M_CTL 0xfffbb804 #define OMAP7XX_DSP_MMU_BASE 0xfffed200 /* * ---------------------------------------------------------------------------- * OMAP7XX PCC_UPLD configuration registers * ---------------------------------------------------------------------------- */ #define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900) #define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00) #endif /* __ASM_ARCH_OMAP7XX_H */ PK ! *M���# �# include/mach/irqs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * arch/arm/plat-omap/include/mach/irqs.h * * Copyright (C) Greg Lonnon 2001 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> * * Copyright (C) 2009 Texas Instruments * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> * * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 * are different. */ #ifndef __ASM_ARCH_OMAP15XX_IRQS_H #define __ASM_ARCH_OMAP15XX_IRQS_H /* * IRQ numbers for interrupt handler 1 * * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below * */ #define INT_CAMERA (NR_IRQS_LEGACY + 1) #define INT_FIQ (NR_IRQS_LEGACY + 3) #define INT_RTDX (NR_IRQS_LEGACY + 6) #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7) #define INT_HOST (NR_IRQS_LEGACY + 8) #define INT_ABORT (NR_IRQS_LEGACY + 9) #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13) #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14) #define INT_UART3 (NR_IRQS_LEGACY + 15) #define INT_TIMER3 (NR_IRQS_LEGACY + 16) #define INT_DMA_CH0_6 (NR_IRQS_LEGACY + 19) #define INT_DMA_CH1_7 (NR_IRQS_LEGACY + 20) #define INT_DMA_CH2_8 (NR_IRQS_LEGACY + 21) #define INT_DMA_CH3 (NR_IRQS_LEGACY + 22) #define INT_DMA_CH4 (NR_IRQS_LEGACY + 23) #define INT_DMA_CH5 (NR_IRQS_LEGACY + 24) #define INT_TIMER1 (NR_IRQS_LEGACY + 26) #define INT_WD_TIMER (NR_IRQS_LEGACY + 27) #define INT_BRIDGE_PUB (NR_IRQS_LEGACY + 28) #define INT_TIMER2 (NR_IRQS_LEGACY + 30) #define INT_LCD_CTRL (NR_IRQS_LEGACY + 31) /* * OMAP-1510 specific IRQ numbers for interrupt handler 1 */ #define INT_1510_IH2_IRQ (NR_IRQS_LEGACY + 0) #define INT_1510_RES2 (NR_IRQS_LEGACY + 2) #define INT_1510_SPI_TX (NR_IRQS_LEGACY + 4) #define INT_1510_SPI_RX (NR_IRQS_LEGACY + 5) #define INT_1510_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) #define INT_1510_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) #define INT_1510_RES12 (NR_IRQS_LEGACY + 12) #define INT_1510_LB_MMU (NR_IRQS_LEGACY + 17) #define INT_1510_RES18 (NR_IRQS_LEGACY + 18) #define INT_1510_LOCAL_BUS (NR_IRQS_LEGACY + 29) /* * OMAP-1610 specific IRQ numbers for interrupt handler 1 */ #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ #define INT_1610_IH2_FIQ (NR_IRQS_LEGACY + 2) #define INT_1610_McBSP2_TX (NR_IRQS_LEGACY + 4) #define INT_1610_McBSP2_RX (NR_IRQS_LEGACY + 5) #define INT_1610_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) #define INT_1610_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) #define INT_1610_LCD_LINE (NR_IRQS_LEGACY + 12) #define INT_1610_GPTIMER1 (NR_IRQS_LEGACY + 17) #define INT_1610_GPTIMER2 (NR_IRQS_LEGACY + 18) #define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29) /* * OMAP-7xx specific IRQ numbers for interrupt handler 1 */ #define INT_7XX_IH2_FIQ (NR_IRQS_LEGACY + 0) #define INT_7XX_IH2_IRQ (NR_IRQS_LEGACY + 1) #define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2) #define INT_7XX_USB_ISO (NR_IRQS_LEGACY + 3) #define INT_7XX_ICR (NR_IRQS_LEGACY + 4) #define INT_7XX_EAC (NR_IRQS_LEGACY + 5) #define INT_7XX_GPIO_BANK1 (NR_IRQS_LEGACY + 6) #define INT_7XX_GPIO_BANK2 (NR_IRQS_LEGACY + 7) #define INT_7XX_GPIO_BANK3 (NR_IRQS_LEGACY + 8) #define INT_7XX_McBSP2TX (NR_IRQS_LEGACY + 10) #define INT_7XX_McBSP2RX (NR_IRQS_LEGACY + 11) #define INT_7XX_McBSP2RX_OVF (NR_IRQS_LEGACY + 12) #define INT_7XX_LCD_LINE (NR_IRQS_LEGACY + 14) #define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15) #define INT_7XX_TIMER3 (NR_IRQS_LEGACY + 16) #define INT_7XX_GPIO_BANK5 (NR_IRQS_LEGACY + 17) #define INT_7XX_GPIO_BANK6 (NR_IRQS_LEGACY + 18) #define INT_7XX_SPGIO_WR (NR_IRQS_LEGACY + 29) /* * IRQ numbers for interrupt handler 2 * * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below */ #define IH2_BASE (NR_IRQS_LEGACY + 32) #define INT_KEYBOARD (1 + IH2_BASE) #define INT_uWireTX (2 + IH2_BASE) #define INT_uWireRX (3 + IH2_BASE) #define INT_I2C (4 + IH2_BASE) #define INT_MPUIO (5 + IH2_BASE) #define INT_USB_HHC_1 (6 + IH2_BASE) #define INT_McBSP3TX (10 + IH2_BASE) #define INT_McBSP3RX (11 + IH2_BASE) #define INT_McBSP1TX (12 + IH2_BASE) #define INT_McBSP1RX (13 + IH2_BASE) #define INT_UART1 (14 + IH2_BASE) #define INT_UART2 (15 + IH2_BASE) #define INT_BT_MCSI1TX (16 + IH2_BASE) #define INT_BT_MCSI1RX (17 + IH2_BASE) #define INT_SOSSI_MATCH (19 + IH2_BASE) #define INT_USB_W2FC (20 + IH2_BASE) #define INT_1WIRE (21 + IH2_BASE) #define INT_OS_TIMER (22 + IH2_BASE) #define INT_MMC (23 + IH2_BASE) #define INT_GAUGE_32K (24 + IH2_BASE) #define INT_RTC_TIMER (25 + IH2_BASE) #define INT_RTC_ALARM (26 + IH2_BASE) #define INT_MEM_STICK (27 + IH2_BASE) /* * OMAP-1510 specific IRQ numbers for interrupt handler 2 */ #define INT_1510_DSP_MMU (28 + IH2_BASE) #define INT_1510_COM_SPI_RO (31 + IH2_BASE) /* * OMAP-1610 specific IRQ numbers for interrupt handler 2 */ #define INT_1610_FAC (0 + IH2_BASE) #define INT_1610_USB_HHC_2 (7 + IH2_BASE) #define INT_1610_USB_OTG (8 + IH2_BASE) #define INT_1610_SoSSI (9 + IH2_BASE) #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) #define INT_1610_DSP_MMU (28 + IH2_BASE) #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) #define INT_1610_STI (32 + IH2_BASE) #define INT_1610_STI_WAKEUP (33 + IH2_BASE) #define INT_1610_GPTIMER3 (34 + IH2_BASE) #define INT_1610_GPTIMER4 (35 + IH2_BASE) #define INT_1610_GPTIMER5 (36 + IH2_BASE) #define INT_1610_GPTIMER6 (37 + IH2_BASE) #define INT_1610_GPTIMER7 (38 + IH2_BASE) #define INT_1610_GPTIMER8 (39 + IH2_BASE) #define INT_1610_GPIO_BANK2 (40 + IH2_BASE) #define INT_1610_GPIO_BANK3 (41 + IH2_BASE) #define INT_1610_MMC2 (42 + IH2_BASE) #define INT_1610_CF (43 + IH2_BASE) #define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) #define INT_1610_GPIO_BANK4 (48 + IH2_BASE) #define INT_1610_SPI (49 + IH2_BASE) #define INT_1610_DMA_CH6 (53 + IH2_BASE) #define INT_1610_DMA_CH7 (54 + IH2_BASE) #define INT_1610_DMA_CH8 (55 + IH2_BASE) #define INT_1610_DMA_CH9 (56 + IH2_BASE) #define INT_1610_DMA_CH10 (57 + IH2_BASE) #define INT_1610_DMA_CH11 (58 + IH2_BASE) #define INT_1610_DMA_CH12 (59 + IH2_BASE) #define INT_1610_DMA_CH13 (60 + IH2_BASE) #define INT_1610_DMA_CH14 (61 + IH2_BASE) #define INT_1610_DMA_CH15 (62 + IH2_BASE) #define INT_1610_NAND (63 + IH2_BASE) #define INT_1610_SHA1MD5 (91 + IH2_BASE) /* * OMAP-7xx specific IRQ numbers for interrupt handler 2 */ #define INT_7XX_HW_ERRORS (0 + IH2_BASE) #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) #define INT_7XX_CFCD (2 + IH2_BASE) #define INT_7XX_CFIREQ (3 + IH2_BASE) #define INT_7XX_I2C (4 + IH2_BASE) #define INT_7XX_PCC (5 + IH2_BASE) #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) #define INT_7XX_SYREN_SPI (8 + IH2_BASE) #define INT_7XX_VLYNQ (9 + IH2_BASE) #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) #define INT_7XX_McBSP1TX (11 + IH2_BASE) #define INT_7XX_McBSP1RX (12 + IH2_BASE) #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) #define INT_7XX_MCSI (16 + IH2_BASE) #define INT_7XX_uWireTX (17 + IH2_BASE) #define INT_7XX_uWireRX (18 + IH2_BASE) #define INT_7XX_SMC_CD (19 + IH2_BASE) #define INT_7XX_SMC_IREQ (20 + IH2_BASE) #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) #define INT_7XX_TIMER32K (22 + IH2_BASE) #define INT_7XX_MMC_SDIO (23 + IH2_BASE) #define INT_7XX_UPLD (24 + IH2_BASE) #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) #define INT_7XX_USB_GENI (29 + IH2_BASE) #define INT_7XX_USB_OTG (30 + IH2_BASE) #define INT_7XX_CAMERA_IF (31 + IH2_BASE) #define INT_7XX_RNG (32 + IH2_BASE) #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) #define INT_7XX_RNG_IDLE (38 + IH2_BASE) #define INT_7XX_MPUIO (39 + IH2_BASE) #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) #define INT_7XX_DMA_CH6 (53 + IH2_BASE) #define INT_7XX_DMA_CH7 (54 + IH2_BASE) #define INT_7XX_DMA_CH8 (55 + IH2_BASE) #define INT_7XX_DMA_CH9 (56 + IH2_BASE) #define INT_7XX_DMA_CH10 (57 + IH2_BASE) #define INT_7XX_DMA_CH11 (58 + IH2_BASE) #define INT_7XX_DMA_CH12 (59 + IH2_BASE) #define INT_7XX_DMA_CH13 (60 + IH2_BASE) #define INT_7XX_DMA_CH14 (61 + IH2_BASE) #define INT_7XX_DMA_CH15 (62 + IH2_BASE) #define INT_7XX_NAND (63 + IH2_BASE) /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and * 16 MPUIO lines */ #define OMAP_MAX_GPIO_LINES 192 #define IH_GPIO_BASE (128 + IH2_BASE) #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) /* External FPGA handles interrupts on Innovator boards */ #define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) #ifdef CONFIG_MACH_OMAP_INNOVATOR #define OMAP_FPGA_NR_IRQS 24 #else #define OMAP_FPGA_NR_IRQS 0 #endif #define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) #define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) #ifdef CONFIG_FIQ #define FIQ_START 1024 #endif #endif PK ! سR# # include/mach/omap1510.hnu �[��� /* * Hardware definitions for TI OMAP1510 processor. * * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __ASM_ARCH_OMAP15XX_H #define __ASM_ARCH_OMAP15XX_H /* * ---------------------------------------------------------------------------- * Base addresses * ---------------------------------------------------------------------------- */ /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ #define OMAP1510_DSP_BASE 0xE0000000 #define OMAP1510_DSP_SIZE 0x28000 #define OMAP1510_DSP_START 0xE0000000 #define OMAP1510_DSPREG_BASE 0xE1000000 #define OMAP1510_DSPREG_SIZE SZ_128K #define OMAP1510_DSPREG_START 0xE1000000 #define OMAP1510_DSP_MMU_BASE (0xfffed200) /* * --------------------------------------------------------------------------- * OMAP-1510 FPGA * --------------------------------------------------------------------------- */ #define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ #define OMAP1510_FPGA_SIZE SZ_4K #define OMAP1510_FPGA_START 0x08000000 /* PA */ /* Revision */ #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) #define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) #define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) #define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) #define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) /* Interrupt status */ #define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) #define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) /* Interrupt mask */ #define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) #define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) /* Reset registers */ #define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) #define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) #define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) #define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) #define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) #define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) #define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) #define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) #define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) #define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) #define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) #define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) #define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) #define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) #define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) #define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) #define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) #define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) #define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) #define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) #define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) #define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) #define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) #define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) /* * Power up Giga UART driver, turn on HID clock. * Turn off BT power, since we're not using it and it * draws power. */ #define OMAP1510_FPGA_RESET_VALUE 0x42 #define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) #define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) #define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) #define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) #define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) #define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) #define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) #define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) /* * Innovator/OMAP1510 FPGA HID register bit definitions */ #define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ #define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ #define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ #define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ #define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ #define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ #define OMAP1510_FPGA_HID_rsrvd (1<<6) #define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ /* The FPGA IRQ is cascaded through GPIO_13 */ #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) /* IRQ Numbers for interrupts muxed through the FPGA */ #define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) #define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) #define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) #define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) #define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) #define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) #define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) #define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) #define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) #define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) #define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) #define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) #define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) #define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) #define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) #define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) #define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) #define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) #define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) #define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) #define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) #define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) #define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) #define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) #endif /* __ASM_ARCH_OMAP15XX_H */ PK ! )ߢ�! �! include/mach/omap16xx.hnu �[��� /* * Hardware definitions for TI OMAP1610/5912/1710 processors. * * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __ASM_ARCH_OMAP16XX_H #define __ASM_ARCH_OMAP16XX_H /* * ---------------------------------------------------------------------------- * Base addresses * ---------------------------------------------------------------------------- */ /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ #define OMAP16XX_DSP_BASE 0xE0000000 #define OMAP16XX_DSP_SIZE 0x28000 #define OMAP16XX_DSP_START 0xE0000000 #define OMAP16XX_DSPREG_BASE 0xE1000000 #define OMAP16XX_DSPREG_SIZE SZ_128K #define OMAP16XX_DSPREG_START 0xE1000000 #define OMAP16XX_SEC_BASE 0xFFFE4000 #define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000) #define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800) #define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000) /* * --------------------------------------------------------------------------- * Interrupts * --------------------------------------------------------------------------- */ #define OMAP_IH2_0_BASE (0xfffe0000) #define OMAP_IH2_1_BASE (0xfffe0100) #define OMAP_IH2_2_BASE (0xfffe0200) #define OMAP_IH2_3_BASE (0xfffe0300) #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) #define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) #define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) #define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) #define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) #define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) #define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) #define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) #define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) #define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) #define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) #define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) #define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) #define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) #define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) #define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) #define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) #define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) #define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) #define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) #define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) /* * ---------------------------------------------------------------------------- * Clocks * ---------------------------------------------------------------------------- */ #define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) /* * ---------------------------------------------------------------------------- * Pin configuration registers * ---------------------------------------------------------------------------- */ #define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8) #define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9) #define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10) #define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11) #define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13) /* * ---------------------------------------------------------------------------- * System control registers * ---------------------------------------------------------------------------- */ #define OMAP1610_RESET_CONTROL 0xfffe1140 /* * --------------------------------------------------------------------------- * TIPB bus interface * --------------------------------------------------------------------------- */ #define TIPB_SWITCH_BASE (0xfffbc800) #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) /* UART3 Registers Mapping through MPU bus */ #define UART3_RHR (OMAP1_UART3_BASE + 0) #define UART3_THR (OMAP1_UART3_BASE + 0) #define UART3_DLL (OMAP1_UART3_BASE + 0) #define UART3_IER (OMAP1_UART3_BASE + 4) #define UART3_DLH (OMAP1_UART3_BASE + 4) #define UART3_IIR (OMAP1_UART3_BASE + 8) #define UART3_FCR (OMAP1_UART3_BASE + 8) #define UART3_EFR (OMAP1_UART3_BASE + 8) #define UART3_LCR (OMAP1_UART3_BASE + 0x0C) #define UART3_MCR (OMAP1_UART3_BASE + 0x10) #define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10) #define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14) #define UART3_LSR (OMAP1_UART3_BASE + 0x14) #define UART3_TCR (OMAP1_UART3_BASE + 0x18) #define UART3_MSR (OMAP1_UART3_BASE + 0x18) #define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18) #define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C) #define UART3_SPR (OMAP1_UART3_BASE + 0x1C) #define UART3_TLR (OMAP1_UART3_BASE + 0x1C) #define UART3_MDR1 (OMAP1_UART3_BASE + 0x20) #define UART3_MDR2 (OMAP1_UART3_BASE + 0x24) #define UART3_SFLSR (OMAP1_UART3_BASE + 0x28) #define UART3_TXFLL (OMAP1_UART3_BASE + 0x28) #define UART3_RESUME (OMAP1_UART3_BASE + 0x2C) #define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C) #define UART3_SFREGL (OMAP1_UART3_BASE + 0x30) #define UART3_RXFLL (OMAP1_UART3_BASE + 0x30) #define UART3_SFREGH (OMAP1_UART3_BASE + 0x34) #define UART3_RXFLH (OMAP1_UART3_BASE + 0x34) #define UART3_BLR (OMAP1_UART3_BASE + 0x38) #define UART3_ACREG (OMAP1_UART3_BASE + 0x3C) #define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C) #define UART3_SCR (OMAP1_UART3_BASE + 0x40) #define UART3_SSR (OMAP1_UART3_BASE + 0x44) #define UART3_EBLR (OMAP1_UART3_BASE + 0x48) #define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C) #define UART3_MVR (OMAP1_UART3_BASE + 0x50) /* * --------------------------------------------------------------------------- * Watchdog timer * --------------------------------------------------------------------------- */ /* 32-bit Watchdog timer in OMAP 16XX */ #define OMAP_16XX_WATCHDOG_BASE (0xfffeb000) #define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00) #define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10) #define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14) #define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24) #define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28) #define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c) #define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30) #define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34) #define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48) #define WCLR_PRE_SHIFT 5 #define WCLR_PTV_SHIFT 2 #define WWPS_W_PEND_WSPR (1 << 4) #define WWPS_W_PEND_WTGR (1 << 3) #define WWPS_W_PEND_WLDR (1 << 2) #define WWPS_W_PEND_WCRR (1 << 1) #define WWPS_W_PEND_WCLR (1 << 0) #define WSPR_ENABLE_0 (0x0000bbbb) #define WSPR_ENABLE_1 (0x00004444) #define WSPR_DISABLE_0 (0x0000aaaa) #define WSPR_DISABLE_1 (0x00005555) #define OMAP16XX_DSP_MMU_BASE (0xfffed200) #define OMAP16XX_MAILBOX_BASE (0xfffcf000) #endif /* __ASM_ARCH_OMAP16XX_H */ PK ! �#�� � include/mach/lcdc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * arch/arm/mach-omap1/include/mach/lcdc.h * * Extracted from drivers/video/omap/lcdc.c * Copyright (C) 2004 Nokia Corporation * Author: Imre Deak <imre.deak@nokia.com> */ #ifndef __MACH_LCDC_H__ #define __MACH_LCDC_H__ #define OMAP_LCDC_BASE 0xfffec000 #define OMAP_LCDC_SIZE 256 #define OMAP_LCDC_IRQ INT_LCD_CTRL #define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00) #define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04) #define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08) #define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c) #define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10) #define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14) #define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18) #define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c) #define OMAP_LCDC_STAT_DONE (1 << 0) #define OMAP_LCDC_STAT_VSYNC (1 << 1) #define OMAP_LCDC_STAT_SYNC_LOST (1 << 2) #define OMAP_LCDC_STAT_ABC (1 << 3) #define OMAP_LCDC_STAT_LINE_INT (1 << 4) #define OMAP_LCDC_STAT_FUF (1 << 5) #define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6) #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) #define OMAP_LCDC_CTRL_LCD_TFT (1 << 7) #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10) #define OMAP_LCDC_IRQ_VSYNC (1 << 2) #define OMAP_LCDC_IRQ_DONE (1 << 3) #define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4) #define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5) #define OMAP_LCDC_IRQ_LINE (1 << 6) #define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2) #endif /* __MACH_LCDC_H__ */ PK ! ��R] ] include/mach/serial.hnu �[��� /* * Copyright (C) 2009 Texas Instruments * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H #include <linux/init.h> /* * Memory entry used for the DEBUG_LL UART configuration, relative to * start of RAM. See also uncompress.h and debug-macro.S. * * Note that using a memory location for storing the UART configuration * has at least two limitations: * * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the * uncompress code could then partially overwrite itself * 2. We assume printascii is called at least once before paging_init, * and addruart has a chance to read OMAP_UART_INFO */ #define OMAP_UART_INFO_OFS 0x3ffc #define OMAP_PORT_SHIFT 2 #define OMAP7XX_PORT_SHIFT 0 #define OMAP1510_BASE_BAUD (12000000/16) #define OMAP16XX_BASE_BAUD (48000000/16) /* * DEBUG_LL port encoding stored into the UART1 scratchpad register by * decomp_setup in uncompress.h */ #define OMAP1UART1 11 #define OMAP1UART2 12 #define OMAP1UART3 13 #ifndef __ASSEMBLER__ extern void omap_serial_init(void); #endif #endif PK ! �� � � include/mach/mtd-xip.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * MTD primitives for XIP support. Architecture specific functions. * * Do not include this file directly. It's included from linux/mtd/xip.h * * Author: Vladimir Barinov <vbarinov@embeddedalley.com> * * (c) 2005 MontaVista Software, Inc. */ #ifndef __ARCH_OMAP_MTD_XIP_H__ #define __ARCH_OMAP_MTD_XIP_H__ #include <mach/hardware.h> #define OMAP_MPU_TIMER_BASE (0xfffec500) #define OMAP_MPU_TIMER_OFFSET 0x100 typedef struct { u32 cntl; /* CNTL_TIMER, R/W */ u32 load_tim; /* LOAD_TIM, W */ u32 read_tim; /* READ_TIM, R */ } xip_omap_mpu_timer_regs_t; #define xip_omap_mpu_timer_base(n) \ ((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ (n)*OMAP_MPU_TIMER_OFFSET)) static inline unsigned long xip_omap_mpu_timer_read(int nr) { volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr); return timer->read_tim; } #define xip_irqpending() \ (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR)) #define xip_currtime() (~xip_omap_mpu_timer_read(0)) /* * It's permitted to do approximation for xip_elapsed_since macro * (see linux/mtd/xip.h) */ #ifdef CONFIG_MACH_OMAP_PERSEUS2 #define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7) #else #define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6) #endif /* * xip_cpu_idle() is used when waiting for a delay equal or larger than * the system timer tick period. This should put the CPU into idle mode * to save power and to be woken up only when some interrupts are pending. * As above, this should not rely upon standard kernel code. */ #define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1)) #endif /* __ARCH_OMAP_MTD_XIP_H__ */ PK ! �w`, `, include/mach/hardware.hnu �[��� /* * arch/arm/mach-omap1/include/mach/hardware.h * * Hardware definitions for TI OMAP processors and boards * * NOTE: Please put device driver specific defines into a separate header * file for each driver. * * Copyright (C) 2001 RidgeRun, Inc. * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> * * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> * and Dirk Behme <dirk.behme@de.bosch.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __ASM_ARCH_OMAP_HARDWARE_H #define __ASM_ARCH_OMAP_HARDWARE_H #include <linux/sizes.h> #ifndef __ASSEMBLER__ #include <asm/types.h> #include <mach/soc.h> /* * NOTE: Please use ioremap + __raw_read/write where possible instead of these */ extern u8 omap_readb(u32 pa); extern u16 omap_readw(u32 pa); extern u32 omap_readl(u32 pa); extern void omap_writeb(u8 v, u32 pa); extern void omap_writew(u16 v, u32 pa); extern void omap_writel(u32 v, u32 pa); #include <mach/tc.h> /* Almost all documentation for chip and board memory maps assumes * BM is clear. Most devel boards have a switch to control booting * from NOR flash (using external chipselect 3) rather than mask ROM, * which uses BM to interchange the physical CS0 and CS3 addresses. */ static inline u32 omap_cs0m_phys(void) { return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) ? OMAP_CS3_PHYS : 0; } static inline u32 omap_cs3_phys(void) { return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) ? 0 : OMAP_CS3_PHYS; } #endif /* ifndef __ASSEMBLER__ */ #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) #include <mach/serial.h> /* * --------------------------------------------------------------------------- * Common definitions for all OMAP processors * NOTE: Put all processor or board specific parts to the special header * files. * --------------------------------------------------------------------------- */ /* * ---------------------------------------------------------------------------- * Timers * ---------------------------------------------------------------------------- */ #define OMAP_MPU_TIMER1_BASE (0xfffec500) #define OMAP_MPU_TIMER2_BASE (0xfffec600) #define OMAP_MPU_TIMER3_BASE (0xfffec700) #define MPU_TIMER_FREE (1 << 6) #define MPU_TIMER_CLOCK_ENABLE (1 << 5) #define MPU_TIMER_AR (1 << 1) #define MPU_TIMER_ST (1 << 0) /* * ---------------------------------------------------------------------------- * Clocks * ---------------------------------------------------------------------------- */ #define CLKGEN_REG_BASE (0xfffece00) #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) #define CK_RATEF 1 #define CK_IDLEF 2 #define CK_ENABLEF 4 #define CK_SELECTF 8 #define SETARM_IDLE_SHIFT /* DPLL control registers */ #define DPLL_CTL (0xfffecf00) /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) /* * --------------------------------------------------------------------------- * UPLD * --------------------------------------------------------------------------- */ #define ULPD_REG_BASE (0xfffe0800) #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) # define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ # define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) # define SOFT_UDC_REQ (1 << 4) # define SOFT_USB_CLK_REQ (1 << 3) # define SOFT_DPLL_REQ (1 << 0) #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) # define DIS_MMC2_DPLL_REQ (1 << 11) # define DIS_MMC1_DPLL_REQ (1 << 10) # define DIS_UART3_DPLL_REQ (1 << 9) # define DIS_UART2_DPLL_REQ (1 << 8) # define DIS_UART1_DPLL_REQ (1 << 7) # define DIS_USB_HOST_DPLL_REQ (1 << 6) #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) /* * --------------------------------------------------------------------------- * Watchdog timer * --------------------------------------------------------------------------- */ /* Watchdog timer within the OMAP3.2 gigacell */ #define OMAP_MPU_WATCHDOG_BASE (0xfffec800) #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) /* * --------------------------------------------------------------------------- * Interrupts * --------------------------------------------------------------------------- */ #ifdef CONFIG_ARCH_OMAP1 /* * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c * or something similar.. -- PFM. */ #define OMAP_IH1_BASE 0xfffecb00 #define OMAP_IH2_BASE 0xfffe0000 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) #define IRQ_ITR_REG_OFFSET 0x00 #define IRQ_MIR_REG_OFFSET 0x04 #define IRQ_SIR_IRQ_REG_OFFSET 0x10 #define IRQ_SIR_FIQ_REG_OFFSET 0x14 #define IRQ_CONTROL_REG_OFFSET 0x18 #define IRQ_ISR_REG_OFFSET 0x9c #define IRQ_ILR0_REG_OFFSET 0x1c #define IRQ_GMR_REG_OFFSET 0xa0 #endif /* * ---------------------------------------------------------------------------- * System control registers * ---------------------------------------------------------------------------- */ #define MOD_CONF_CTRL_0 0xfffe1080 #define MOD_CONF_CTRL_1 0xfffe1110 /* * ---------------------------------------------------------------------------- * Pin multiplexing registers * ---------------------------------------------------------------------------- */ #define FUNC_MUX_CTRL_0 0xfffe1000 #define FUNC_MUX_CTRL_1 0xfffe1004 #define FUNC_MUX_CTRL_2 0xfffe1008 #define COMP_MODE_CTRL_0 0xfffe100c #define FUNC_MUX_CTRL_3 0xfffe1010 #define FUNC_MUX_CTRL_4 0xfffe1014 #define FUNC_MUX_CTRL_5 0xfffe1018 #define FUNC_MUX_CTRL_6 0xfffe101C #define FUNC_MUX_CTRL_7 0xfffe1020 #define FUNC_MUX_CTRL_8 0xfffe1024 #define FUNC_MUX_CTRL_9 0xfffe1028 #define FUNC_MUX_CTRL_A 0xfffe102C #define FUNC_MUX_CTRL_B 0xfffe1030 #define FUNC_MUX_CTRL_C 0xfffe1034 #define FUNC_MUX_CTRL_D 0xfffe1038 #define PULL_DWN_CTRL_0 0xfffe1040 #define PULL_DWN_CTRL_1 0xfffe1044 #define PULL_DWN_CTRL_2 0xfffe1048 #define PULL_DWN_CTRL_3 0xfffe104c #define PULL_DWN_CTRL_4 0xfffe10ac /* OMAP-1610 specific multiplexing registers */ #define FUNC_MUX_CTRL_E 0xfffe1090 #define FUNC_MUX_CTRL_F 0xfffe1094 #define FUNC_MUX_CTRL_10 0xfffe1098 #define FUNC_MUX_CTRL_11 0xfffe109c #define FUNC_MUX_CTRL_12 0xfffe10a0 #define PU_PD_SEL_0 0xfffe10b4 #define PU_PD_SEL_1 0xfffe10b8 #define PU_PD_SEL_2 0xfffe10bc #define PU_PD_SEL_3 0xfffe10c0 #define PU_PD_SEL_4 0xfffe10c4 /* Timer32K for 1610 and 1710*/ #define OMAP_TIMER32K_BASE 0xFFFBC400 /* * --------------------------------------------------------------------------- * TIPB bus interface * --------------------------------------------------------------------------- */ #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) /* * ---------------------------------------------------------------------------- * MPUI interface * ---------------------------------------------------------------------------- */ #define MPUI_BASE (0xfffec900) #define MPUI_CTRL (MPUI_BASE + 0x0) #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) #define MPUI_STATUS_REG (MPUI_BASE + 0x10) #define MPUI_DSP_STATUS (MPUI_BASE + 0x14) #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) /* * ---------------------------------------------------------------------------- * LED Pulse Generator * ---------------------------------------------------------------------------- */ #define OMAP_LPG1_BASE 0xfffbd000 #define OMAP_LPG2_BASE 0xfffbd800 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) /* * ---------------------------------------------------------------------------- * Pulse-Width Light * ---------------------------------------------------------------------------- */ #define OMAP_PWL_BASE 0xfffb5800 #define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) #define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) /* * --------------------------------------------------------------------------- * Processor specific defines * --------------------------------------------------------------------------- */ #include "omap7xx.h" #include "omap1510.h" #include "omap16xx.h" #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ PK ! ��awT T include/mach/soc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * OMAP cpu type detection * * Copyright (C) 2004, 2008 Nokia Corporation * * Copyright (C) 2009-11 Texas Instruments. * * Written by Tony Lindgren <tony.lindgren@nokia.com> * * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> */ #ifndef __ASM_ARCH_OMAP_CPU_H #define __ASM_ARCH_OMAP_CPU_H #include <asm/irq.h> #include <mach/hardware.h> #include <mach/irqs.h> #ifndef __ASSEMBLY__ #include <linux/bitops.h> /* * Test if multicore OMAP support is needed */ #undef MULTI_OMAP1 #undef OMAP_NAME #ifdef CONFIG_ARCH_OMAP730 # ifdef OMAP_NAME # undef MULTI_OMAP1 # define MULTI_OMAP1 # else # define OMAP_NAME omap730 # endif #endif #ifdef CONFIG_ARCH_OMAP850 # ifdef OMAP_NAME # undef MULTI_OMAP1 # define MULTI_OMAP1 # else # define OMAP_NAME omap850 # endif #endif #ifdef CONFIG_ARCH_OMAP15XX # ifdef OMAP_NAME # undef MULTI_OMAP1 # define MULTI_OMAP1 # else # define OMAP_NAME omap1510 # endif #endif #ifdef CONFIG_ARCH_OMAP16XX # ifdef OMAP_NAME # undef MULTI_OMAP1 # define MULTI_OMAP1 # else # define OMAP_NAME omap16xx # endif #endif /* * omap_rev bits: * CPU id bits (0730, 1510, 1710, 2422...) [31:16] * CPU revision (See _REV_ defined in cpu.h) [15:08] * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00] */ unsigned int omap_rev(void); /* * Get the CPU revision for OMAP devices */ #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) /* * Macros to group OMAP into cpu classes. * These can be used in most places. * cpu_is_omap7xx(): True for OMAP730, OMAP850 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 */ #define GET_OMAP_CLASS (omap_rev() & 0xff) #define IS_OMAP_CLASS(class, id) \ static inline int is_omap ##class (void) \ { \ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ } #define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) #define IS_OMAP_SUBCLASS(subclass, id) \ static inline int is_omap ##subclass (void) \ { \ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ } IS_OMAP_CLASS(7xx, 0x07) IS_OMAP_CLASS(15xx, 0x15) IS_OMAP_CLASS(16xx, 0x16) #define cpu_is_omap7xx() 0 #define cpu_is_omap15xx() 0 #define cpu_is_omap16xx() 0 #if defined(MULTI_OMAP1) # if defined(CONFIG_ARCH_OMAP730) # undef cpu_is_omap7xx # define cpu_is_omap7xx() is_omap7xx() # endif # if defined(CONFIG_ARCH_OMAP850) # undef cpu_is_omap7xx # define cpu_is_omap7xx() is_omap7xx() # endif # if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap15xx # define cpu_is_omap15xx() is_omap15xx() # endif # if defined(CONFIG_ARCH_OMAP16XX) # undef cpu_is_omap16xx # define cpu_is_omap16xx() is_omap16xx() # endif #else # if defined(CONFIG_ARCH_OMAP730) # undef cpu_is_omap7xx # define cpu_is_omap7xx() 1 # endif # if defined(CONFIG_ARCH_OMAP850) # undef cpu_is_omap7xx # define cpu_is_omap7xx() 1 # endif # if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap15xx # define cpu_is_omap15xx() 1 # endif # if defined(CONFIG_ARCH_OMAP16XX) # undef cpu_is_omap16xx # define cpu_is_omap16xx() 1 # endif #endif /* * Macros to detect individual cpu types. * These are only rarely needed. * cpu_is_omap310(): True for OMAP310 * cpu_is_omap1510(): True for OMAP1510 * cpu_is_omap1610(): True for OMAP1610 * cpu_is_omap1611(): True for OMAP1611 * cpu_is_omap5912(): True for OMAP5912 * cpu_is_omap1621(): True for OMAP1621 * cpu_is_omap1710(): True for OMAP1710 */ #define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) #define IS_OMAP_TYPE(type, id) \ static inline int is_omap ##type (void) \ { \ return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ } IS_OMAP_TYPE(310, 0x0310) IS_OMAP_TYPE(1510, 0x1510) IS_OMAP_TYPE(1610, 0x1610) IS_OMAP_TYPE(1611, 0x1611) IS_OMAP_TYPE(5912, 0x1611) IS_OMAP_TYPE(1621, 0x1621) IS_OMAP_TYPE(1710, 0x1710) #define cpu_is_omap310() 0 #define cpu_is_omap1510() 0 #define cpu_is_omap1610() 0 #define cpu_is_omap5912() 0 #define cpu_is_omap1611() 0 #define cpu_is_omap1621() 0 #define cpu_is_omap1710() 0 /* These are needed to compile common code */ #ifdef CONFIG_ARCH_OMAP1 #define cpu_is_omap242x() 0 #define cpu_is_omap2430() 0 #define cpu_is_omap243x() 0 #define cpu_is_omap24xx() 0 #define cpu_is_omap34xx() 0 #define cpu_is_omap44xx() 0 #define soc_is_omap54xx() 0 #define soc_is_dra7xx() 0 #define soc_is_am33xx() 0 #define cpu_class_is_omap1() 1 #define cpu_class_is_omap2() 0 #endif /* * Whether we have MULTI_OMAP1 or not, we still need to distinguish * between 310 vs. 1510 and 1611B/5912 vs. 1710. */ #if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap310 # undef cpu_is_omap1510 # define cpu_is_omap310() is_omap310() # define cpu_is_omap1510() is_omap1510() #endif #if defined(CONFIG_ARCH_OMAP16XX) # undef cpu_is_omap1610 # undef cpu_is_omap1611 # undef cpu_is_omap5912 # undef cpu_is_omap1621 # undef cpu_is_omap1710 # define cpu_is_omap1610() is_omap1610() # define cpu_is_omap1611() is_omap1611() # define cpu_is_omap5912() is_omap5912() # define cpu_is_omap1621() is_omap1621() # define cpu_is_omap1710() is_omap1710() #endif #endif /* __ASSEMBLY__ */ #endif PK ! ��2 � � include/mach/memory.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-omap1/include/mach/memory.h */ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H /* REVISIT: omap1 legacy drivers still rely on this */ #include <mach/soc.h> #endif PK ! }) � � include/mach/usb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * FIXME correct answer depends on hmc_mode, * as does (on omap1) any nonzero value for config->otg port number */ #if IS_ENABLED(CONFIG_USB_OMAP) #define is_usb0_device(config) 1 #else #define is_usb0_device(config) 0 #endif #include <linux/platform_data/usb-omap1.h> #if IS_ENABLED(CONFIG_USB_SUPPORT) void omap1_usb_init(struct omap_usb_config *pdata); #else static inline void omap1_usb_init(struct omap_usb_config *pdata) { } #endif #define OMAP1_OTG_BASE 0xfffb0400 #define OMAP1_UDC_BASE 0xfffb4000 #define OMAP1_OHCI_BASE 0xfffba000 #define OMAP2_OHCI_BASE 0x4805e000 #define OMAP2_UDC_BASE 0x4805e200 #define OMAP2_OTG_BASE 0x4805e300 #define OTG_BASE OMAP1_OTG_BASE #define UDC_BASE OMAP1_UDC_BASE #define OMAP_OHCI_BASE OMAP1_OHCI_BASE /* * OTG and transceiver registers, for OMAPs starting with ARM926 */ #define OTG_REV (OTG_BASE + 0x00) #define OTG_SYSCON_1 (OTG_BASE + 0x04) # define USB2_TRX_MODE(w) (((w)>>24)&0x07) # define USB1_TRX_MODE(w) (((w)>>20)&0x07) # define USB0_TRX_MODE(w) (((w)>>16)&0x07) # define OTG_IDLE_EN (1 << 15) # define HST_IDLE_EN (1 << 14) # define DEV_IDLE_EN (1 << 13) # define OTG_RESET_DONE (1 << 2) # define OTG_SOFT_RESET (1 << 1) #define OTG_SYSCON_2 (OTG_BASE + 0x08) # define OTG_EN (1 << 31) # define USBX_SYNCHRO (1 << 30) # define OTG_MST16 (1 << 29) # define SRP_GPDATA (1 << 28) # define SRP_GPDVBUS (1 << 27) # define SRP_GPUVBUS(w) (((w)>>24)&0x07) # define A_WAIT_VRISE(w) (((w)>>20)&0x07) # define B_ASE_BRST(w) (((w)>>16)&0x07) # define SRP_DPW (1 << 14) # define SRP_DATA (1 << 13) # define SRP_VBUS (1 << 12) # define OTG_PADEN (1 << 10) # define HMC_PADEN (1 << 9) # define UHOST_EN (1 << 8) # define HMC_TLLSPEED (1 << 7) # define HMC_TLLATTACH (1 << 6) # define OTG_HMC(w) (((w)>>0)&0x3f) #define OTG_CTRL (OTG_BASE + 0x0c) # define OTG_USB2_EN (1 << 29) # define OTG_USB2_DP (1 << 28) # define OTG_USB2_DM (1 << 27) # define OTG_USB1_EN (1 << 26) # define OTG_USB1_DP (1 << 25) # define OTG_USB1_DM (1 << 24) # define OTG_USB0_EN (1 << 23) # define OTG_USB0_DP (1 << 22) # define OTG_USB0_DM (1 << 21) # define OTG_ASESSVLD (1 << 20) # define OTG_BSESSEND (1 << 19) # define OTG_BSESSVLD (1 << 18) # define OTG_VBUSVLD (1 << 17) # define OTG_ID (1 << 16) # define OTG_DRIVER_SEL (1 << 15) # define OTG_A_SETB_HNPEN (1 << 12) # define OTG_A_BUSREQ (1 << 11) # define OTG_B_HNPEN (1 << 9) # define OTG_B_BUSREQ (1 << 8) # define OTG_BUSDROP (1 << 7) # define OTG_PULLDOWN (1 << 5) # define OTG_PULLUP (1 << 4) # define OTG_DRV_VBUS (1 << 3) # define OTG_PD_VBUS (1 << 2) # define OTG_PU_VBUS (1 << 1) # define OTG_PU_ID (1 << 0) #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ # define DRIVER_SWITCH (1 << 15) # define A_VBUS_ERR (1 << 13) # define A_REQ_TMROUT (1 << 12) # define A_SRP_DETECT (1 << 11) # define B_HNP_FAIL (1 << 10) # define B_SRP_TMROUT (1 << 9) # define B_SRP_DONE (1 << 8) # define B_SRP_STARTED (1 << 7) # define OPRT_CHG (1 << 0) #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ // same bits as in IRQ_EN #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ # define OTGVPD (1 << 14) # define OTGVPU (1 << 13) # define OTGPUID (1 << 12) # define USB2VDR (1 << 10) # define USB2PDEN (1 << 9) # define USB2PUEN (1 << 8) # define USB1VDR (1 << 6) # define USB1PDEN (1 << 5) # define USB1PUEN (1 << 4) # define USB0VDR (1 << 2) # define USB0PDEN (1 << 1) # define USB0PUEN (1 << 0) #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ /*-------------------------------------------------------------------------*/ /* OMAP1 */ #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) # define CONF_USB2_UNI_R (1 << 8) # define CONF_USB1_UNI_R (1 << 7) # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) # define CONF_USB0_ISOLATE_R (1 << 3) # define CONF_USB_PWRDN_DM_R (1 << 2) # define CONF_USB_PWRDN_DP_R (1 << 1) PK ! ,pܗ}! }! include/mach/mux.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * arch/arm/plat-omap/include/mach/mux.h * * Table of the Omap register configurations for the FUNC_MUX and * PULL_DWN combinations. * * Copyright (C) 2004 - 2008 Texas Instruments Inc. * Copyright (C) 2003 - 2008 Nokia Corporation * * Written by Tony Lindgren * * NOTE: Please use the following naming style for new pin entries. * For example, W8_1610_MMC2_DAT0, where: * - W8 = ball * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 * - MMC2_DAT0 = function */ #ifndef __ASM_ARCH_MUX_H #define __ASM_ARCH_MUX_H #define PU_PD_SEL_NA 0 /* No pu_pd reg available */ #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */ #ifdef CONFIG_OMAP_MUX_DEBUG #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ .mux_reg = FUNC_MUX_CTRL_##reg, \ .mask_offset = mode_offset, \ .mask = mode, #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ .pull_reg = PULL_DWN_CTRL_##reg, \ .pull_bit = bit, \ .pull_val = status, #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ .pu_pd_reg = PU_PD_SEL_##reg, \ .pu_pd_val = status, #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \ .mux_reg = OMAP7XX_IO_CONF_##reg, \ .mask_offset = mode_offset, \ .mask = mode, #define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \ .pull_reg = OMAP7XX_IO_CONF_##reg, \ .pull_bit = bit, \ .pull_val = status, #else #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ .mask_offset = mode_offset, \ .mask = mode, #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ .pull_bit = bit, \ .pull_val = status, #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ .pu_pd_val = status, #define MUX_REG_7XX(reg, mode_offset, mode) \ .mux_reg = OMAP7XX_IO_CONF_##reg, \ .mask_offset = mode_offset, \ .mask = mode, #define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \ .pull_bit = bit, \ .pull_val = status, #endif /* CONFIG_OMAP_MUX_DEBUG */ #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ pull_reg, pull_bit, pull_status, \ pu_pd_reg, pu_pd_status, debug_status) \ { \ .name = desc, \ .debug = debug_status, \ MUX_REG(mux_reg, mode_offset, mode) \ PULL_REG(pull_reg, pull_bit, pull_status) \ PU_PD_REG(pu_pd_reg, pu_pd_status) \ }, /* * OMAP730/850 has a slightly different config for the pin mux. * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and * not the FUNC_MUX_CTRL_x regs from hardware.h * - for pull-up/down, only has one enable bit which is in the same register * as mux config */ #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ pull_bit, pull_status, debug_status)\ { \ .name = desc, \ .debug = debug_status, \ MUX_REG_7XX(mux_reg, mode_offset, mode) \ PULL_REG_7XX(mux_reg, pull_bit, pull_status) \ PU_PD_REG(NA, 0) \ }, struct pin_config { char *name; const unsigned int mux_reg; unsigned char debug; const unsigned char mask_offset; const unsigned char mask; const char *pull_name; const unsigned int pull_reg; const unsigned char pull_val; const unsigned char pull_bit; const char *pu_pd_name; const unsigned int pu_pd_reg; const unsigned char pu_pd_val; #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) const char *mux_reg_name; #endif }; enum omap7xx_index { /* OMAP 730 keyboard */ E2_7XX_KBR0, J7_7XX_KBR1, E1_7XX_KBR2, F3_7XX_KBR3, D2_7XX_KBR4, C2_7XX_KBC0, D3_7XX_KBC1, E4_7XX_KBC2, F4_7XX_KBC3, E3_7XX_KBC4, /* USB */ AA17_7XX_USB_DM, W16_7XX_USB_PU_EN, W17_7XX_USB_VBUSI, W18_7XX_USB_DMCK_OUT, W19_7XX_USB_DCRST, /* MMC */ MMC_7XX_CMD, MMC_7XX_CLK, MMC_7XX_DAT0, /* I2C */ I2C_7XX_SCL, I2C_7XX_SDA, /* SPI */ SPI_7XX_1, SPI_7XX_2, SPI_7XX_3, SPI_7XX_4, SPI_7XX_5, SPI_7XX_6, /* UART */ UART_7XX_1, UART_7XX_2, }; enum omap1xxx_index { /* UART1 (BT_UART_GATING)*/ UART1_TX = 0, UART1_RTS, /* UART2 (COM_UART_GATING)*/ UART2_TX, UART2_RX, UART2_CTS, UART2_RTS, /* UART3 (GIGA_UART_GATING) */ UART3_TX, UART3_RX, UART3_CTS, UART3_RTS, UART3_CLKREQ, UART3_BCLK, /* 12MHz clock out */ Y15_1610_UART3_RTS, /* PWT & PWL */ PWT, PWL, /* USB master generic */ R18_USB_VBUS, R18_1510_USB_GPIO0, W4_USB_PUEN, W4_USB_CLKO, W4_USB_HIGHZ, W4_GPIO58, /* USB1 master */ USB1_SUSP, USB1_SEO, W13_1610_USB1_SE0, USB1_TXEN, USB1_TXD, USB1_VP, USB1_VM, USB1_RCV, USB1_SPEED, R13_1610_USB1_SPEED, R13_1710_USB1_SE0, /* USB2 master */ USB2_SUSP, USB2_VP, USB2_TXEN, USB2_VM, USB2_RCV, USB2_SEO, USB2_TXD, /* OMAP-1510 GPIO */ R18_1510_GPIO0, R19_1510_GPIO1, M14_1510_GPIO2, /* OMAP1610 GPIO */ P18_1610_GPIO3, Y15_1610_GPIO17, /* OMAP-1710 GPIO */ R18_1710_GPIO0, V2_1710_GPIO10, N21_1710_GPIO14, W15_1710_GPIO40, /* MPUIO */ MPUIO2, N15_1610_MPUIO2, MPUIO4, MPUIO5, T20_1610_MPUIO5, W11_1610_MPUIO6, V10_1610_MPUIO7, W11_1610_MPUIO9, V10_1610_MPUIO10, W10_1610_MPUIO11, E20_1610_MPUIO13, U20_1610_MPUIO14, E19_1610_MPUIO15, /* MCBSP2 */ MCBSP2_CLKR, MCBSP2_CLKX, MCBSP2_DR, MCBSP2_DX, MCBSP2_FSR, MCBSP2_FSX, /* MCBSP3 */ MCBSP3_CLKX, /* Misc ballouts */ BALLOUT_V8_ARMIO3, N20_HDQ, /* OMAP-1610 MMC2 */ W8_1610_MMC2_DAT0, V8_1610_MMC2_DAT1, W15_1610_MMC2_DAT2, R10_1610_MMC2_DAT3, Y10_1610_MMC2_CLK, Y8_1610_MMC2_CMD, V9_1610_MMC2_CMDDIR, V5_1610_MMC2_DATDIR0, W19_1610_MMC2_DATDIR1, R18_1610_MMC2_CLKIN, /* OMAP-1610 External Trace Interface */ M19_1610_ETM_PSTAT0, L15_1610_ETM_PSTAT1, L18_1610_ETM_PSTAT2, L19_1610_ETM_D0, J19_1610_ETM_D6, J18_1610_ETM_D7, /* OMAP16XX GPIO */ P20_1610_GPIO4, V9_1610_GPIO7, W8_1610_GPIO9, N20_1610_GPIO11, N19_1610_GPIO13, P10_1610_GPIO22, V5_1610_GPIO24, AA20_1610_GPIO_41, W19_1610_GPIO48, M7_1610_GPIO62, V14_16XX_GPIO37, R9_16XX_GPIO18, L14_16XX_GPIO49, /* OMAP-1610 uWire */ V19_1610_UWIRE_SCLK, U18_1610_UWIRE_SDI, W21_1610_UWIRE_SDO, N14_1610_UWIRE_CS0, P15_1610_UWIRE_CS3, N15_1610_UWIRE_CS1, /* OMAP-1610 SPI */ U19_1610_SPIF_SCK, U18_1610_SPIF_DIN, P20_1610_SPIF_DIN, W21_1610_SPIF_DOUT, R18_1610_SPIF_DOUT, N14_1610_SPIF_CS0, N15_1610_SPIF_CS1, T19_1610_SPIF_CS2, P15_1610_SPIF_CS3, /* OMAP-1610 Flash */ L3_1610_FLASH_CS2B_OE, M8_1610_FLASH_CS2B_WE, /* First MMC */ MMC_CMD, MMC_DAT1, MMC_DAT2, MMC_DAT0, MMC_CLK, MMC_DAT3, /* OMAP-1710 MMC CMDDIR and DATDIR0 */ M15_1710_MMC_CLKI, P19_1710_MMC_CMDDIR, P20_1710_MMC_DATDIR0, /* OMAP-1610 USB0 alternate pin configuration */ W9_USB0_TXEN, AA9_USB0_VP, Y5_USB0_RCV, R9_USB0_VM, V6_USB0_TXD, W5_USB0_SE0, V9_USB0_SPEED, V9_USB0_SUSP, /* USB2 */ W9_USB2_TXEN, AA9_USB2_VP, Y5_USB2_RCV, R9_USB2_VM, V6_USB2_TXD, W5_USB2_SE0, /* 16XX UART */ R13_1610_UART1_TX, V14_16XX_UART1_RX, R14_1610_UART1_CTS, AA15_1610_UART1_RTS, R9_16XX_UART2_RX, L14_16XX_UART3_RX, /* I2C OMAP-1610 */ I2C_SCL, I2C_SDA, /* Keypad */ F18_1610_KBC0, D20_1610_KBC1, D19_1610_KBC2, E18_1610_KBC3, C21_1610_KBC4, G18_1610_KBR0, F19_1610_KBR1, H14_1610_KBR2, E20_1610_KBR3, E19_1610_KBR4, N19_1610_KBR5, /* Power management */ T20_1610_LOW_PWR, /* MCLK Settings */ V5_1710_MCLK_ON, V5_1710_MCLK_OFF, R10_1610_MCLK_ON, R10_1610_MCLK_OFF, /* CompactFlash controller */ P11_1610_CF_CD2, R11_1610_CF_IOIS16, V10_1610_CF_IREQ, W10_1610_CF_RESET, W11_1610_CF_CD1, /* parallel camera */ J15_1610_CAM_LCLK, J18_1610_CAM_D7, J19_1610_CAM_D6, J14_1610_CAM_D5, K18_1610_CAM_D4, K19_1610_CAM_D3, K15_1610_CAM_D2, K14_1610_CAM_D1, L19_1610_CAM_D0, L18_1610_CAM_VS, L15_1610_CAM_HS, M19_1610_CAM_RSTZ, Y15_1610_CAM_OUTCLK, /* serial camera */ H19_1610_CAM_EXCLK, Y12_1610_CCP_CLKP, W13_1610_CCP_CLKM, W14_1610_CCP_DATAP, Y14_1610_CCP_DATAM, }; struct omap_mux_cfg { struct pin_config *pins; unsigned long size; int (*cfg_reg)(const struct pin_config *cfg); }; #ifdef CONFIG_OMAP_MUX /* setup pin muxing in Linux */ extern int omap1_mux_init(void); extern int omap_mux_register(struct omap_mux_cfg *); extern int omap_cfg_reg(unsigned long reg_cfg); #else /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ static inline int omap1_mux_init(void) { return 0; } static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } #endif extern int omap2_mux_init(void); #endif PK ! �,�� � include/mach/io.hnu �[��� /* * arch/arm/mach-omap1/include/mach/io.h * * IO definitions for TI OMAP processors and boards * * Copied from arch/arm/mach-sa1100/include/mach/io.h * Copyright (C) 1997-1999 Russell King * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. * * Modifications: * 06-12-1997 RMK Created. * 07-04-1999 RMK Major cleanup */ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H #define IO_SPACE_LIMIT 0xffffffff /* * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ #define __io(a) __typesafe_io(a) #endif PK ! o�*^� � include/mach/tc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * arch/arm/plat-omap/include/mach/tc.h * * OMAP Traffic Controller * * Copyright (C) 2004 Nokia Corporation * Author: Imre Deak <imre.deak@nokia.com> */ #ifndef __ASM_ARCH_TC_H #define __ASM_ARCH_TC_H #define TCMIF_BASE 0xfffecc00 #define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00) #define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04) #define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08) #define EMIFS_CONFIG (TCMIF_BASE + 0x0c) #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) #define EMIFF_MRS (TCMIF_BASE + 0x24) #define TC_TIMEOUT1 (TCMIF_BASE + 0x28) #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) #define TC_TIMEOUT3 (TCMIF_BASE + 0x30) #define TC_ENDIANISM (TCMIF_BASE + 0x34) #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) #define EMIFS_ACS0 (TCMIF_BASE + 0x50) #define EMIFS_ACS1 (TCMIF_BASE + 0x54) #define EMIFS_ACS2 (TCMIF_BASE + 0x58) #define EMIFS_ACS3 (TCMIF_BASE + 0x5c) #define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0) /* external EMIFS chipselect regions */ #define OMAP_CS0_PHYS 0x00000000 #define OMAP_CS0_SIZE SZ_64M #define OMAP_CS1_PHYS 0x04000000 #define OMAP_CS1_SIZE SZ_64M #define OMAP_CS1A_PHYS OMAP_CS1_PHYS #define OMAP_CS1A_SIZE SZ_32M #define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE) #define OMAP_CS1B_SIZE SZ_32M #define OMAP_CS2_PHYS 0x08000000 #define OMAP_CS2_SIZE SZ_64M #define OMAP_CS2A_PHYS OMAP_CS2_PHYS #define OMAP_CS2A_SIZE SZ_32M #define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE) #define OMAP_CS2B_SIZE SZ_32M #define OMAP_CS3_PHYS 0x0c000000 #define OMAP_CS3_SIZE SZ_64M #ifndef __ASSEMBLER__ /* EMIF Slow Interface Configuration Register */ #define OMAP_EMIFS_CONFIG_FR (1 << 4) #define OMAP_EMIFS_CONFIG_PDE (1 << 3) #define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) #define OMAP_EMIFS_CONFIG_BM (1 << 1) #define OMAP_EMIFS_CONFIG_WP (1 << 0) #define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) #define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) #endif /* __ASSEMBLER__ */ #endif /* __ASM_ARCH_TC_H */ PK ! oV"H� � Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only if ARCH_OMAP1 menu "TI OMAP1 specific features" comment "OMAP Core Type" config ARCH_OMAP730 bool "OMAP730 Based System" select ARCH_OMAP_OTG select CPU_ARM926T select OMAP_MPU_TIMER config ARCH_OMAP850 bool "OMAP850 Based System" select ARCH_OMAP_OTG select CPU_ARM926T config ARCH_OMAP15XX default y bool "OMAP15xx Based System" select CPU_ARM925T select OMAP_MPU_TIMER config ARCH_OMAP16XX bool "OMAP16xx Based System" select ARCH_OMAP_OTG select CPU_ARM926T select OMAP_DM_TIMER config OMAP_MUX bool "OMAP multiplexing support" default y help Pin multiplexing support for OMAP boards. If your bootloader sets the multiplexing correctly, say N. Otherwise, or if unsure, say Y. config OMAP_MUX_DEBUG bool "Multiplexing debug output" depends on OMAP_MUX help Makes the multiplexing functions print out a lot of debug info. This is useful if you want to find out the correct values of the multiplexing registers. config OMAP_MUX_WARNINGS bool "Warn about pins the bootloader didn't set up" depends on OMAP_MUX default y help Choose Y here to warn whenever driver initialization logic needs to change the pin multiplexing setup. When there are no warnings printed, it's safe to deselect OMAP_MUX for your product. comment "OMAP Board Type" config MACH_OMAP_INNOVATOR bool "TI Innovator" depends on ARCH_OMAP15XX || ARCH_OMAP16XX help TI OMAP 1510 or 1610 Innovator board support. Say Y here if you have such a board. config MACH_OMAP_H2 bool "TI H2 Support" depends on ARCH_OMAP16XX help TI OMAP 1610/1611B H2 board support. Say Y here if you have such a board. config MACH_OMAP_H3 bool "TI H3 Support" depends on ARCH_OMAP16XX help TI OMAP 1710 H3 board support. Say Y here if you have such a board. config MACH_HERALD bool "HTC Herald" depends on ARCH_OMAP850 help HTC Herald smartphone support (AKA T-Mobile Wing, ...) config MACH_OMAP_OSK bool "TI OSK Support" depends on ARCH_OMAP16XX help TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here if you have such a board. config OMAP_OSK_MISTRAL bool "Mistral QVGA board Support" depends on MACH_OMAP_OSK help The OSK supports an optional add-on board with a Quarter-VGA touchscreen, PDA-ish buttons, a resume button, bicolor LED, and camera connector. Say Y here if you have this board. config MACH_OMAP_PERSEUS2 bool "TI Perseus2" depends on ARCH_OMAP730 help Support for TI OMAP 730 Perseus2 board. Say Y here if you have such a board. config MACH_OMAP_FSAMPLE bool "TI F-Sample" depends on ARCH_OMAP730 help Support for TI OMAP 850 F-Sample board. Say Y here if you have such a board. config MACH_OMAP_PALMTE bool "Palm Tungsten E" depends on ARCH_OMAP15XX help Support for the Palm Tungsten E PDA. To boot the kernel, you'll need a PalmOS compatible bootloader; check out http://palmtelinux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. config MACH_OMAP_PALMZ71 bool "Palm Zire71" depends on ARCH_OMAP15XX help Support for the Palm Zire71 PDA. To boot the kernel, you'll need a PalmOS compatible bootloader; check out http://hackndev.com/palm/z71 for more information. Say Y here if you have such a PDA, say N otherwise. config MACH_OMAP_PALMTT bool "Palm Tungsten|T" depends on ARCH_OMAP15XX help Support for the Palm Tungsten|T PDA. To boot the kernel, you'll need a PalmOS compatible bootloader (Garux); check out http://garux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. config MACH_SX1 bool "Siemens SX1" depends on ARCH_OMAP15XX select I2C help Support for the Siemens SX1 phone. To boot the kernel, you'll need a SX1 compatible bootloader; check out http://forum.oslik.ru and https://www.handhelds.org/moin/moin.cgi/SiemensSX1 for more information. Say Y here if you have such a phone, say NO otherwise. config MACH_NOKIA770 bool "Nokia 770" depends on ARCH_OMAP16XX help Support for the Nokia 770 Internet Tablet. Say Y here if you have such a device. config MACH_AMS_DELTA bool "Amstrad E3 (Delta)" depends on ARCH_OMAP15XX select FIQ select GPIO_GENERIC_PLATFORM select LEDS_GPIO_REGISTER select REGULATOR select REGULATOR_FIXED_VOLTAGE help Support for the Amstrad E3 (codename Delta) videophone. Say Y here if you have such a device. config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP15XX || ARCH_OMAP16XX help Support for generic OMAP-1510, 1610 or 1710 board with no FPGA. Can be used as template for porting Linux to custom OMAP boards. Say Y here if you have a custom board. endmenu endif PK ! X��` ` Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the linux kernel. # # Common support obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \ serial.o devices.o dma.o fb.o obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),) obj-y += mcbsp.o endif obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # OCPI interconnect support for 1710, 1610 and 5912 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o # Power Management obj-$(CONFIG_PM) += pm.o sleep.o i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) led-y := leds.o usb-fs-$(CONFIG_USB_SUPPORT) := usb.o obj-y += $(usb-fs-m) $(usb-fs-y) # Specific board support obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o \ board-nand.o obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o board-nand.o obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \ board-nand.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \ ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o obj-$(CONFIG_MACH_HERALD) += board-htcherald.o ifeq ($(CONFIG_ARCH_OMAP15XX),y) # Innovator-1510 FPGA obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o endif # GPIO obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o ifneq ($(CONFIG_FB_OMAP),) obj-y += lcd_dma.o endif PK ! �Y�- Makefile.bootnu �[��� # SPDX-License-Identifier: GPL-2.0-only zreladdr-y += 0x10008000 params_phys-y := 0x10000100 initrd_phys-y := 0x10800000 PK ! ���� � include/mach/lcd_dma.hnu �[��� PK ! �}� � A include/mach/uncompress.hnu �[��� PK ! �[��� � include/mach/omap7xx.hnu �[��� PK ! *M���# �# "' include/mach/irqs.hnu �[��� PK ! سR# # K include/mach/omap1510.hnu �[��� PK ! )ߢ�! �! ug include/mach/omap16xx.hnu �[��� PK ! �#�� � `� include/mach/lcdc.hnu �[��� PK ! ��R] ] v� include/mach/serial.hnu �[��� PK ! �� � � � include/mach/mtd-xip.hnu �[��� PK ! �w`, `, V� include/mach/hardware.hnu �[��� PK ! ��awT T �� include/mach/soc.hnu �[��� PK ! ��2 � � �� include/mach/memory.hnu �[��� PK ! }) � � �� include/mach/usb.hnu �[��� PK ! ,pܗ}! }! �� include/mach/mux.hnu �[��� PK ! �,�� � � include/mach/io.hnu �[��� PK ! o�*^� � � include/mach/tc.hnu �[��� PK ! oV"H� � � Kconfignu �[��� PK ! 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