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PK ! � _� � include/mach/uncompress.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/uncompress.h * * Copyright (C) 2002 Intel Corporation. * Copyright (C) 2003-2004 MontaVista Software, Inc. */ #ifndef _ARCH_UNCOMPRESS_H_ #define _ARCH_UNCOMPRESS_H_ #include "ixp4xx-regs.h" #include <asm/mach-types.h> #include <linux/serial_reg.h> #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) volatile u32* uart_base; static inline void putc(int c) { /* Check THRE and TEMT bits before we transmit the character. */ while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) barrier(); *uart_base = c; } static void flush(void) { } static __inline__ void __arch_decomp_setup(unsigned long arch_id) { /* * Some boards are using UART2 as console */ if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2() || machine_is_devixp() || machine_is_miccpt() || machine_is_mic256()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; } /* * arch_id is a variable in decompress_kernel() */ #define arch_decomp_setup() __arch_decomp_setup(arch_id) #endif PK ! �@��� � include/mach/hardware.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/hardware.h * * Copyright (C) 2002 Intel Corporation. * Copyright (C) 2003-2004 MontaVista Software, Inc. */ /* * Hardware definitions for IXP4xx based systems */ #ifndef __ASM_ARCH_HARDWARE_H__ #define __ASM_ARCH_HARDWARE_H__ #ifdef CONFIG_IXP4XX_INDIRECT_PCI #define PCIBIOS_MAX_MEM 0x4FFFFFFF #else #define PCIBIOS_MAX_MEM 0x4BFFFFFF #endif /* Register locations and bits */ #include "ixp4xx-regs.h" #ifndef __ASSEMBLER__ #include <linux/soc/ixp4xx/cpu.h> #endif /* Platform helper functions and definitions */ #include "platform.h" #endif /* _ASM_ARCH_HARDWARE_H */ PK ! ��>�'. '. include/mach/ixp4xx-regs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h * * Register definitions for IXP4xx chipset. This file contains * register location and bit definitions only. Platform specific * definitions and helper function declarations are in platform.h * and machine-name.h. * * Copyright (C) 2002 Intel Corporation. * Copyright (C) 2003-2004 MontaVista Software, Inc. */ #ifndef _ASM_ARM_IXP4XX_H_ #define _ASM_ARM_IXP4XX_H_ /* * IXP4xx Linux Memory Map: * * Phy Size Virt Description * ========================================================================= * * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM * * 0x48000000 0x04000000 ioremap'd PCI Memory Space * * 0x50000000 0x10000000 ioremap'd EXP BUS * * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals * * 0xC0000000 0x00001000 0xFEF13000 PCI CFG * * 0xC4000000 0x00001000 0xFEF14000 EXP CFG * * 0x60000000 0x00004000 0xFEF15000 QMgr */ /* * Queue Manager */ #define IXP4XX_QMGR_BASE_PHYS 0x60000000 /* * Peripheral space, including debug UART. Must be section-aligned so that * it can be used with the low-level debug code. */ #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000) #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 /* * PCI Config registers */ #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000) #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 /* * Expansion BUS Configuration registers */ #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 #define IXP4XX_EXP_CS0_OFFSET 0x00 #define IXP4XX_EXP_CS1_OFFSET 0x04 #define IXP4XX_EXP_CS2_OFFSET 0x08 #define IXP4XX_EXP_CS3_OFFSET 0x0C #define IXP4XX_EXP_CS4_OFFSET 0x10 #define IXP4XX_EXP_CS5_OFFSET 0x14 #define IXP4XX_EXP_CS6_OFFSET 0x18 #define IXP4XX_EXP_CS7_OFFSET 0x1C #define IXP4XX_EXP_CFG0_OFFSET 0x20 #define IXP4XX_EXP_CFG1_OFFSET 0x24 #define IXP4XX_EXP_CFG2_OFFSET 0x28 #define IXP4XX_EXP_CFG3_OFFSET 0x2C /* * Expansion Bus Controller registers. */ #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) /* * Peripheral Space Register Region Base Addresses */ #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) /* ixp46X only */ #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) /* The UART is explicitly put in the beginning of fixmap */ #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) /* ixp46X only */ #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) /* * Constants to make it easy to access Timer Control/Status registers */ #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ /* * Operating System Timer Register Definitions. */ #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) /* * Timer register values and bit definitions */ #define IXP4XX_OST_ENABLE 0x00000001 #define IXP4XX_OST_ONE_SHOT 0x00000002 /* Low order bits of reload value ignored */ #define IXP4XX_OST_RELOAD_MASK 0x00000003 #define IXP4XX_OST_DISABLED 0x00000000 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 #define IXP4XX_WDT_KEY 0x0000482E #define IXP4XX_WDT_RESET_ENABLE 0x00000001 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 /* * Constants to make it easy to access PCI Control/Status registers */ #define PCI_NP_AD_OFFSET 0x00 #define PCI_NP_CBE_OFFSET 0x04 #define PCI_NP_WDATA_OFFSET 0x08 #define PCI_NP_RDATA_OFFSET 0x0c #define PCI_CRP_AD_CBE_OFFSET 0x10 #define PCI_CRP_WDATA_OFFSET 0x14 #define PCI_CRP_RDATA_OFFSET 0x18 #define PCI_CSR_OFFSET 0x1c #define PCI_ISR_OFFSET 0x20 #define PCI_INTEN_OFFSET 0x24 #define PCI_DMACTRL_OFFSET 0x28 #define PCI_AHBMEMBASE_OFFSET 0x2c #define PCI_AHBIOBASE_OFFSET 0x30 #define PCI_PCIMEMBASE_OFFSET 0x34 #define PCI_AHBDOORBELL_OFFSET 0x38 #define PCI_PCIDOORBELL_OFFSET 0x3C #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 /* * PCI Control/Status Registers */ #define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) #define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) #define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) #define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) #define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) #define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) #define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) #define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) #define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) #define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET) #define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) #define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) #define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) #define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) #define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) #define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) #define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) #define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) #define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) #define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) #define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) #define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) #define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) /* * PCI register values and bit definitions */ /* CSR bit definitions */ #define PCI_CSR_HOST 0x00000001 #define PCI_CSR_ARBEN 0x00000002 #define PCI_CSR_ADS 0x00000004 #define PCI_CSR_PDS 0x00000008 #define PCI_CSR_ABE 0x00000010 #define PCI_CSR_DBT 0x00000020 #define PCI_CSR_ASE 0x00000100 #define PCI_CSR_IC 0x00008000 /* ISR (Interrupt status) Register bit definitions */ #define PCI_ISR_PSE 0x00000001 #define PCI_ISR_PFE 0x00000002 #define PCI_ISR_PPE 0x00000004 #define PCI_ISR_AHBE 0x00000008 #define PCI_ISR_APDC 0x00000010 #define PCI_ISR_PADC 0x00000020 #define PCI_ISR_ADB 0x00000040 #define PCI_ISR_PDB 0x00000080 /* INTEN (Interrupt Enable) Register bit definitions */ #define PCI_INTEN_PSE 0x00000001 #define PCI_INTEN_PFE 0x00000002 #define PCI_INTEN_PPE 0x00000004 #define PCI_INTEN_AHBE 0x00000008 #define PCI_INTEN_APDC 0x00000010 #define PCI_INTEN_PADC 0x00000020 #define PCI_INTEN_ADB 0x00000040 #define PCI_INTEN_PDB 0x00000080 /* * Shift value for byte enable on NP cmd/byte enable register */ #define IXP4XX_PCI_NP_CBE_BESL 4 /* * PCI commands supported by NP access unit */ #define NP_CMD_IOREAD 0x2 #define NP_CMD_IOWRITE 0x3 #define NP_CMD_CONFIGREAD 0xa #define NP_CMD_CONFIGWRITE 0xb #define NP_CMD_MEMREAD 0x6 #define NP_CMD_MEMWRITE 0x7 /* * Constants for CRP access into local config space */ #define CRP_AD_CBE_BESL 20 #define CRP_AD_CBE_WRITE 0x00010000 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ #endif PK ! k�:� � include/mach/udc.hnu �[��� /* * arch/arm/mach-ixp4xx/include/mach/udc.h * */ #include <linux/platform_data/pxa2xx_udc.h> extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); PK ! �^~6W5 W5 include/mach/io.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-ixp4xx/include/mach/io.h * * Author: Deepak Saxena <dsaxena@plexity.net> * * Copyright (C) 2002-2005 MontaVista Software, Inc. */ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H #include <linux/bitops.h> #include <mach/hardware.h> extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); /* * IXP4xx provides two methods of accessing PCI memory space: * * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). * To access PCI via this space, we simply ioremap() the BAR * into the kernel and we can use the standard read[bwl]/write[bwl] * macros. This is the preffered method due to speed but it * limits the system to just 64MB of PCI memory. This can be * problematic if using video cards and other memory-heavy targets. * * 2) If > 64MB of memory space is required, the IXP4xx can use indirect * registers to access the whole 4 GB of PCI memory space (as we do below * for I/O transactions). This allows currently for up to 1 GB (0x10000000 * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that * every PCI access requires three local register accesses plus a spinlock, * but in some cases the performance hit is acceptable. In addition, you * cannot mmap() PCI devices in this case. */ #ifdef CONFIG_IXP4XX_INDIRECT_PCI /* * In the case of using indirect PCI, we simply return the actual PCI * address and our read/write implementation use that to drive the * access registers. If something outside of PCI is ioremap'd, we * fallback to the default. */ extern unsigned long pcibios_min_mem; static inline int is_pci_memory(u32 addr) { return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF); } #define writeb(v, p) __indirect_writeb(v, p) #define writew(v, p) __indirect_writew(v, p) #define writel(v, p) __indirect_writel(v, p) #define writeb_relaxed(v, p) __indirect_writeb(v, p) #define writew_relaxed(v, p) __indirect_writew(v, p) #define writel_relaxed(v, p) __indirect_writel(v, p) #define writesb(p, v, l) __indirect_writesb(p, v, l) #define writesw(p, v, l) __indirect_writesw(p, v, l) #define writesl(p, v, l) __indirect_writesl(p, v, l) #define readb(p) __indirect_readb(p) #define readw(p) __indirect_readw(p) #define readl(p) __indirect_readl(p) #define readb_relaxed(p) __indirect_readb(p) #define readw_relaxed(p) __indirect_readw(p) #define readl_relaxed(p) __indirect_readl(p) #define readsb(p, v, l) __indirect_readsb(p, v, l) #define readsw(p, v, l) __indirect_readsw(p, v, l) #define readsl(p, v, l) __indirect_readsl(p, v, l) static inline void __indirect_writeb(u8 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) { __raw_writeb(value, p); return; } n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } static inline void __indirect_writesb(volatile void __iomem *bus_addr, const void *p, int count) { const u8 *vaddr = p; while (count--) writeb(*vaddr++, bus_addr); } static inline void __indirect_writew(u16 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) { __raw_writew(value, p); return; } n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } static inline void __indirect_writesw(volatile void __iomem *bus_addr, const void *p, int count) { const u16 *vaddr = p; while (count--) writew(*vaddr++, bus_addr); } static inline void __indirect_writel(u32 value, volatile void __iomem *p) { u32 addr = (__force u32)p; if (!is_pci_memory(addr)) { __raw_writel(value, p); return; } ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); } static inline void __indirect_writesl(volatile void __iomem *bus_addr, const void *p, int count) { const u32 *vaddr = p; while (count--) writel(*vaddr++, bus_addr); } static inline u8 __indirect_readb(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) return __raw_readb(p); n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) return 0xff; return data >> (8*n); } static inline void __indirect_readsb(const volatile void __iomem *bus_addr, void *p, u32 count) { u8 *vaddr = p; while (count--) *vaddr++ = readb(bus_addr); } static inline u16 __indirect_readw(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (!is_pci_memory(addr)) return __raw_readw(p); n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) return 0xffff; return data>>(8*n); } static inline void __indirect_readsw(const volatile void __iomem *bus_addr, void *p, u32 count) { u16 *vaddr = p; while (count--) *vaddr++ = readw(bus_addr); } static inline u32 __indirect_readl(const volatile void __iomem *p) { u32 addr = (__force u32)p; u32 data; if (!is_pci_memory(addr)) return __raw_readl(p); if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) return 0xffffffff; return data; } static inline void __indirect_readsl(const volatile void __iomem *bus_addr, void *p, u32 count) { u32 *vaddr = p; while (count--) *vaddr++ = readl(bus_addr); } /* * We can use the built-in functions b/c they end up calling writeb/readb */ #define memset_io(c,v,l) _memset_io((c),(v),(l)) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) #endif /* CONFIG_IXP4XX_INDIRECT_PCI */ #ifndef CONFIG_PCI #define __io(v) __typesafe_io(v) #else /* * IXP4xx does not have a transparent cpu -> PCI I/O translation * window. Instead, it has a set of registers that must be tweaked * with the proper byte lanes, command types, and address for the * transaction. This means that we need to override the default * I/O functions. */ #define outb outb static inline void outb(u8 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } #define outsb outsb static inline void outsb(u32 io_addr, const void *p, u32 count) { const u8 *vaddr = p; while (count--) outb(*vaddr++, io_addr); } #define outw outw static inline void outw(u16 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } #define outsw outsw static inline void outsw(u32 io_addr, const void *p, u32 count) { const u16 *vaddr = p; while (count--) outw(cpu_to_le16(*vaddr++), io_addr); } #define outl outl static inline void outl(u32 value, u32 addr) { ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); } #define outsl outsl static inline void outsl(u32 io_addr, const void *p, u32 count) { const u32 *vaddr = p; while (count--) outl(cpu_to_le32(*vaddr++), io_addr); } #define inb inb static inline u8 inb(u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) return 0xff; return data >> (8*n); } #define insb insb static inline void insb(u32 io_addr, void *p, u32 count) { u8 *vaddr = p; while (count--) *vaddr++ = inb(io_addr); } #define inw inw static inline u16 inw(u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) return 0xffff; return data>>(8*n); } #define insw insw static inline void insw(u32 io_addr, void *p, u32 count) { u16 *vaddr = p; while (count--) *vaddr++ = le16_to_cpu(inw(io_addr)); } #define inl inl static inline u32 inl(u32 addr) { u32 data; if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) return 0xffffffff; return data; } #define insl insl static inline void insl(u32 io_addr, void *p, u32 count) { u32 *vaddr = p; while (count--) *vaddr++ = le32_to_cpu(inl(io_addr)); } #define PIO_OFFSET 0x10000UL #define PIO_MASK 0x0ffffUL #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) #define ioread8(p) ioread8(p) static inline u8 ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(addr); #else return (unsigned int)__indirect_readb(addr); #endif } #define ioread8_rep(p, v, c) ioread8_rep(p, v, c) static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) insb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); #else __indirect_readsb(addr, vaddr, count); #endif } #define ioread16(p) ioread16(p) static inline u16 ioread16(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)inw(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu((__force __le16)__raw_readw(addr)); #else return (unsigned int)__indirect_readw(addr); #endif } #define ioread16_rep(p, v, c) ioread16_rep(p, v, c) static inline void ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) insw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); #else __indirect_readsw(addr, vaddr, count); #endif } #define ioread32(p) ioread32(p) static inline u32 ioread32(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)inl(port & PIO_MASK); else { #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu((__force __le32)__raw_readl(addr)); #else return (unsigned int)__indirect_readl(addr); #endif } } #define ioread32_rep(p, v, c) ioread32_rep(p, v, c) static inline void ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) insl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); #else __indirect_readsl(addr, vaddr, count); #endif } #define iowrite8(v, p) iowrite8(v, p) static inline void iowrite8(u8 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outb(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, addr); #else __indirect_writeb(value, addr); #endif } #define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outsb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); #else __indirect_writesb(addr, vaddr, count); #endif } #define iowrite16(v, p) iowrite16(v, p) static inline void iowrite16(u16 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outw(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); #else __indirect_writew(value, addr); #endif } #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outsw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); #else __indirect_writesw(addr, vaddr, count); #endif } #define iowrite32(v, p) iowrite32(v, p) static inline void iowrite32(u32 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outl(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel((u32 __force)cpu_to_le32(value), addr); #else __indirect_writel(value, addr); #endif } #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) outsl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); #else __indirect_writesl(addr, vaddr, count); #endif } #define ioport_map(port, nr) ioport_map(port, nr) static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) { return ((void __iomem*)((port) + PIO_OFFSET)); } #define ioport_unmap(addr) ioport_unmap(addr) static inline void ioport_unmap(void __iomem *addr) { } #endif /* CONFIG_PCI */ #endif /* __ASM_ARM_ARCH_IO_H */ PK ! �=8-� � include/mach/platform.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * arch/arm/mach-ixp4xx/include/mach/platform.h * * Constants and functions that are useful to IXP4xx platform-specific code * and device drivers. * * Copyright (C) 2004 MontaVista Software, Inc. */ #ifndef __ASM_ARCH_HARDWARE_H__ #error "Do not include this directly, instead #include <mach/hardware.h>" #endif #ifndef __ASSEMBLY__ #include <linux/reboot.h> #include <linux/platform_data/eth_ixp4xx.h> #include <asm/types.h> #ifndef __ARMEB__ #define REG_OFFSET 0 #else #define REG_OFFSET 3 #endif /* * Expansion bus memory regions */ #define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000) /* * The expansion bus on the IXP4xx can be configured for either 16 or * 32MB windows and the CS offset for each region changes based on the * current configuration. This means that we cannot simply hardcode * each offset. ixp4xx_sys_init() looks at the expansion bus configuration * as setup by the bootloader to determine our window size. */ extern unsigned long ixp4xx_exp_bus_size; #define IXP4XX_EXP_BUS_BASE(region)\ (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size)) #define IXP4XX_EXP_BUS_END(region)\ (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1) /* Those macros can be used to adjust timing and configure * other features for each region. */ #define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16) #define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20) #define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22) #define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26) #define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28) #define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10) #define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14) #define IXP4XX_EXP_BUS_CS_EN (1L << 31) #define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6) #define IXP4XX_EXP_BUS_HRDY_POL (1L << 5) #define IXP4XX_EXP_BUS_MUX_EN (1L << 4) #define IXP4XX_EXP_BUS_SPLT_EN (1L << 3) #define IXP4XX_EXP_BUS_WR_EN (1L << 1) #define IXP4XX_EXP_BUS_BYTE_EN (1L << 0) #define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00 #define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01 #define IXP4XX_EXP_BUS_CYCLES_HPI 0x02 #define IXP4XX_FLASH_WRITABLE (0x2) #define IXP4XX_FLASH_DEFAULT (0xbcd23c40) #define IXP4XX_FLASH_WRITE (0xbcd23c42) /* * Clock Speed Definitions. */ #define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */ #define IXP4XX_UART_XTAL 14745600 /* * Frequency of clock used for primary clocksource */ extern unsigned long ixp4xx_timer_freq; /* * Functions used by platform-level setup code */ extern void ixp4xx_map_io(void); extern void ixp4xx_init_early(void); extern void ixp4xx_init_irq(void); extern void ixp4xx_sys_init(void); extern void ixp4xx_timer_init(void); extern void ixp4xx_restart(enum reboot_mode, const char *); extern void ixp4xx_pci_preinit(void); struct pci_sys_data; extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); extern struct pci_ops ixp4xx_ops; #endif // __ASSEMBLY__ PK ! 5�B� � Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only if ARCH_IXP4XX menu "Intel IXP4xx Implementation Options" comment "IXP4xx Platforms" config MACH_IXP4XX_OF bool prompt "Device Tree IXP4xx boards" default y select ARM_APPENDED_DTB # Old Redboot bootloaders deployed select I2C select I2C_IOP3XX select PCI select USE_OF help Say 'Y' here to support Device Tree-based IXP4xx platforms. config MACH_GATEWAY7001 bool "Gateway 7001" depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Gateway's 7001 Access Point. For more information on this platform, see http://openwrt.org config MACH_GORAMO_MLR bool "GORAMO Multi Link Router" depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support GORAMO MultiLink router. config ARCH_PRPMC1100 bool "PrPMC1100" help Say 'Y' here if you want your kernel to support the Motorola PrPCM1100 Processor Mezanine Module. For more information on this platform, see <file:Documentation/arm/ixp4xx.rst>. # # Certain registers and IRQs are only enabled if supporting IXP465 CPUs # config CPU_IXP46X bool depends on MACH_IXDP465 default y config CPU_IXP43X bool depends on MACH_KIXRP435 default y comment "IXP4xx Options" config IXP4XX_PCI_LEGACY bool "IXP4xx legacy PCI driver support" depends on PCI help Selects legacy PCI driver. Not recommended for new development. config IXP4XX_INDIRECT_PCI bool "Use indirect PCI memory access" depends on IXP4XX_PCI_LEGACY help IXP4xx provides two methods of accessing PCI memory space: 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). To access PCI via this space, we simply ioremap() the BAR into the kernel and we can use the standard read[bwl]/write[bwl] macros. This is the preferred method due to speed but it limits the system to just 64MB of PCI memory. This can be problematic if using video cards and other memory-heavy devices. 2) If > 64MB of memory space is required, the IXP4xx can be configured to use indirect registers to access the whole PCI memory space. This currently allows for up to 1 GB (0x10000000 to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that every PCI access requires three local register accesses plus a spinlock, but in some cases the performance hit is acceptable. In addition, you cannot mmap() PCI devices in this case due to the indirect nature of the PCI window. By default, the direct method is used. Choose this option if you need to use the indirect method instead. If you don't know what you need, leave this option unselected. endmenu endif PK ! ��L�� � Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the linux kernel. # obj-pci-y := obj-pci-n := # Device tree platform obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o obj-y += common.o obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o PK ! M�ba a Makefile.bootnu �[��� # SPDX-License-Identifier: GPL-2.0-only zreladdr-y += 0x00008000 params_phys-y := 0x00000100 PK ! � _� � include/mach/uncompress.hnu �[��� PK ! �@��� � � include/mach/hardware.hnu �[��� PK ! ��>�'. '. � include/mach/ixp4xx-regs.hnu �[��� PK ! k�:� � 46 include/mach/udc.hnu �[��� PK ! �^~6W5 W5 7 include/mach/io.hnu �[��� PK ! �=8-� � �l include/mach/platform.hnu �[��� PK ! 5�B� � �x Kconfignu �[��� PK ! ��L�� � �� Makefilenu �[��� PK ! M�ba a R� Makefile.bootnu �[��� PK � �
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