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PK ! �@0� � iidc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (C) 2021, Intel Corporation. */ #ifndef _IIDC_H_ #define _IIDC_H_ #include <linux/auxiliary_bus.h> #include <linux/dcbnl.h> #include <linux/device.h> #include <linux/if_ether.h> #include <linux/kernel.h> #include <linux/netdevice.h> enum iidc_event_type { IIDC_EVENT_BEFORE_MTU_CHANGE, IIDC_EVENT_AFTER_MTU_CHANGE, IIDC_EVENT_BEFORE_TC_CHANGE, IIDC_EVENT_AFTER_TC_CHANGE, IIDC_EVENT_CRIT_ERR, IIDC_EVENT_NBITS /* must be last */ }; enum iidc_reset_type { IIDC_PFR, IIDC_CORER, IIDC_GLOBR, }; #define IIDC_MAX_USER_PRIORITY 8 /* Struct to hold per RDMA Qset info */ struct iidc_rdma_qset_params { /* Qset TEID returned to the RDMA driver in * ice_add_rdma_qset and used by RDMA driver * for calls to ice_del_rdma_qset */ u32 teid; /* Qset TEID */ u16 qs_handle; /* RDMA driver provides this */ u16 vport_id; /* VSI index */ u8 tc; /* TC branch the Qset should belong to */ }; struct iidc_qos_info { u64 tc_ctx; u8 rel_bw; u8 prio_type; u8 egress_virt_up; u8 ingress_virt_up; }; /* Struct to pass QoS info */ struct iidc_qos_params { struct iidc_qos_info tc_info[IEEE_8021QAZ_MAX_TCS]; u8 up2tc[IIDC_MAX_USER_PRIORITY]; u8 vport_relative_bw; u8 vport_priority_type; u8 num_tc; }; struct iidc_event { DECLARE_BITMAP(type, IIDC_EVENT_NBITS); u32 reg; }; struct ice_pf; int ice_add_rdma_qset(struct ice_pf *pf, struct iidc_rdma_qset_params *qset); int ice_del_rdma_qset(struct ice_pf *pf, struct iidc_rdma_qset_params *qset); int ice_rdma_request_reset(struct ice_pf *pf, enum iidc_reset_type reset_type); int ice_rdma_update_vsi_filter(struct ice_pf *pf, u16 vsi_id, bool enable); void ice_get_qos_params(struct ice_pf *pf, struct iidc_qos_params *qos); #define IIDC_RDMA_ROCE_NAME "roce" /* Structure representing auxiliary driver tailored information about the core * PCI dev, each auxiliary driver using the IIDC interface will have an * instance of this struct dedicated to it. */ struct iidc_auxiliary_dev { struct auxiliary_device adev; struct ice_pf *pf; }; /* structure representing the auxiliary driver. This struct is to be * allocated and populated by the auxiliary driver's owner. The core PCI * driver will access these ops by performing a container_of on the * auxiliary_device->dev.driver. */ struct iidc_auxiliary_drv { struct auxiliary_driver adrv; /* This event_handler is meant to be a blocking call. For instance, * when a BEFORE_MTU_CHANGE event comes in, the event_handler will not * return until the auxiliary driver is ready for the MTU change to * happen. */ void (*event_handler)(struct ice_pf *pf, struct iidc_event *event); }; #endif /* _IIDC_H_*/ PK ! q�#� i40e_client.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2013 - 2018 Intel Corporation. */ #ifndef _I40E_CLIENT_H_ #define _I40E_CLIENT_H_ #include <linux/auxiliary_bus.h> #define I40E_CLIENT_STR_LENGTH 10 /* Client interface version should be updated anytime there is a change in the * existing APIs or data structures. */ #define I40E_CLIENT_VERSION_MAJOR 0 #define I40E_CLIENT_VERSION_MINOR 01 #define I40E_CLIENT_VERSION_BUILD 00 #define I40E_CLIENT_VERSION_STR \ __stringify(I40E_CLIENT_VERSION_MAJOR) "." \ __stringify(I40E_CLIENT_VERSION_MINOR) "." \ __stringify(I40E_CLIENT_VERSION_BUILD) struct i40e_client_version { u8 major; u8 minor; u8 build; u8 rsvd; }; enum i40e_client_state { __I40E_CLIENT_NULL, __I40E_CLIENT_REGISTERED }; enum i40e_client_instance_state { __I40E_CLIENT_INSTANCE_NONE, __I40E_CLIENT_INSTANCE_OPENED, }; struct i40e_ops; struct i40e_client; #define I40E_QUEUE_INVALID_IDX 0xFFFF struct i40e_qv_info { u32 v_idx; /* msix_vector */ u16 ceq_idx; u16 aeq_idx; u8 itr_idx; }; struct i40e_qvlist_info { u32 num_vectors; struct i40e_qv_info qv_info[]; }; /* set of LAN parameters useful for clients managed by LAN */ /* Struct to hold per priority info */ struct i40e_prio_qos_params { u16 qs_handle; /* qs handle for prio */ u8 tc; /* TC mapped to prio */ u8 reserved; }; #define I40E_CLIENT_MAX_USER_PRIORITY 8 /* Struct to hold Client QoS */ struct i40e_qos_params { struct i40e_prio_qos_params prio_qos[I40E_CLIENT_MAX_USER_PRIORITY]; }; struct i40e_params { struct i40e_qos_params qos; u16 mtu; }; /* Structure to hold Lan device info for a client device */ struct i40e_info { struct i40e_client_version version; u8 lanmac[6]; struct net_device *netdev; struct pci_dev *pcidev; struct auxiliary_device *aux_dev; u8 __iomem *hw_addr; u8 fid; /* function id, PF id or VF id */ #define I40E_CLIENT_FTYPE_PF 0 u8 ftype; /* function type, PF or VF */ void *pf; /* All L2 params that could change during the life span of the PF * and needs to be communicated to the client when they change */ struct i40e_qvlist_info *qvlist_info; struct i40e_params params; struct i40e_ops *ops; u16 msix_count; /* number of msix vectors*/ /* Array down below will be dynamically allocated based on msix_count */ struct msix_entry *msix_entries; u16 itr_index; /* Which ITR index the PE driver is suppose to use */ u16 fw_maj_ver; /* firmware major version */ u16 fw_min_ver; /* firmware minor version */ u32 fw_build; /* firmware build number */ }; struct i40e_auxiliary_device { struct auxiliary_device aux_dev; struct i40e_info *ldev; }; #define I40E_CLIENT_RESET_LEVEL_PF 1 #define I40E_CLIENT_RESET_LEVEL_CORE 2 #define I40E_CLIENT_VSI_FLAG_TCP_ENABLE BIT(1) struct i40e_ops { /* setup_q_vector_list enables queues with a particular vector */ int (*setup_qvlist)(struct i40e_info *ldev, struct i40e_client *client, struct i40e_qvlist_info *qv_info); int (*virtchnl_send)(struct i40e_info *ldev, struct i40e_client *client, u32 vf_id, u8 *msg, u16 len); /* If the PE Engine is unresponsive, RDMA driver can request a reset. * The level helps determine the level of reset being requested. */ void (*request_reset)(struct i40e_info *ldev, struct i40e_client *client, u32 level); /* API for the RDMA driver to set certain VSI flags that control * PE Engine. */ int (*update_vsi_ctxt)(struct i40e_info *ldev, struct i40e_client *client, bool is_vf, u32 vf_id, u32 flag, u32 valid_flag); }; struct i40e_client_ops { /* Should be called from register_client() or whenever PF is ready * to create a specific client instance. */ int (*open)(struct i40e_info *ldev, struct i40e_client *client); /* Should be called when netdev is unavailable or when unregister * call comes in. If the close is happenening due to a reset being * triggered set the reset bit to true. */ void (*close)(struct i40e_info *ldev, struct i40e_client *client, bool reset); /* called when some l2 managed parameters changes - mtu */ void (*l2_param_change)(struct i40e_info *ldev, struct i40e_client *client, struct i40e_params *params); int (*virtchnl_receive)(struct i40e_info *ldev, struct i40e_client *client, u32 vf_id, u8 *msg, u16 len); /* called when a VF is reset by the PF */ void (*vf_reset)(struct i40e_info *ldev, struct i40e_client *client, u32 vf_id); /* called when the number of VFs changes */ void (*vf_enable)(struct i40e_info *ldev, struct i40e_client *client, u32 num_vfs); /* returns true if VF is capable of specified offload */ int (*vf_capable)(struct i40e_info *ldev, struct i40e_client *client, u32 vf_id); }; /* Client device */ struct i40e_client_instance { struct list_head list; struct i40e_info lan_info; struct i40e_client *client; unsigned long state; }; struct i40e_client { struct list_head list; /* list of registered clients */ char name[I40E_CLIENT_STR_LENGTH]; struct i40e_client_version version; unsigned long state; /* client state */ atomic_t ref_cnt; /* Count of all the client devices of this kind */ u32 flags; u8 type; #define I40E_CLIENT_IWARP 0 const struct i40e_client_ops *ops; /* client ops provided by the client */ }; static inline bool i40e_client_is_registered(struct i40e_client *client) { return test_bit(__I40E_CLIENT_REGISTERED, &client->state); } void i40e_client_device_register(struct i40e_info *ldev, struct i40e_client *client); void i40e_client_device_unregister(struct i40e_info *ldev); #endif /* _I40E_CLIENT_H_ */ PK ! ��� � Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the Intel network device drivers. # obj-$(CONFIG_E100) += e100.o obj-$(CONFIG_E1000) += e1000/ obj-$(CONFIG_E1000E) += e1000e/ obj-$(CONFIG_IGB) += igb/ obj-$(CONFIG_IGC) += igc/ obj-$(CONFIG_IGBVF) += igbvf/ obj-$(CONFIG_IXGBE) += ixgbe/ obj-$(CONFIG_IXGBEVF) += ixgbevf/ obj-$(CONFIG_I40E) += i40e/ obj-$(CONFIG_IXGB) += ixgb/ obj-$(CONFIG_IAVF) += iavf/ obj-$(CONFIG_FM10K) += fm10k/ obj-$(CONFIG_ICE) += ice/ PK ! dO�{- {- stratix10-smc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation */ #ifndef __STRATIX10_SMC_H #define __STRATIX10_SMC_H #include <linux/arm-smccc.h> #include <linux/bitops.h> /** * This file defines the Secure Monitor Call (SMC) message protocol used for * service layer driver in normal world (EL1) to communicate with secure * monitor software in Secure Monitor Exception Level 3 (EL3). * * This file is shared with secure firmware (FW) which is out of kernel tree. * * An ARM SMC instruction takes a function identifier and up to 6 64-bit * register values as arguments, and can return up to 4 64-bit register * value. The operation of the secure monitor is determined by the parameter * values passed in through registers. * * EL1 and EL3 communicates pointer as physical address rather than the * virtual address. * * Functions specified by ARM SMC Calling convention: * * FAST call executes atomic operations, returns when the requested operation * has completed. * STD call starts a operation which can be preempted by a non-secure * interrupt. The call can return before the requested operation has * completed. * * a0..a7 is used as register names in the descriptions below, on arm32 * that translates to r0..r7 and on arm64 to w0..w7. */ /** * @func_num: function ID */ #define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ ARM_SMCCC_OWNER_SIP, (func_num)) #define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ ARM_SMCCC_OWNER_SIP, (func_num)) /** * Return values in INTEL_SIP_SMC_* call * * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: * Secure monitor software doesn't recognize the request. * * INTEL_SIP_SMC_STATUS_OK: * Secure monitor software accepts the service client's request. * * INTEL_SIP_SMC_STATUS_BUSY: * Secure monitor software is still processing service client's request. * * INTEL_SIP_SMC_STATUS_REJECTED: * Secure monitor software reject the service client's request. * * INTEL_SIP_SMC_STATUS_ERROR: * There is error during the process of service request. * * INTEL_SIP_SMC_RSU_ERROR: * There is error during the process of remote status update request. */ #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF #define INTEL_SIP_SMC_STATUS_OK 0x0 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 #define INTEL_SIP_SMC_RSU_ERROR 0x7 /** * Request INTEL_SIP_SMC_FPGA_CONFIG_START * * Sync call used by service driver at EL1 to request the FPGA in EL3 to * be prepare to receive a new configuration. * * Call register usage: * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. * a1: flag for full or partial configuration. 0 for full and 1 for partial * configuration. * a2-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 #define INTEL_SIP_SMC_FPGA_CONFIG_START \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) /** * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE * * Async call used by service driver at EL1 to provide FPGA configuration data * to secure world. * * Call register usage: * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. * a1: 64bit physical address of the configuration data memory block * a2: Size of configuration data block. * a3-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or * INTEL_SIP_SMC_STATUS_ERROR. * a1: 64bit physical address of 1st completed memory block if any completed * block, otherwise zero value. * a2: 64bit physical address of 2nd completed memory block if any completed * block, otherwise zero value. * a3: 64bit physical address of 3rd completed memory block if any completed * block, otherwise zero value. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \ INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE) /** * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE * * Sync call used by service driver at EL1 to track the completed write * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE * call returns INTEL_SIP_SMC_STATUS_BUSY. * * Call register usage: * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. * a1-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_BUSY or * INTEL_SIP_SMC_STATUS_ERROR. * a1: 64bit physical address of 1st completed memory block. * a2: 64bit physical address of 2nd completed memory block if * any completed block, otherwise zero value. * a3: 64bit physical address of 3rd completed memory block if * any completed block, otherwise zero value. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) /** * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE * * Sync call used by service driver at EL1 to inform secure world that all * data are sent, to check whether or not the secure world had completed * the FPGA configuration process. * * Call register usage: * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE. * a1-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or * INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE) /** * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM * * Sync call used by service driver at EL1 to query the physical address of * memory block reserved by secure monitor software. * * Call register usage: * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM. * a1-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. * a1: start of physical address of reserved memory block. * a2: size of reserved memory block. * a3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM) /** * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK * * For SMC loop-back mode only, used for internal integration, debugging * or troubleshooting. * * Call register usage: * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK. * a1-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 #define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK) /** * Request INTEL_SIP_SMC_REG_READ * * Read a protected register at EL3 * * Call register usage: * a0: INTEL_SIP_SMC_REG_READ. * a1: register address. * a2-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. * a1: value in the register * a2-3: not used. */ #define INTEL_SIP_SMC_FUNCID_REG_READ 7 #define INTEL_SIP_SMC_REG_READ \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) /** * Request INTEL_SIP_SMC_REG_WRITE * * Write a protected register at EL3 * * Call register usage: * a0: INTEL_SIP_SMC_REG_WRITE. * a1: register address * a2: value to program into register. * a3-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 #define INTEL_SIP_SMC_REG_WRITE \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) /** * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE * * Update one or more bits in a protected register at EL3 using a * read-modify-write operation. * * Call register usage: * a0: INTEL_SIP_SMC_REG_UPDATE. * a1: register address * a2: write Mask. * a3: value to write. * a4-7: not used. * * Return status: * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. * a1-3: Not used. */ #define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9 #define INTEL_SIP_SMC_REG_UPDATE \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE) /** * Request INTEL_SIP_SMC_RSU_STATUS * * Request remote status update boot log, call is synchronous. * * Call register usage: * a0 INTEL_SIP_SMC_RSU_STATUS * a1-7 not used * * Return status * a0: Current Image * a1: Last Failing Image * a2: Version | State * a3: Error details | Error location * * Or * * a0: INTEL_SIP_SMC_RSU_ERROR */ #define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11 #define INTEL_SIP_SMC_RSU_STATUS \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS) /** * Request INTEL_SIP_SMC_RSU_UPDATE * * Request to set the offset of the bitstream to boot after reboot, call * is synchronous. * * Call register usage: * a0 INTEL_SIP_SMC_RSU_UPDATE * a1 64bit physical address of the configuration data memory in flash * a2-7 not used * * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ #define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12 #define INTEL_SIP_SMC_RSU_UPDATE \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE) /** * Request INTEL_SIP_SMC_ECC_DBE * * Sync call used by service driver at EL1 to alert EL3 that a Double * Bit ECC error has occurred. * * Call register usage: * a0 INTEL_SIP_SMC_ECC_DBE * a1 SysManager Double Bit Error value * a2-7 not used * * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ #define INTEL_SIP_SMC_FUNCID_ECC_DBE 13 #define INTEL_SIP_SMC_ECC_DBE \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE) #endif /** * Request INTEL_SIP_SMC_RSU_NOTIFY * * Sync call used by service driver at EL1 to report hard processor * system execution stage to firmware * * Call register usage: * a0 INTEL_SIP_SMC_RSU_NOTIFY * a1 32bit value representing hard processor system execution stage * a2-7 not used * * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ #define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14 #define INTEL_SIP_SMC_RSU_NOTIFY \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY) /** * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER * * Sync call used by service driver at EL1 to query RSU retry counter * * Call register usage: * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER * a1-7 not used * * Return status * a0 INTEL_SIP_SMC_STATUS_OK * a1 the retry counter * * Or * * a0 INTEL_SIP_SMC_RSU_ERROR */ #define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER) /** * Request INTEL_SIP_SMC_RSU_DCMF_VERSION * * Sync call used by service driver at EL1 to query DCMF (Decision * Configuration Management Firmware) version from FW * * Call register usage: * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION * a1-7 not used * * Return status * a0 INTEL_SIP_SMC_STATUS_OK * a1 dcmf1 | dcmf0 * a2 dcmf3 | dcmf2 * * Or * * a0 INTEL_SIP_SMC_RSU_ERROR */ #define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16 #define INTEL_SIP_SMC_RSU_DCMF_VERSION \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION) /** * Request INTEL_SIP_SMC_RSU_MAX_RETRY * * Sync call used by service driver at EL1 to query max retry value from FW * * Call register usage: * a0 INTEL_SIP_SMC_RSU_MAX_RETRY * a1-7 not used * * Return status * a0 INTEL_SIP_SMC_STATUS_OK * a1 max retry value * * Or * a0 INTEL_SIP_SMC_RSU_ERROR */ #define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18 #define INTEL_SIP_SMC_RSU_MAX_RETRY \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY) PK ! �U� stratix10-svc-client.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation */ #ifndef __STRATIX10_SVC_CLIENT_H #define __STRATIX10_SVC_CLIENT_H /* * Service layer driver supports client names * * fpga: for FPGA configuration * rsu: for remote status update */ #define SVC_CLIENT_FPGA "fpga" #define SVC_CLIENT_RSU "rsu" /* * Status of the sent command, in bit number * * SVC_STATUS_OK: * Secure firmware accepts the request issued by one of service clients. * * SVC_STATUS_BUFFER_SUBMITTED: * Service client successfully submits data buffer to secure firmware. * * SVC_STATUS_BUFFER_DONE: * Secure firmware completes data process, ready to accept the * next WRITE transaction. * * SVC_STATUS_COMPLETED: * Secure firmware completes service request successfully. In case of * FPGA configuration, FPGA should be in user mode. * * SVC_COMMAND_STATUS_BUSY: * Service request is still in process. * * SVC_COMMAND_STATUS_ERROR: * Error encountered during the process of the service request. * * SVC_STATUS_NO_SUPPORT: * Secure firmware doesn't support requested features such as RSU retry * or RSU notify. */ #define SVC_STATUS_OK 0 #define SVC_STATUS_BUFFER_SUBMITTED 1 #define SVC_STATUS_BUFFER_DONE 2 #define SVC_STATUS_COMPLETED 3 #define SVC_STATUS_BUSY 4 #define SVC_STATUS_ERROR 5 #define SVC_STATUS_NO_SUPPORT 6 /* * Flag bit for COMMAND_RECONFIG * * COMMAND_RECONFIG_FLAG_PARTIAL: * Set to FPGA configuration type (full or partial). */ #define COMMAND_RECONFIG_FLAG_PARTIAL 0 /* * Timeout settings for service clients: * timeout value used in Stratix10 FPGA manager driver. * timeout value used in RSU driver */ #define SVC_RECONFIG_REQUEST_TIMEOUT_MS 300 #define SVC_RECONFIG_BUFFER_TIMEOUT_MS 720 #define SVC_RSU_REQUEST_TIMEOUT_MS 300 struct stratix10_svc_chan; /** * enum stratix10_svc_command_code - supported service commands * * @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting * * @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status * is SVC_STATUS_OK * * @COMMAND_RECONFIG_DATA_SUBMIT: submit buffer(s) of bit-stream data for the * FPGA configuration, return status is SVC_STATUS_SUBMITTED or SVC_STATUS_ERROR * * @COMMAND_RECONFIG_DATA_CLAIM: check the status of the configuration, return * status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR * * @COMMAND_RECONFIG_STATUS: check the status of the configuration, return * status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR * * @COMMAND_RSU_STATUS: request remote system update boot log, return status * is log data or SVC_STATUS_RSU_ERROR * * @COMMAND_RSU_UPDATE: set the offset of the bitstream to boot after reboot, * return status is SVC_STATUS_OK or SVC_STATUS_ERROR * * @COMMAND_RSU_NOTIFY: report the status of hard processor system * software to firmware, return status is SVC_STATUS_OK or * SVC_STATUS_ERROR * * @COMMAND_RSU_RETRY: query firmware for the current image's retry counter, * return status is SVC_STATUS_OK or SVC_STATUS_ERROR * * @COMMAND_RSU_MAX_RETRY: query firmware for the max retry value, * return status is SVC_STATUS_OK or SVC_STATUS_ERROR * * @COMMAND_RSU_DCMF_VERSION: query firmware for the DCMF version, return status * is SVC_STATUS_OK or SVC_STATUS_ERROR */ enum stratix10_svc_command_code { COMMAND_NOOP = 0, COMMAND_RECONFIG, COMMAND_RECONFIG_DATA_SUBMIT, COMMAND_RECONFIG_DATA_CLAIM, COMMAND_RECONFIG_STATUS, COMMAND_RSU_STATUS, COMMAND_RSU_UPDATE, COMMAND_RSU_NOTIFY, COMMAND_RSU_RETRY, COMMAND_RSU_MAX_RETRY, COMMAND_RSU_DCMF_VERSION, }; /** * struct stratix10_svc_client_msg - message sent by client to service * @payload: starting address of data need be processed * @payload_length: data size in bytes * @command: service command * @arg: args to be passed via registers and not physically mapped buffers */ struct stratix10_svc_client_msg { void *payload; size_t payload_length; enum stratix10_svc_command_code command; u64 arg[3]; }; /** * struct stratix10_svc_command_config_type - config type * @flags: flag bit for the type of FPGA configuration */ struct stratix10_svc_command_config_type { u32 flags; }; /** * struct stratix10_svc_cb_data - callback data structure from service layer * @status: the status of sent command * @kaddr1: address of 1st completed data block * @kaddr2: address of 2nd completed data block * @kaddr3: address of 3rd completed data block */ struct stratix10_svc_cb_data { u32 status; void *kaddr1; void *kaddr2; void *kaddr3; }; /** * struct stratix10_svc_client - service client structure * @dev: the client device * @receive_cb: callback to provide service client the received data * @priv: client private data */ struct stratix10_svc_client { struct device *dev; void (*receive_cb)(struct stratix10_svc_client *client, struct stratix10_svc_cb_data *cb_data); void *priv; }; /** * stratix10_svc_request_channel_byname() - request service channel * @client: identity of the client requesting the channel * @name: supporting client name defined above * * Return: a pointer to channel assigned to the client on success, * or ERR_PTR() on error. */ struct stratix10_svc_chan *stratix10_svc_request_channel_byname(struct stratix10_svc_client *client, const char *name); /** * stratix10_svc_free_channel() - free service channel. * @chan: service channel to be freed */ void stratix10_svc_free_channel(struct stratix10_svc_chan *chan); /** * stratix10_svc_allocate_memory() - allocate the momory * @chan: service channel assigned to the client * @size: number of bytes client requests * * Service layer allocates the requested number of bytes from the memory * pool for the client. * * Return: the starting address of allocated memory on success, or * ERR_PTR() on error. */ void *stratix10_svc_allocate_memory(struct stratix10_svc_chan *chan, size_t size); /** * stratix10_svc_free_memory() - free allocated memory * @chan: service channel assigned to the client * @kaddr: starting address of memory to be free back to pool */ void stratix10_svc_free_memory(struct stratix10_svc_chan *chan, void *kaddr); /** * stratix10_svc_send() - send a message to the remote * @chan: service channel assigned to the client * @msg: message data to be sent, in the format of * struct stratix10_svc_client_msg * * Return: 0 for success, -ENOMEM or -ENOBUFS on error. */ int stratix10_svc_send(struct stratix10_svc_chan *chan, void *msg); /** * stratix10_svc_done() - complete service request * @chan: service channel assigned to the client * * This function is used by service client to inform service layer that * client's service requests are completed, or there is an error in the * request process. */ void stratix10_svc_done(struct stratix10_svc_chan *chan); #endif PK ! 7�;6, 6, Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only # # Intel network device configuration # config NET_VENDOR_INTEL bool "Intel devices" default y help If you have a network (Ethernet) card belonging to this class, say Y. Note that the answer to this question doesn't directly affect the kernel: saying N will just cause the configurator to skip all the questions about Intel cards. If you say Y, you will be asked for your specific card in the following questions. if NET_VENDOR_INTEL config E100 tristate "Intel(R) PRO/100+ support" depends on PCI select MII help This driver supports Intel(R) PRO/100 family of adapters. To verify that your adapter is supported, find the board ID number on the adapter. Look for a label that has a barcode and a number in the format 123456-001 (six digits hyphen three digits). Use the above information and the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> to identify the adapter. More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/e100.rst>. To compile this driver as a module, choose M here. The module will be called e100. config E1000 tristate "Intel(R) PRO/1000 Gigabit Ethernet support" depends on PCI help This driver supports Intel(R) PRO/1000 gigabit ethernet family of adapters. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/e1000.rst>. To compile this driver as a module, choose M here. The module will be called e1000. config E1000E tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support" depends on PCI && (!SPARC32 || BROKEN) depends on PTP_1588_CLOCK_OPTIONAL select CRC32 help This driver supports the PCI-Express Intel(R) PRO/1000 gigabit ethernet family of adapters. For PCI or PCI-X e1000 adapters, use the regular e1000 driver For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/e1000e.rst>. To compile this driver as a module, choose M here. The module will be called e1000e. config E1000E_HWTS bool "Support HW cross-timestamp on PCH devices" default y depends on E1000E && X86 help Say Y to enable hardware supported cross-timestamping on PCH devices. The cross-timestamp is available through the PTP clock driver precise cross-timestamp ioctl (PTP_SYS_OFFSET_PRECISE). config IGB tristate "Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support" depends on PCI depends on PTP_1588_CLOCK_OPTIONAL select I2C select I2C_ALGOBIT help This driver supports Intel(R) 82575/82576 gigabit ethernet family of adapters. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/igb.rst>. To compile this driver as a module, choose M here. The module will be called igb. config IGB_HWMON bool "Intel(R) PCI-Express Gigabit adapters HWMON support" default y depends on IGB && HWMON && !(IGB=y && HWMON=m) help Say Y if you want to expose thermal sensor data on Intel devices. Some of our devices contain thermal sensors, both external and internal. This data is available via the hwmon sysfs interface and exposes the onboard sensors. config IGB_DCA bool "Direct Cache Access (DCA) Support" default y depends on IGB && DCA && !(IGB=y && DCA=m) help Say Y here if you want to use Direct Cache Access (DCA) in the driver. DCA is a method for warming the CPU cache before data is used, with the intent of lessening the impact of cache misses. config IGBVF tristate "Intel(R) 82576 Virtual Function Ethernet support" depends on PCI help This driver supports Intel(R) 82576 virtual functions. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/igbvf.rst>. To compile this driver as a module, choose M here. The module will be called igbvf. config IXGB tristate "Intel(R) PRO/10GbE support" depends on PCI help This driver supports Intel(R) PRO/10GbE family of adapters for PCI-X type cards. For PCI-E type cards, use the "ixgbe" driver instead. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/ixgb.rst>. To compile this driver as a module, choose M here. The module will be called ixgb. config IXGBE tristate "Intel(R) 10GbE PCI Express adapters support" depends on PCI depends on PTP_1588_CLOCK_OPTIONAL select MDIO select PHYLIB help This driver supports Intel(R) 10GbE PCI Express family of adapters. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/ixgbe.rst>. To compile this driver as a module, choose M here. The module will be called ixgbe. config IXGBE_HWMON bool "Intel(R) 10GbE PCI Express adapters HWMON support" default y depends on IXGBE && HWMON && !(IXGBE=y && HWMON=m) help Say Y if you want to expose the thermal sensor data on some of our cards, via a hwmon sysfs interface. config IXGBE_DCA bool "Direct Cache Access (DCA) Support" default y depends on IXGBE && DCA && !(IXGBE=y && DCA=m) help Say Y here if you want to use Direct Cache Access (DCA) in the driver. DCA is a method for warming the CPU cache before data is used, with the intent of lessening the impact of cache misses. config IXGBE_DCB bool "Data Center Bridging (DCB) Support" default n depends on IXGBE && DCB help Say Y here if you want to use Data Center Bridging (DCB) in the driver. If unsure, say N. config IXGBE_IPSEC bool "IPSec XFRM cryptography-offload acceleration" depends on IXGBE depends on XFRM_OFFLOAD default y select XFRM_ALGO help Enable support for IPSec offload in ixgbe.ko config IXGBEVF tristate "Intel(R) 10GbE PCI Express Virtual Function Ethernet support" depends on PCI_MSI help This driver supports Intel(R) PCI Express virtual functions for the Intel(R) ixgbe driver. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/ixgbevf.rst>. To compile this driver as a module, choose M here. The module will be called ixgbevf. MSI-X interrupt support is required for this driver to work correctly. config IXGBEVF_IPSEC bool "IPSec XFRM cryptography-offload acceleration" depends on IXGBEVF depends on XFRM_OFFLOAD default y select XFRM_ALGO help Enable support for IPSec offload in ixgbevf.ko config I40E tristate "Intel(R) Ethernet Controller XL710 Family support" depends on PTP_1588_CLOCK_OPTIONAL depends on PCI select AUXILIARY_BUS help This driver supports Intel(R) Ethernet Controller XL710 Family of devices. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/i40e.rst>. To compile this driver as a module, choose M here. The module will be called i40e. config I40E_DCB bool "Data Center Bridging (DCB) Support" default n depends on I40E && DCB help Say Y here if you want to use Data Center Bridging (DCB) in the driver. If unsure, say N. # this is here to allow seamless migration from I40EVF --> IAVF name # so that CONFIG_IAVF symbol will always mirror the state of CONFIG_I40EVF config IAVF tristate config I40EVF tristate "Intel(R) Ethernet Adaptive Virtual Function support" select IAVF depends on PCI_MSI help This driver supports virtual functions for Intel XL710, X710, X722, XXV710, and all devices advertising support for Intel Ethernet Adaptive Virtual Function devices. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <https://support.intel.com> This driver was formerly named i40evf. More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/iavf.rst>. To compile this driver as a module, choose M here. The module will be called iavf. MSI-X interrupt support is required for this driver to work correctly. config ICE tristate "Intel(R) Ethernet Connection E800 Series Support" default n depends on PCI_MSI depends on PTP_1588_CLOCK_OPTIONAL select AUXILIARY_BUS select DIMLIB select NET_DEVLINK select PLDMFW help This driver supports Intel(R) Ethernet Connection E800 Series of devices. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/ice.rst>. To compile this driver as a module, choose M here. The module will be called ice. config FM10K tristate "Intel(R) FM10000 Ethernet Switch Host Interface Support" default n depends on PCI_MSI depends on PTP_1588_CLOCK_OPTIONAL help This driver supports Intel(R) FM10000 Ethernet Switch Host Interface. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> More specific information on configuring the driver is in <file:Documentation/networking/device_drivers/ethernet/intel/fm10k.rst>. To compile this driver as a module, choose M here. The module will be called fm10k. MSI-X interrupt support is required config IGC tristate "Intel(R) Ethernet Controller I225-LM/I225-V support" default n depends on PCI depends on PTP_1588_CLOCK_OPTIONAL help This driver supports Intel(R) Ethernet Controller I225-LM/I225-V family of adapters. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: <http://support.intel.com> To compile this driver as a module, choose M here. The module will be called igc. endif # NET_VENDOR_INTEL PK ! � %�� � ipu3/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only config VIDEO_IPU3_CIO2 tristate "Intel ipu3-cio2 driver" depends on VIDEO_V4L2 && PCI depends on ACPI || COMPILE_TEST depends on X86 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE select VIDEOBUF2_DMA_SG help This is the Intel IPU3 CIO2 CSI-2 receiver unit, found in Intel Skylake and Kaby Lake SoCs and used for capturing images and video from a camera sensor. Say Y or M here if you have a Skylake/Kaby Lake SoC with MIPI CSI-2 connected camera. The module will be called ipu3-cio2. config CIO2_BRIDGE bool "IPU3 CIO2 Sensors Bridge" depends on VIDEO_IPU3_CIO2 && ACPI help This extension provides an API for the ipu3-cio2 driver to create connections to cameras that are hidden in the SSDB buffer in ACPI. It can be used to enable support for cameras in detachable / hybrid devices that ship with Windows. Say Y here if your device is a detachable / hybrid laptop that comes with Windows installed by the OEM, for example: - Microsoft Surface models (except Surface Pro 3) - The Lenovo Miix line (for example the 510, 520, 710 and 720) - Dell 7285 If in doubt, say N here. PK ! �YL� � ipu3/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_VIDEO_IPU3_CIO2) += ipu3-cio2.o ipu3-cio2-y += ipu3-cio2-main.o ipu3-cio2-$(CONFIG_CIO2_BRIDGE) += cio2-bridge.o PK ! "f�ʮ � ipu6/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # Copyright (c) 2017 - 2020 Intel Corporation. ifneq ($(EXTERNAL_BUILD), 1) srcpath := $(srctree) endif ccflags-y += -DIPU_TPG_FRAME_SYNC -DIPU_PSYS_GPC \ -DIPU_ISYS_GPC intel-ipu6-objs += ../ipu.o \ ../ipu-bus.o \ ../ipu-dma.o \ ../ipu-mmu.o \ ../ipu-buttress.o \ ../ipu-trace.o \ ../ipu-cpd.o \ ipu6.o \ ../ipu-fw-com.o obj-$(CONFIG_VIDEO_INTEL_IPU6) += intel-ipu6.o intel-ipu6-isys-objs += ../ipu-isys.o \ ../ipu-isys-csi2.o \ ipu6-isys.o \ ipu6-isys-phy.o \ ipu6-isys-csi2.o \ ipu6-isys-gpc.o \ ../ipu-isys-csi2-be-soc.o \ ../ipu-fw-isys.o \ ../ipu-isys-video.o \ ../ipu-isys-queue.o \ ../ipu-isys-subdev.o obj-$(CONFIG_VIDEO_INTEL_IPU6) += intel-ipu6-isys.o intel-ipu6-psys-objs += ../ipu-psys.o \ ipu6-psys.o \ ipu-resources.o \ ipu6-psys-gpc.o \ ipu6-l-scheduler.o \ ipu6-ppg.o intel-ipu6-psys-objs += ipu-fw-resources.o \ ipu6-fw-resources.o \ ipu6se-fw-resources.o \ ipu6ep-fw-resources.o \ ../ipu-fw-psys.o ifeq ($(CONFIG_COMPAT),y) intel-ipu6-psys-objs += ../ipu-psys-compat32.o endif obj-$(CONFIG_VIDEO_INTEL_IPU6) += intel-ipu6-psys.o ccflags-y += -I$(srcpath)/$(src)/../../../../../include/ ccflags-y += -I$(srcpath)/$(src)/../ ccflags-y += -I$(srcpath)/$(src)/ PK ! �7.v v int340x_thermal/Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only # # ACPI INT340x thermal drivers configuration # config INT340X_THERMAL tristate "ACPI INT340X thermal drivers" depends on X86_64 && ACPI && PCI select THERMAL_GOV_USER_SPACE select ACPI_THERMAL_REL select ACPI_FAN select INTEL_SOC_DTS_IOSF_CORE select PROC_THERMAL_MMIO_RAPL if POWERCAP help Newer laptops and tablets that use ACPI may have thermal sensors and other devices with thermal control capabilities outside the core CPU/SOC, for thermal safety reasons. They are exposed for the OS to use via the INT3400 ACPI device object as the master, and INT3401~INT340B ACPI device objects as the slaves. Enable this to expose the temperature information and cooling ability from these objects to userspace via the normal thermal framework. This means that a wide range of applications and GUI widgets can show the information to the user or use this information for making decisions. For example, the Intel Thermal Daemon can use this information to allow the user to select his laptop to run without turning on the fans. config ACPI_THERMAL_REL tristate depends on ACPI if INT340X_THERMAL config INT3406_THERMAL tristate "ACPI INT3406 display thermal driver" depends on ACPI_VIDEO help The display thermal device represents the LED/LCD display panel that may or may not include touch support. The main function of the display thermal device is to allow control of the display brightness in order to address a thermal condition or to reduce power consumed by display device. config PROC_THERMAL_MMIO_RAPL tristate select INTEL_RAPL_CORE endif PK ! p�� int340x_thermal/Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_INT340X_THERMAL) += int3400_thermal.o obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal_zone.o obj-$(CONFIG_INT340X_THERMAL) += int3402_thermal.o obj-$(CONFIG_INT340X_THERMAL) += int3403_thermal.o obj-$(CONFIG_INT340X_THERMAL) += processor_thermal_device.o obj-$(CONFIG_INT340X_THERMAL) += int3401_thermal.o obj-$(CONFIG_INT340X_THERMAL) += processor_thermal_device_pci_legacy.o obj-$(CONFIG_INT340X_THERMAL) += processor_thermal_device_pci.o obj-$(CONFIG_PROC_THERMAL_MMIO_RAPL) += processor_thermal_rapl.o obj-$(CONFIG_INT340X_THERMAL) += processor_thermal_rfim.o obj-$(CONFIG_INT340X_THERMAL) += processor_thermal_mbox.o obj-$(CONFIG_INT3406_THERMAL) += int3406_thermal.o obj-$(CONFIG_ACPI_THERMAL_REL) += acpi_thermal_rel.o PK ! KI� � $ telemetry/intel_telemetry_debugfs.konu �[��� ELF >