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PK ! internal.hnu �[��� PK ! ���� � xcr.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_FPU_XCR_H #define _ASM_X86_FPU_XCR_H #define XCR_XFEATURE_ENABLED_MASK 0x00000000 static inline u64 xgetbv(u32 index) { u32 eax, edx; asm volatile("xgetbv" : "=a" (eax), "=d" (edx) : "c" (index)); return eax + ((u64)edx << 32); } static inline void xsetbv(u32 index, u64 value) { u32 eax = value; u32 edx = value >> 32; asm volatile("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); } #endif /* _ASM_X86_FPU_XCR_H */ PK ! � ��( ( xstate.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_X86_XSAVE_H #define __ASM_X86_XSAVE_H #include <linux/uaccess.h> #include <linux/types.h> #include <asm/processor.h> #include <asm/fpu/api.h> #include <asm/user.h> /* Bit 63 of XCR0 is reserved for future expansion */ #define XFEATURE_MASK_EXTEND (~(XFEATURE_MASK_FPSSE | (1ULL << 63))) #define XSTATE_CPUID 0x0000000d #define TILE_CPUID 0x0000001d #define FXSAVE_SIZE 512 #define XSAVE_HDR_SIZE 64 #define XSAVE_HDR_OFFSET FXSAVE_SIZE #define XSAVE_YMM_SIZE 256 #define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET) #define XSAVE_ALIGNMENT 64 /* All currently supported user features */ #define XFEATURE_MASK_USER_SUPPORTED (XFEATURE_MASK_FP | \ XFEATURE_MASK_SSE | \ XFEATURE_MASK_YMM | \ XFEATURE_MASK_OPMASK | \ XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM | \ XFEATURE_MASK_PKRU | \ XFEATURE_MASK_BNDREGS | \ XFEATURE_MASK_BNDCSR | \ XFEATURE_MASK_XTILE) /* * Features which are restored when returning to user space. * PKRU is not restored on return to user space because PKRU * is switched eagerly in switch_to() and flush_thread() */ #define XFEATURE_MASK_USER_RESTORE \ (XFEATURE_MASK_USER_SUPPORTED & ~XFEATURE_MASK_PKRU) /* Features which are dynamically enabled for a process on request */ #define XFEATURE_MASK_USER_DYNAMIC XFEATURE_MASK_XTILE_DATA /* All currently supported supervisor features */ #define XFEATURE_MASK_SUPERVISOR_SUPPORTED (XFEATURE_MASK_PASID) /* * A supervisor state component may not always contain valuable information, * and its size may be huge. Saving/restoring such supervisor state components * at each context switch can cause high CPU and space overhead, which should * be avoided. Such supervisor state components should only be saved/restored * on demand. The on-demand supervisor features are set in this mask. * * Unlike the existing supported supervisor features, an independent supervisor * feature does not allocate a buffer in task->fpu, and the corresponding * supervisor state component cannot be saved/restored at each context switch. * * To support an independent supervisor feature, a developer should follow the * dos and don'ts as below: * - Do dynamically allocate a buffer for the supervisor state component. * - Do manually invoke the XSAVES/XRSTORS instruction to save/restore the * state component to/from the buffer. * - Don't set the bit corresponding to the independent supervisor feature in * IA32_XSS at run time, since it has been set at boot time. */ #define XFEATURE_MASK_INDEPENDENT (XFEATURE_MASK_LBR) /* * Unsupported supervisor features. When a supervisor feature in this mask is * supported in the future, move it to the supported supervisor feature mask. */ #define XFEATURE_MASK_SUPERVISOR_UNSUPPORTED (XFEATURE_MASK_PT) /* All supervisor states including supported and unsupported states. */ #define XFEATURE_MASK_SUPERVISOR_ALL (XFEATURE_MASK_SUPERVISOR_SUPPORTED | \ XFEATURE_MASK_INDEPENDENT | \ XFEATURE_MASK_SUPERVISOR_UNSUPPORTED) /* * The feature mask required to restore FPU state: * - All user states which are not eagerly switched in switch_to()/exec() * - The suporvisor states */ #define XFEATURE_MASK_FPSTATE (XFEATURE_MASK_USER_RESTORE | \ XFEATURE_MASK_SUPERVISOR_SUPPORTED) extern u64 xstate_fx_sw_bytes[USER_XSTATE_FX_SW_WORDS]; extern void __init update_regset_xstate_info(unsigned int size, u64 xstate_mask); int xfeature_size(int xfeature_nr); void xsaves(struct xregs_state *xsave, u64 mask); void xrstors(struct xregs_state *xsave, u64 mask); int xfd_enable_feature(u64 xfd_err); #ifdef CONFIG_X86_64 DECLARE_STATIC_KEY_FALSE(__fpu_state_size_dynamic); #endif #ifdef CONFIG_X86_64 DECLARE_STATIC_KEY_FALSE(__fpu_state_size_dynamic); static __always_inline __pure bool fpu_state_size_dynamic(void) { return static_branch_unlikely(&__fpu_state_size_dynamic); } #else static __always_inline __pure bool fpu_state_size_dynamic(void) { return false; } #endif #endif PK ! E _�� � api.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 1994 Linus Torvalds * * Pentium III FXSR, SSE support * General FPU state handling cleanups * Gareth Hughes <gareth@valinux.com>, May 2000 * x86-64 work by Andi Kleen 2002 */ #ifndef _ASM_X86_FPU_API_H #define _ASM_X86_FPU_API_H #include <linux/bottom_half.h> #include <asm/fpu/types.h> /* * Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It * disables preemption so be careful if you intend to use it for long periods * of time. * If you intend to use the FPU in irq/softirq you need to check first with * irq_fpu_usable() if it is possible. */ /* Kernel FPU states to initialize in kernel_fpu_begin_mask() */ #define KFPU_387 _BITUL(0) /* 387 state will be initialized */ #define KFPU_MXCSR _BITUL(1) /* MXCSR will be initialized */ extern void kernel_fpu_begin_mask(unsigned int kfpu_mask); extern void kernel_fpu_end(void); extern bool irq_fpu_usable(void); extern void fpregs_mark_activate(void); /* Code that is unaware of kernel_fpu_begin_mask() can use this */ static inline void kernel_fpu_begin(void) { #ifdef CONFIG_X86_64 /* * Any 64-bit code that uses 387 instructions must explicitly request * KFPU_387. */ kernel_fpu_begin_mask(KFPU_MXCSR); #else /* * 32-bit kernel code may use 387 operations as well as SSE2, etc, * as long as it checks that the CPU has the required capability. */ kernel_fpu_begin_mask(KFPU_387 | KFPU_MXCSR); #endif } /* * Use fpregs_lock() while editing CPU's FPU registers or fpu->fpstate. * A context switch will (and softirq might) save CPU's FPU registers to * fpu->fpstate.regs and set TIF_NEED_FPU_LOAD leaving CPU's FPU registers in * a random state. * * local_bh_disable() protects against both preemption and soft interrupts * on !RT kernels. * * On RT kernels local_bh_disable() is not sufficient because it only * serializes soft interrupt related sections via a local lock, but stays * preemptible. Disabling preemption is the right choice here as bottom * half processing is always in thread context on RT kernels so it * implicitly prevents bottom half processing as well. * * Disabling preemption also serializes against kernel_fpu_begin(). */ static inline void fpregs_lock(void) { if (!IS_ENABLED(CONFIG_PREEMPT_RT)) local_bh_disable(); else preempt_disable(); } static inline void fpregs_unlock(void) { if (!IS_ENABLED(CONFIG_PREEMPT_RT)) local_bh_enable(); else preempt_enable(); } #ifdef CONFIG_X86_DEBUG_FPU extern void fpregs_assert_state_consistent(void); #else static inline void fpregs_assert_state_consistent(void) { } #endif /* * Load the task FPU state before returning to userspace. */ extern void switch_fpu_return(void); /* * Query the presence of one or more xfeatures. Works on any legacy CPU as well. * * If 'feature_name' is set then put a human-readable description of * the feature there as well - this can be used to print error (or success) * messages. */ extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name); /* * Tasks that are not using SVA have mm->pasid set to zero to note that they * will not have the valid bit set in MSR_IA32_PASID while they are running. */ #define PASID_DISABLED 0 static inline void update_pasid(void) { } /* Trap handling */ extern int fpu__exception_code(struct fpu *fpu, int trap_nr); extern void fpu_sync_fpstate(struct fpu *fpu); extern void fpu_reset_from_exception_fixup(void); /* Boot, hotplug and resume */ extern void fpu__init_cpu(void); extern void fpu__init_system(void); extern void fpu__init_check_bugs(void); extern void fpu__resume_cpu(void); #ifdef CONFIG_MATH_EMULATION extern void fpstate_init_soft(struct swregs_state *soft); #else static inline void fpstate_init_soft(struct swregs_state *soft) {} #endif /* State tracking */ DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); /* Process cleanup */ #ifdef CONFIG_X86_64 extern void fpstate_free(struct fpu *fpu); #else static inline void fpstate_free(struct fpu *fpu) { } #endif /* fpstate-related functions which are exported to KVM */ extern void fpstate_clear_xstate_component(struct fpstate *fps, unsigned int xfeature); /* KVM specific functions */ extern bool fpu_alloc_guest_fpstate(struct fpu_guest *gfpu); extern void fpu_free_guest_fpstate(struct fpu_guest *gfpu); extern int fpu_swap_kvm_fpstate(struct fpu_guest *gfpu, bool enter_guest); extern void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest *gfpu, void *buf, unsigned int size, u64 xfeatures, u32 pkru); extern int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest *gfpu, const void *buf, u64 xcr0, u32 *vpkru); static inline void fpstate_set_confidential(struct fpu_guest *gfpu) { gfpu->fpstate->is_confidential = true; } static inline bool fpstate_is_confidential(struct fpu_guest *gfpu) { return gfpu->fpstate->is_confidential; } /* prctl */ struct task_struct; extern long fpu_xstate_prctl(struct task_struct *tsk, int option, unsigned long arg2); #endif /* _ASM_X86_FPU_API_H */ PK ! ��[ sched.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_FPU_SCHED_H #define _ASM_X86_FPU_SCHED_H #include <linux/sched.h> #include <asm/cpufeature.h> #include <asm/fpu/types.h> #include <asm/trace/fpu.h> extern void save_fpregs_to_fpstate(struct fpu *fpu); extern void fpu__drop(struct fpu *fpu); extern int fpu_clone(struct task_struct *dst, unsigned long clone_flags); extern void fpu_flush_thread(void); /* * FPU state switching for scheduling. * * This is a two-stage process: * * - switch_fpu_prepare() saves the old state. * This is done within the context of the old process. * * - switch_fpu_finish() sets TIF_NEED_FPU_LOAD; the floating point state * will get loaded on return to userspace, or when the kernel needs it. * * If TIF_NEED_FPU_LOAD is cleared then the CPU's FPU registers * are saved in the current thread's FPU register state. * * If TIF_NEED_FPU_LOAD is set then CPU's FPU registers may not * hold current()'s FPU registers. It is required to load the * registers before returning to userland or using the content * otherwise. * * The FPU context is only stored/restored for a user task and * PF_KTHREAD is used to distinguish between kernel and user threads. */ static inline void switch_fpu_prepare(struct fpu *old_fpu, int cpu) { if (cpu_feature_enabled(X86_FEATURE_FPU) && !(current->flags & PF_KTHREAD)) { save_fpregs_to_fpstate(old_fpu); /* * The save operation preserved register state, so the * fpu_fpregs_owner_ctx is still @old_fpu. Store the * current CPU number in @old_fpu, so the next return * to user space can avoid the FPU register restore * when is returns on the same CPU and still owns the * context. */ old_fpu->last_cpu = cpu; trace_x86_fpu_regs_deactivated(old_fpu); } } /* * Delay loading of the complete FPU state until the return to userland. * PKRU is handled separately. */ static inline void switch_fpu_finish(void) { if (cpu_feature_enabled(X86_FEATURE_FPU)) set_thread_flag(TIF_NEED_FPU_LOAD); } #endif /* _ASM_X86_FPU_SCHED_H */ PK ! �#p��5 �5 types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * FPU data structures: */ #ifndef _ASM_X86_FPU_H #define _ASM_X86_FPU_H /* * The legacy x87 FPU state format, as saved by FSAVE and * restored by the FRSTOR instructions: */ struct fregs_state { u32 cwd; /* FPU Control Word */ u32 swd; /* FPU Status Word */ u32 twd; /* FPU Tag Word */ u32 fip; /* FPU IP Offset */ u32 fcs; /* FPU IP Selector */ u32 foo; /* FPU Operand Pointer Offset */ u32 fos; /* FPU Operand Pointer Selector */ /* 8*10 bytes for each FP-reg = 80 bytes: */ u32 st_space[20]; /* Software status information [not touched by FSAVE]: */ u32 status; }; /* * The legacy fx SSE/MMX FPU state format, as saved by FXSAVE and * restored by the FXRSTOR instructions. It's similar to the FSAVE * format, but differs in some areas, plus has extensions at * the end for the XMM registers. */ struct fxregs_state { u16 cwd; /* Control Word */ u16 swd; /* Status Word */ u16 twd; /* Tag Word */ u16 fop; /* Last Instruction Opcode */ union { struct { u64 rip; /* Instruction Pointer */ u64 rdp; /* Data Pointer */ }; struct { u32 fip; /* FPU IP Offset */ u32 fcs; /* FPU IP Selector */ u32 foo; /* FPU Operand Offset */ u32 fos; /* FPU Operand Selector */ }; }; u32 mxcsr; /* MXCSR Register State */ u32 mxcsr_mask; /* MXCSR Mask */ /* 8*16 bytes for each FP-reg = 128 bytes: */ u32 st_space[32]; /* 16*16 bytes for each XMM-reg = 256 bytes: */ u32 xmm_space[64]; u32 padding[12]; union { u32 padding1[12]; u32 sw_reserved[12]; }; } __attribute__((aligned(16))); /* Default value for fxregs_state.mxcsr: */ #define MXCSR_DEFAULT 0x1f80 /* Copy both mxcsr & mxcsr_flags with a single u64 memcpy: */ #define MXCSR_AND_FLAGS_SIZE sizeof(u64) /* * Software based FPU emulation state. This is arbitrary really, * it matches the x87 format to make it easier to understand: */ struct swregs_state { u32 cwd; u32 swd; u32 twd; u32 fip; u32 fcs; u32 foo; u32 fos; /* 8*10 bytes for each FP-reg = 80 bytes: */ u32 st_space[20]; u8 ftop; u8 changed; u8 lookahead; u8 no_update; u8 rm; u8 alimit; struct math_emu_info *info; u32 entry_eip; }; /* * List of XSAVE features Linux knows about: */ enum xfeature { XFEATURE_FP, XFEATURE_SSE, /* * Values above here are "legacy states". * Those below are "extended states". */ XFEATURE_YMM, XFEATURE_BNDREGS, XFEATURE_BNDCSR, XFEATURE_OPMASK, XFEATURE_ZMM_Hi256, XFEATURE_Hi16_ZMM, XFEATURE_PT_UNIMPLEMENTED_SO_FAR, XFEATURE_PKRU, XFEATURE_PASID, XFEATURE_RSRVD_COMP_11, XFEATURE_RSRVD_COMP_12, XFEATURE_RSRVD_COMP_13, XFEATURE_RSRVD_COMP_14, XFEATURE_LBR, XFEATURE_RSRVD_COMP_16, XFEATURE_XTILE_CFG, XFEATURE_XTILE_DATA, XFEATURE_MAX, }; #define XFEATURE_MASK_FP (1 << XFEATURE_FP) #define XFEATURE_MASK_SSE (1 << XFEATURE_SSE) #define XFEATURE_MASK_YMM (1 << XFEATURE_YMM) #define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS) #define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR) #define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK) #define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256) #define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM) #define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR) #define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU) #define XFEATURE_MASK_PASID (1 << XFEATURE_PASID) #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR) #define XFEATURE_MASK_XTILE_CFG (1 << XFEATURE_XTILE_CFG) #define XFEATURE_MASK_XTILE_DATA (1 << XFEATURE_XTILE_DATA) #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE) #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \ | XFEATURE_MASK_ZMM_Hi256 \ | XFEATURE_MASK_Hi16_ZMM) #ifdef CONFIG_X86_64 # define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA \ | XFEATURE_MASK_XTILE_CFG) #else # define XFEATURE_MASK_XTILE (0) #endif #define FIRST_EXTENDED_XFEATURE XFEATURE_YMM struct reg_128_bit { u8 regbytes[128/8]; }; struct reg_256_bit { u8 regbytes[256/8]; }; struct reg_512_bit { u8 regbytes[512/8]; }; struct reg_1024_byte { u8 regbytes[1024]; }; /* * State component 2: * * There are 16x 256-bit AVX registers named YMM0-YMM15. * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15) * and are stored in 'struct fxregs_state::xmm_space[]' in the * "legacy" area. * * The high 128 bits are stored here. */ struct ymmh_struct { struct reg_128_bit hi_ymm[16]; } __packed; /* Intel MPX support: */ struct mpx_bndreg { u64 lower_bound; u64 upper_bound; } __packed; /* * State component 3 is used for the 4 128-bit bounds registers */ struct mpx_bndreg_state { struct mpx_bndreg bndreg[4]; } __packed; /* * State component 4 is used for the 64-bit user-mode MPX * configuration register BNDCFGU and the 64-bit MPX status * register BNDSTATUS. We call the pair "BNDCSR". */ struct mpx_bndcsr { u64 bndcfgu; u64 bndstatus; } __packed; /* * The BNDCSR state is padded out to be 64-bytes in size. */ struct mpx_bndcsr_state { union { struct mpx_bndcsr bndcsr; u8 pad_to_64_bytes[64]; }; } __packed; /* AVX-512 Components: */ /* * State component 5 is used for the 8 64-bit opmask registers * k0-k7 (opmask state). */ struct avx_512_opmask_state { u64 opmask_reg[8]; } __packed; /* * State component 6 is used for the upper 256 bits of the * registers ZMM0-ZMM15. These 16 256-bit values are denoted * ZMM0_H-ZMM15_H (ZMM_Hi256 state). */ struct avx_512_zmm_uppers_state { struct reg_256_bit zmm_upper[16]; } __packed; /* * State component 7 is used for the 16 512-bit registers * ZMM16-ZMM31 (Hi16_ZMM state). */ struct avx_512_hi16_state { struct reg_512_bit hi16_zmm[16]; } __packed; /* * State component 9: 32-bit PKRU register. The state is * 8 bytes long but only 4 bytes is used currently. */ struct pkru_state { u32 pkru; u32 pad; } __packed; /* * State component 15: Architectural LBR configuration state. * The size of Arch LBR state depends on the number of LBRs (lbr_depth). */ struct lbr_entry { u64 from; u64 to; u64 info; }; struct arch_lbr_state { u64 lbr_ctl; u64 lbr_depth; u64 ler_from; u64 ler_to; u64 ler_info; struct lbr_entry entries[]; }; /* * State component 17: 64-byte tile configuration register. */ struct xtile_cfg { u64 tcfg[8]; } __packed; /* * State component 18: 1KB tile data register. * Each register represents 16 64-byte rows of the matrix * data. But the number of registers depends on the actual * implementation. */ struct xtile_data { struct reg_1024_byte tmm; } __packed; /* * State component 10 is supervisor state used for context-switching the * PASID state. */ struct ia32_pasid_state { u64 pasid; } __packed; struct xstate_header { u64 xfeatures; u64 xcomp_bv; u64 reserved[6]; } __attribute__((packed)); /* * xstate_header.xcomp_bv[63] indicates that the extended_state_area * is in compacted format. */ #define XCOMP_BV_COMPACTED_FORMAT ((u64)1 << 63) /* * This is our most modern FPU state format, as saved by the XSAVE * and restored by the XRSTOR instructions. * * It consists of a legacy fxregs portion, an xstate header and * subsequent areas as defined by the xstate header. Not all CPUs * support all the extensions, so the size of the extended area * can vary quite a bit between CPUs. */ struct xregs_state { struct fxregs_state i387; struct xstate_header header; u8 extended_state_area[0]; } __attribute__ ((packed, aligned (64))); /* * This is a union of all the possible FPU state formats * put together, so that we can pick the right one runtime. * * The size of the structure is determined by the largest * member - which is the xsave area. The padding is there * to ensure that statically-allocated task_structs (just * the init_task today) have enough space. */ union fpregs_state { struct fregs_state fsave; struct fxregs_state fxsave; struct swregs_state soft; struct xregs_state xsave; u8 __padding[PAGE_SIZE]; }; struct fpstate { /* @kernel_size: The size of the kernel register image */ unsigned int size; /* @user_size: The size in non-compacted UABI format */ unsigned int user_size; /* @xfeatures: xfeatures for which the storage is sized */ u64 xfeatures; /* @user_xfeatures: xfeatures valid in UABI buffers */ u64 user_xfeatures; /* @xfd: xfeatures disabled to trap userspace use. */ u64 xfd; /* @is_valloc: Indicator for dynamically allocated state */ unsigned int is_valloc : 1; /* @is_guest: Indicator for guest state (KVM) */ unsigned int is_guest : 1; /* * @is_confidential: Indicator for KVM confidential mode. * The FPU registers are restored by the * vmentry firmware from encrypted guest * memory. On vmexit the FPU registers are * saved by firmware to encrypted guest memory * and the registers are scrubbed before * returning to the host. So there is no * content which is worth saving and restoring. * The fpstate has to be there so that * preemption and softirq FPU usage works * without special casing. */ unsigned int is_confidential : 1; /* @in_use: State is in use */ unsigned int in_use : 1; /* @regs: The register state union for all supported formats */ union fpregs_state regs; /* @regs is dynamically sized! Don't add anything after @regs! */ } __aligned(64); struct fpu_state_perm { /* * @__state_perm: * * This bitmap indicates the permission for state components, which * are available to a thread group. The permission prctl() sets the * enabled state bits in thread_group_leader()->thread.fpu. * * All run time operations use the per thread information in the * currently active fpu.fpstate which contains the xfeature masks * and sizes for kernel and user space. * * This master permission field is only to be used when * task.fpu.fpstate based checks fail to validate whether the task * is allowed to expand it's xfeatures set which requires to * allocate a larger sized fpstate buffer. * * Do not access this field directly. Use the provided helper * function. Unlocked access is possible for quick checks. */ u64 __state_perm; /* * @__state_size: * * The size required for @__state_perm. Only valid to access * with sighand locked. */ unsigned int __state_size; /* * @__user_state_size: * * The size required for @__state_perm user part. Only valid to * access with sighand locked. */ unsigned int __user_state_size; }; /* * Highest level per task FPU state data structure that * contains the FPU register state plus various FPU * state fields: */ struct fpu { /* * @last_cpu: * * Records the last CPU on which this context was loaded into * FPU registers. (In the lazy-restore case we might be * able to reuse FPU registers across multiple context switches * this way, if no intermediate task used the FPU.) * * A value of -1 is used to indicate that the FPU state in context * memory is newer than the FPU state in registers, and that the * FPU state should be reloaded next time the task is run. */ unsigned int last_cpu; /* * @avx512_timestamp: * * Records the timestamp of AVX512 use during last context switch. */ unsigned long avx512_timestamp; /* * @fpstate: * * Pointer to the active struct fpstate. Initialized to * point at @__fpstate below. */ struct fpstate *fpstate; /* * @__task_fpstate: * * Pointer to an inactive struct fpstate. Initialized to NULL. Is * used only for KVM support to swap out the regular task fpstate. */ struct fpstate *__task_fpstate; /* * @perm: * * Permission related information */ struct fpu_state_perm perm; /* * @__fpstate: * * Initial in-memory storage for FPU registers which are saved in * context switch and when the kernel uses the FPU. The registers * are restored from this storage on return to user space if they * are not longer containing the tasks FPU register state. */ struct fpstate __fpstate; /* * WARNING: '__fpstate' is dynamically-sized. Do not put * anything after it here. */ }; /* * Guest pseudo FPU container */ struct fpu_guest { /* * @fpstate: Pointer to the allocated guest fpstate */ struct fpstate *fpstate; }; /* * FPU state configuration data. Initialized at boot time. Read only after init. */ struct fpu_state_config { /* * @max_size: * * The maximum size of the register state buffer. Includes all * supported features except independent managed features. */ unsigned int max_size; /* * @default_size: * * The default size of the register state buffer. Includes all * supported features except independent managed features and * features which have to be requested by user space before usage. */ unsigned int default_size; /* * @max_features: * * The maximum supported features bitmap. Does not include * independent managed features. */ u64 max_features; /* * @default_features: * * The default supported features bitmap. Does not include * independent managed features and features which have to * be requested by user space before usage. */ u64 default_features; /* * @legacy_features: * * Features which can be reported back to user space * even without XSAVE support, i.e. legacy features FP + SSE */ u64 legacy_features; /* * @independent_features: * * Features that are supported by XSAVES, but not managed as part of * the FPU core, such as LBR */ u64 independent_features; }; /* FPU state configuration information */ extern struct fpu_state_config fpu_kernel_cfg, fpu_user_cfg; #endif /* _ASM_X86_FPU_H */ PK ! ɰ�� � signal.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * x86 FPU signal frame handling methods: */ #ifndef _ASM_X86_FPU_SIGNAL_H #define _ASM_X86_FPU_SIGNAL_H #include <linux/compat.h> #include <linux/user.h> #include <asm/fpu/types.h> #ifdef CONFIG_X86_64 # include <uapi/asm/sigcontext.h> # include <asm/user32.h> struct ksignal; int ia32_setup_rt_frame(int sig, struct ksignal *ksig, compat_sigset_t *set, struct pt_regs *regs); int ia32_setup_frame(int sig, struct ksignal *ksig, compat_sigset_t *set, struct pt_regs *regs); #else # define user_i387_ia32_struct user_i387_struct # define user32_fxsr_struct user_fxsr_struct # define ia32_setup_frame __setup_frame # define ia32_setup_rt_frame __setup_rt_frame #endif extern void convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk); extern void convert_to_fxsr(struct fxregs_state *fxsave, const struct user_i387_ia32_struct *env); unsigned long fpu__alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx, unsigned long *size); unsigned long fpu__get_fpstate_size(void); extern bool copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size); extern void fpu__clear_user_states(struct fpu *fpu); extern bool fpu__restore_sig(void __user *buf, int ia32_frame); extern void restore_fpregs_from_fpstate(struct fpstate *fpstate, u64 mask); extern bool copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size); #endif /* _ASM_X86_FPU_SIGNAL_H */ PK ! �;e&} } regset.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * FPU regset handling methods: */ #ifndef _ASM_X86_FPU_REGSET_H #define _ASM_X86_FPU_REGSET_H #include <linux/regset.h> extern user_regset_active_fn regset_fpregs_active, regset_xregset_fpregs_active; extern user_regset_get2_fn fpregs_get, xfpregs_get, fpregs_soft_get, xstateregs_get; extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set, xstateregs_set; /* * xstateregs_active == regset_fpregs_active. Please refer to the comment * at the definition of regset_fpregs_active. */ #define xstateregs_active regset_fpregs_active #endif /* _ASM_X86_FPU_REGSET_H */ PK ! internal.hnu �[��� PK ! ���� � : xcr.hnu �[��� PK ! � ��( ( R xstate.hnu �[��� PK ! E _�� � � api.hnu �[��� PK ! ��[ �& sched.hnu �[��� PK ! �#p��5 �5 �. types.hnu �[��� PK ! ɰ�� � �d signal.hnu �[��� PK ! �;e&} } k regset.hnu �[��� PK : �m
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