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PK ! Av|8 8 cx25840.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * cx25840.h - definition for cx25840/1/2/3 inputs * * Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) */ #ifndef _CX25840_H_ #define _CX25840_H_ /* * Note that the cx25840 driver requires that the bridge driver calls the * v4l2_subdev's load_fw operation in order to load the driver's firmware. * This will load the firmware on the first invocation (further ones are NOP). * Without this the audio standard detection will fail and you will * only get mono. * Alternatively, you can call the reset operation (this can be done * multiple times if needed, each invocation will fully reinitialize * the device). * * Since loading the firmware is often problematic when the driver is * compiled into the kernel I recommend postponing calling this function * until the first open of the video device. Another reason for * postponing it is that loading this firmware takes a long time (seconds) * due to the slow i2c bus speed. So it will speed up the boot process if * you can avoid loading the fw as long as the video device isn't used. */ enum cx25840_video_input { /* Composite video inputs In1-In8 */ CX25840_COMPOSITE1 = 1, CX25840_COMPOSITE2, CX25840_COMPOSITE3, CX25840_COMPOSITE4, CX25840_COMPOSITE5, CX25840_COMPOSITE6, CX25840_COMPOSITE7, CX25840_COMPOSITE8, /* * S-Video inputs consist of one luma input (In1-In8) ORed with one * chroma input (In5-In8) */ CX25840_SVIDEO_LUMA1 = 0x10, CX25840_SVIDEO_LUMA2 = 0x20, CX25840_SVIDEO_LUMA3 = 0x30, CX25840_SVIDEO_LUMA4 = 0x40, CX25840_SVIDEO_LUMA5 = 0x50, CX25840_SVIDEO_LUMA6 = 0x60, CX25840_SVIDEO_LUMA7 = 0x70, CX25840_SVIDEO_LUMA8 = 0x80, CX25840_SVIDEO_CHROMA4 = 0x400, CX25840_SVIDEO_CHROMA5 = 0x500, CX25840_SVIDEO_CHROMA6 = 0x600, CX25840_SVIDEO_CHROMA7 = 0x700, CX25840_SVIDEO_CHROMA8 = 0x800, /* S-Video aliases for common luma/chroma combinations */ CX25840_SVIDEO1 = 0x510, CX25840_SVIDEO2 = 0x620, CX25840_SVIDEO3 = 0x730, CX25840_SVIDEO4 = 0x840, /* Allow frames to specify specific input configurations */ CX25840_VIN1_CH1 = 0x80000000, CX25840_VIN2_CH1 = 0x80000001, CX25840_VIN3_CH1 = 0x80000002, CX25840_VIN4_CH1 = 0x80000003, CX25840_VIN5_CH1 = 0x80000004, CX25840_VIN6_CH1 = 0x80000005, CX25840_VIN7_CH1 = 0x80000006, CX25840_VIN8_CH1 = 0x80000007, CX25840_VIN4_CH2 = 0x80000000, CX25840_VIN5_CH2 = 0x80000010, CX25840_VIN6_CH2 = 0x80000020, CX25840_NONE_CH2 = 0x80000030, CX25840_VIN7_CH3 = 0x80000000, CX25840_VIN8_CH3 = 0x80000040, CX25840_NONE0_CH3 = 0x80000080, CX25840_NONE1_CH3 = 0x800000c0, CX25840_SVIDEO_ON = 0x80000100, CX25840_COMPONENT_ON = 0x80000200, CX25840_DIF_ON = 0x80000400, }; /* * The defines below are used to set the chip video output settings * in the generic mode that can be enabled by calling the subdevice * init core op. * * The requested settings can be passed to the init core op as * @val parameter and to the s_routing video op as @config parameter. * * For details please refer to the section 3.7 Video Output Formatting and * to Video Out Control 1 to 4 registers in the section 5.6 Video Decoder Core * of the chip datasheet. */ #define CX25840_VCONFIG_FMT_SHIFT 0 #define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0) #define CX25840_VCONFIG_FMT_BT601 BIT(0) #define CX25840_VCONFIG_FMT_BT656 BIT(1) #define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0) #define CX25840_VCONFIG_FMT_VIP2 BIT(2) #define CX25840_VCONFIG_RES_SHIFT 3 #define CX25840_VCONFIG_RES_MASK GENMASK(4, 3) #define CX25840_VCONFIG_RES_8BIT BIT(3) #define CX25840_VCONFIG_RES_10BIT BIT(4) #define CX25840_VCONFIG_VBIRAW_SHIFT 5 #define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5) #define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5) #define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6) #define CX25840_VCONFIG_ANCDATA_SHIFT 7 #define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7) #define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7) #define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8) #define CX25840_VCONFIG_TASKBIT_SHIFT 9 #define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9) #define CX25840_VCONFIG_TASKBIT_ZERO BIT(9) #define CX25840_VCONFIG_TASKBIT_ONE BIT(10) #define CX25840_VCONFIG_ACTIVE_SHIFT 11 #define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11) #define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11) #define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12) #define CX25840_VCONFIG_VALID_SHIFT 13 #define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13) #define CX25840_VCONFIG_VALID_NORMAL BIT(13) #define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14) #define CX25840_VCONFIG_HRESETW_SHIFT 15 #define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15) #define CX25840_VCONFIG_HRESETW_NORMAL BIT(15) #define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16) #define CX25840_VCONFIG_CLKGATE_SHIFT 17 #define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17) #define CX25840_VCONFIG_CLKGATE_NONE BIT(17) #define CX25840_VCONFIG_CLKGATE_VALID BIT(18) #define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17) #define CX25840_VCONFIG_DCMODE_SHIFT 19 #define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19) #define CX25840_VCONFIG_DCMODE_DWORDS BIT(19) #define CX25840_VCONFIG_DCMODE_BYTES BIT(20) #define CX25840_VCONFIG_IDID0S_SHIFT 21 #define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21) #define CX25840_VCONFIG_IDID0S_NORMAL BIT(21) #define CX25840_VCONFIG_IDID0S_LINECNT BIT(22) #define CX25840_VCONFIG_VIPCLAMP_SHIFT 23 #define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23) #define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23) #define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24) enum cx25840_audio_input { /* Audio inputs: serial or In4-In8 */ CX25840_AUDIO_SERIAL, CX25840_AUDIO4 = 4, CX25840_AUDIO5, CX25840_AUDIO6, CX25840_AUDIO7, CX25840_AUDIO8, }; enum cx25840_io_pin { CX25840_PIN_DVALID_PRGM0 = 0, CX25840_PIN_FIELD_PRGM1, CX25840_PIN_HRESET_PRGM2, CX25840_PIN_VRESET_HCTL_PRGM3, CX25840_PIN_IRQ_N_PRGM4, CX25840_PIN_IR_TX_PRGM6, CX25840_PIN_IR_RX_PRGM5, CX25840_PIN_GPIO0_PRGM8, CX25840_PIN_GPIO1_PRGM9, CX25840_PIN_SA_SDIN, /* Alternate GP Input only */ CX25840_PIN_SA_SDOUT, /* Alternate GP Input only */ CX25840_PIN_PLL_CLK_PRGM7, CX25840_PIN_CHIP_SEL_VIPCLK, /* Output only */ }; enum cx25840_io_pad { /* Output pads, these must match the actual chip register values */ CX25840_PAD_DEFAULT = 0, CX25840_PAD_ACTIVE, CX25840_PAD_VACTIVE, CX25840_PAD_CBFLAG, CX25840_PAD_VID_DATA_EXT0, CX25840_PAD_VID_DATA_EXT1, CX25840_PAD_GPO0, CX25840_PAD_GPO1, CX25840_PAD_GPO2, CX25840_PAD_GPO3, CX25840_PAD_IRQ_N, CX25840_PAD_AC_SYNC, CX25840_PAD_AC_SDOUT, CX25840_PAD_PLL_CLK, CX25840_PAD_VRESET, CX25840_PAD_RESERVED, /* Pads for PLL_CLK output only */ CX25840_PAD_XTI_X5_DLL, CX25840_PAD_AUX_PLL, CX25840_PAD_VID_PLL, CX25840_PAD_XTI, /* Input Pads */ CX25840_PAD_GPI0, CX25840_PAD_GPI1, CX25840_PAD_GPI2, CX25840_PAD_GPI3, }; enum cx25840_io_pin_strength { CX25840_PIN_DRIVE_MEDIUM = 0, CX25840_PIN_DRIVE_SLOW, CX25840_PIN_DRIVE_FAST, }; enum cx23885_io_pin { CX23885_PIN_IR_RX_GPIO19, CX23885_PIN_IR_TX_GPIO20, CX23885_PIN_I2S_SDAT_GPIO21, CX23885_PIN_I2S_WCLK_GPIO22, CX23885_PIN_I2S_BCLK_GPIO23, CX23885_PIN_IRQ_N_GPIO16, }; enum cx23885_io_pad { CX23885_PAD_IR_RX, CX23885_PAD_GPIO19, CX23885_PAD_IR_TX, CX23885_PAD_GPIO20, CX23885_PAD_I2S_SDAT, CX23885_PAD_GPIO21, CX23885_PAD_I2S_WCLK, CX23885_PAD_GPIO22, CX23885_PAD_I2S_BCLK, CX23885_PAD_GPIO23, CX23885_PAD_IRQ_N, CX23885_PAD_GPIO16, }; /* * pvr150_workaround activates a workaround for a hardware bug that is * present in Hauppauge PVR-150 (and possibly PVR-500) cards that have * certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The * audio autodetect fails on some channels for these models and the workaround * is to select the audio standard explicitly. Many thanks to Hauppauge for * providing this information. * * This platform data only needs to be supplied by the ivtv driver. */ struct cx25840_platform_data { int pvr150_workaround; }; #endif PK ! D)T� � tea575x.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOUND_TEA575X_TUNER_H #define __SOUND_TEA575X_TUNER_H /* * ALSA driver for TEA5757/5759 Philips AM/FM tuner chips * * Copyright (c) 2004 Jaroslav Kysela <perex@perex.cz> */ #include <linux/videodev2.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-dev.h> #include <media/v4l2-device.h> #define TEA575X_FMIF 10700 #define TEA575X_AMIF 450 #define TEA575X_DATA (1 << 0) #define TEA575X_CLK (1 << 1) #define TEA575X_WREN (1 << 2) #define TEA575X_MOST (1 << 3) struct snd_tea575x; struct snd_tea575x_ops { /* Drivers using snd_tea575x must either define read_ and write_val */ void (*write_val)(struct snd_tea575x *tea, u32 val); u32 (*read_val)(struct snd_tea575x *tea); /* Or define the 3 pin functions */ void (*set_pins)(struct snd_tea575x *tea, u8 pins); u8 (*get_pins)(struct snd_tea575x *tea); void (*set_direction)(struct snd_tea575x *tea, bool output); }; struct snd_tea575x { struct v4l2_device *v4l2_dev; struct v4l2_file_operations fops; struct video_device vd; /* video device */ int radio_nr; /* radio_nr */ bool tea5759; /* 5759 chip is present */ bool has_am; /* Device can tune to AM freqs */ bool cannot_read_data; /* Device cannot read the data pin */ bool cannot_mute; /* Device cannot mute */ bool mute; /* Device is muted? */ bool stereo; /* receiving stereo */ bool tuned; /* tuned to a station */ unsigned int val; /* hw value */ u32 band; /* 0: FM, 1: FM-Japan, 2: AM */ u32 freq; /* frequency */ struct mutex mutex; const struct snd_tea575x_ops *ops; void *private_data; u8 card[32]; u8 bus_info[32]; struct v4l2_ctrl_handler ctrl_handler; int (*ext_init)(struct snd_tea575x *tea); }; int snd_tea575x_enum_freq_bands(struct snd_tea575x *tea, struct v4l2_frequency_band *band); int snd_tea575x_g_tuner(struct snd_tea575x *tea, struct v4l2_tuner *v); int snd_tea575x_s_hw_freq_seek(struct file *file, struct snd_tea575x *tea, const struct v4l2_hw_freq_seek *a); int snd_tea575x_hw_init(struct snd_tea575x *tea); int snd_tea575x_init(struct snd_tea575x *tea, struct module *owner); void snd_tea575x_exit(struct snd_tea575x *tea); void snd_tea575x_set_freq(struct snd_tea575x *tea); #endif /* __SOUND_TEA575X_TUNER_H */ PK ! ����9$ 9$ cx2341x.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* cx23415/6/8 header containing common defines. */ #ifndef CX2341X_H #define CX2341X_H #include <media/v4l2-ctrls.h> enum cx2341x_port { CX2341X_PORT_MEMORY = 0, CX2341X_PORT_STREAMING = 1, CX2341X_PORT_SERIAL = 2 }; enum cx2341x_cap { CX2341X_CAP_HAS_SLICED_VBI = 1 << 0, CX2341X_CAP_HAS_TS = 1 << 1, CX2341X_CAP_HAS_AC3 = 1 << 2, }; struct cx2341x_mpeg_params { /* misc */ u32 capabilities; enum cx2341x_port port; u16 width; u16 height; u16 is_50hz; /* stream */ enum v4l2_mpeg_stream_type stream_type; enum v4l2_mpeg_stream_vbi_fmt stream_vbi_fmt; u16 stream_insert_nav_packets; /* audio */ enum v4l2_mpeg_audio_sampling_freq audio_sampling_freq; enum v4l2_mpeg_audio_encoding audio_encoding; enum v4l2_mpeg_audio_l2_bitrate audio_l2_bitrate; enum v4l2_mpeg_audio_ac3_bitrate audio_ac3_bitrate; enum v4l2_mpeg_audio_mode audio_mode; enum v4l2_mpeg_audio_mode_extension audio_mode_extension; enum v4l2_mpeg_audio_emphasis audio_emphasis; enum v4l2_mpeg_audio_crc audio_crc; u32 audio_properties; u16 audio_mute; /* video */ enum v4l2_mpeg_video_encoding video_encoding; enum v4l2_mpeg_video_aspect video_aspect; u16 video_b_frames; u16 video_gop_size; u16 video_gop_closure; enum v4l2_mpeg_video_bitrate_mode video_bitrate_mode; u32 video_bitrate; u32 video_bitrate_peak; u16 video_temporal_decimation; u16 video_mute; u32 video_mute_yuv; /* encoding filters */ enum v4l2_mpeg_cx2341x_video_spatial_filter_mode video_spatial_filter_mode; u16 video_spatial_filter; enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type video_luma_spatial_filter_type; enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type video_chroma_spatial_filter_type; enum v4l2_mpeg_cx2341x_video_temporal_filter_mode video_temporal_filter_mode; u16 video_temporal_filter; enum v4l2_mpeg_cx2341x_video_median_filter_type video_median_filter_type; u16 video_luma_median_filter_top; u16 video_luma_median_filter_bottom; u16 video_chroma_median_filter_top; u16 video_chroma_median_filter_bottom; }; #define CX2341X_MBOX_MAX_DATA 16 extern const u32 cx2341x_mpeg_ctrls[]; typedef int (*cx2341x_mbox_func)(void *priv, u32 cmd, int in, int out, u32 data[CX2341X_MBOX_MAX_DATA]); int cx2341x_update(void *priv, cx2341x_mbox_func func, const struct cx2341x_mpeg_params *old, const struct cx2341x_mpeg_params *new); int cx2341x_ctrl_query(const struct cx2341x_mpeg_params *params, struct v4l2_queryctrl *qctrl); const char * const *cx2341x_ctrl_get_menu(const struct cx2341x_mpeg_params *p, u32 id); int cx2341x_ext_ctrls(struct cx2341x_mpeg_params *params, int busy, struct v4l2_ext_controls *ctrls, unsigned int cmd); void cx2341x_fill_defaults(struct cx2341x_mpeg_params *p); void cx2341x_log_status(const struct cx2341x_mpeg_params *p, const char *prefix); struct cx2341x_handler; struct cx2341x_handler_ops { /* needed for the video clock freq */ int (*s_audio_sampling_freq)(struct cx2341x_handler *hdl, u32 val); /* needed for dualwatch */ int (*s_audio_mode)(struct cx2341x_handler *hdl, u32 val); /* needed for setting up the video resolution */ int (*s_video_encoding)(struct cx2341x_handler *hdl, u32 val); /* needed for setting up the sliced vbi insertion data structures */ int (*s_stream_vbi_fmt)(struct cx2341x_handler *hdl, u32 val); }; struct cx2341x_handler { u32 capabilities; enum cx2341x_port port; u16 width; u16 height; u16 is_50hz; u32 audio_properties; struct v4l2_ctrl_handler hdl; void *priv; cx2341x_mbox_func func; const struct cx2341x_handler_ops *ops; struct v4l2_ctrl *stream_vbi_fmt; struct { /* audio cluster */ struct v4l2_ctrl *audio_sampling_freq; struct v4l2_ctrl *audio_encoding; struct v4l2_ctrl *audio_l2_bitrate; struct v4l2_ctrl *audio_mode; struct v4l2_ctrl *audio_mode_extension; struct v4l2_ctrl *audio_emphasis; struct v4l2_ctrl *audio_crc; struct v4l2_ctrl *audio_ac3_bitrate; }; struct { /* video gop cluster */ struct v4l2_ctrl *video_b_frames; struct v4l2_ctrl *video_gop_size; }; struct { /* stream type cluster */ struct v4l2_ctrl *stream_type; struct v4l2_ctrl *video_encoding; struct v4l2_ctrl *video_bitrate_mode; struct v4l2_ctrl *video_bitrate; struct v4l2_ctrl *video_bitrate_peak; }; struct { /* video mute cluster */ struct v4l2_ctrl *video_mute; struct v4l2_ctrl *video_mute_yuv; }; struct { /* video filter mode cluster */ struct v4l2_ctrl *video_spatial_filter_mode; struct v4l2_ctrl *video_temporal_filter_mode; struct v4l2_ctrl *video_median_filter_type; }; struct { /* video filter type cluster */ struct v4l2_ctrl *video_luma_spatial_filter_type; struct v4l2_ctrl *video_chroma_spatial_filter_type; }; struct { /* video filter cluster */ struct v4l2_ctrl *video_spatial_filter; struct v4l2_ctrl *video_temporal_filter; }; struct { /* video median cluster */ struct v4l2_ctrl *video_luma_median_filter_top; struct v4l2_ctrl *video_luma_median_filter_bottom; struct v4l2_ctrl *video_chroma_median_filter_top; struct v4l2_ctrl *video_chroma_median_filter_bottom; }; }; int cx2341x_handler_init(struct cx2341x_handler *cxhdl, unsigned nr_of_controls_hint); void cx2341x_handler_set_50hz(struct cx2341x_handler *cxhdl, int is_50hz); int cx2341x_handler_setup(struct cx2341x_handler *cxhdl); void cx2341x_handler_set_busy(struct cx2341x_handler *cxhdl, int busy); /* Firmware names */ #define CX2341X_FIRM_ENC_FILENAME "v4l-cx2341x-enc.fw" /* Decoder firmware for the cx23415 only */ #define CX2341X_FIRM_DEC_FILENAME "v4l-cx2341x-dec.fw" /* Firmware API commands */ /* MPEG decoder API, specific to the cx23415 */ #define CX2341X_DEC_PING_FW 0x00 #define CX2341X_DEC_START_PLAYBACK 0x01 #define CX2341X_DEC_STOP_PLAYBACK 0x02 #define CX2341X_DEC_SET_PLAYBACK_SPEED 0x03 #define CX2341X_DEC_STEP_VIDEO 0x05 #define CX2341X_DEC_SET_DMA_BLOCK_SIZE 0x08 #define CX2341X_DEC_GET_XFER_INFO 0x09 #define CX2341X_DEC_GET_DMA_STATUS 0x0a #define CX2341X_DEC_SCHED_DMA_FROM_HOST 0x0b #define CX2341X_DEC_PAUSE_PLAYBACK 0x0d #define CX2341X_DEC_HALT_FW 0x0e #define CX2341X_DEC_SET_STANDARD 0x10 #define CX2341X_DEC_GET_VERSION 0x11 #define CX2341X_DEC_SET_STREAM_INPUT 0x14 #define CX2341X_DEC_GET_TIMING_INFO 0x15 #define CX2341X_DEC_SET_AUDIO_MODE 0x16 #define CX2341X_DEC_SET_EVENT_NOTIFICATION 0x17 #define CX2341X_DEC_SET_DISPLAY_BUFFERS 0x18 #define CX2341X_DEC_EXTRACT_VBI 0x19 #define CX2341X_DEC_SET_DECODER_SOURCE 0x1a #define CX2341X_DEC_SET_PREBUFFERING 0x1e /* MPEG encoder API */ #define CX2341X_ENC_PING_FW 0x80 #define CX2341X_ENC_START_CAPTURE 0x81 #define CX2341X_ENC_STOP_CAPTURE 0x82 #define CX2341X_ENC_SET_AUDIO_ID 0x89 #define CX2341X_ENC_SET_VIDEO_ID 0x8b #define CX2341X_ENC_SET_PCR_ID 0x8d #define CX2341X_ENC_SET_FRAME_RATE 0x8f #define CX2341X_ENC_SET_FRAME_SIZE 0x91 #define CX2341X_ENC_SET_BIT_RATE 0x95 #define CX2341X_ENC_SET_GOP_PROPERTIES 0x97 #define CX2341X_ENC_SET_ASPECT_RATIO 0x99 #define CX2341X_ENC_SET_DNR_FILTER_MODE 0x9b #define CX2341X_ENC_SET_DNR_FILTER_PROPS 0x9d #define CX2341X_ENC_SET_CORING_LEVELS 0x9f #define CX2341X_ENC_SET_SPATIAL_FILTER_TYPE 0xa1 #define CX2341X_ENC_SET_VBI_LINE 0xb7 #define CX2341X_ENC_SET_STREAM_TYPE 0xb9 #define CX2341X_ENC_SET_OUTPUT_PORT 0xbb #define CX2341X_ENC_SET_AUDIO_PROPERTIES 0xbd #define CX2341X_ENC_HALT_FW 0xc3 #define CX2341X_ENC_GET_VERSION 0xc4 #define CX2341X_ENC_SET_GOP_CLOSURE 0xc5 #define CX2341X_ENC_GET_SEQ_END 0xc6 #define CX2341X_ENC_SET_PGM_INDEX_INFO 0xc7 #define CX2341X_ENC_SET_VBI_CONFIG 0xc8 #define CX2341X_ENC_SET_DMA_BLOCK_SIZE 0xc9 #define CX2341X_ENC_GET_PREV_DMA_INFO_MB_10 0xca #define CX2341X_ENC_GET_PREV_DMA_INFO_MB_9 0xcb #define CX2341X_ENC_SCHED_DMA_TO_HOST 0xcc #define CX2341X_ENC_INITIALIZE_INPUT 0xcd #define CX2341X_ENC_SET_FRAME_DROP_RATE 0xd0 #define CX2341X_ENC_PAUSE_ENCODER 0xd2 #define CX2341X_ENC_REFRESH_INPUT 0xd3 #define CX2341X_ENC_SET_COPYRIGHT 0xd4 #define CX2341X_ENC_SET_EVENT_NOTIFICATION 0xd5 #define CX2341X_ENC_SET_NUM_VSYNC_LINES 0xd6 #define CX2341X_ENC_SET_PLACEHOLDER 0xd7 #define CX2341X_ENC_MUTE_VIDEO 0xd9 #define CX2341X_ENC_MUTE_AUDIO 0xda #define CX2341X_ENC_SET_VERT_CROP_LINE 0xdb #define CX2341X_ENC_MISC 0xdc /* OSD API, specific to the cx23415 */ #define CX2341X_OSD_GET_FRAMEBUFFER 0x41 #define CX2341X_OSD_GET_PIXEL_FORMAT 0x42 #define CX2341X_OSD_SET_PIXEL_FORMAT 0x43 #define CX2341X_OSD_GET_STATE 0x44 #define CX2341X_OSD_SET_STATE 0x45 #define CX2341X_OSD_GET_OSD_COORDS 0x46 #define CX2341X_OSD_SET_OSD_COORDS 0x47 #define CX2341X_OSD_GET_SCREEN_COORDS 0x48 #define CX2341X_OSD_SET_SCREEN_COORDS 0x49 #define CX2341X_OSD_GET_GLOBAL_ALPHA 0x4a #define CX2341X_OSD_SET_GLOBAL_ALPHA 0x4b #define CX2341X_OSD_SET_BLEND_COORDS 0x4c #define CX2341X_OSD_GET_FLICKER_STATE 0x4f #define CX2341X_OSD_SET_FLICKER_STATE 0x50 #define CX2341X_OSD_BLT_COPY 0x52 #define CX2341X_OSD_BLT_FILL 0x53 #define CX2341X_OSD_BLT_TEXT 0x54 #define CX2341X_OSD_SET_FRAMEBUFFER_WINDOW 0x56 #define CX2341X_OSD_SET_CHROMA_KEY 0x60 #define CX2341X_OSD_GET_ALPHA_CONTENT_INDEX 0x61 #define CX2341X_OSD_SET_ALPHA_CONTENT_INDEX 0x62 #endif /* CX2341X_H */ PK ! ���s? ? saa7146_vv.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __SAA7146_VV__ #define __SAA7146_VV__ #include <media/v4l2-common.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-fh.h> #include <media/drv-intf/saa7146.h> #include <media/videobuf-dma-sg.h> #define MAX_SAA7146_CAPTURE_BUFFERS 32 /* arbitrary */ #define BUFFER_TIMEOUT (HZ/2) /* 0.5 seconds */ #define WRITE_RPS0(x) do { \ dev->d_rps0.cpu_addr[ count++ ] = cpu_to_le32(x); \ } while (0); #define WRITE_RPS1(x) do { \ dev->d_rps1.cpu_addr[ count++ ] = cpu_to_le32(x); \ } while (0); struct saa7146_video_dma { u32 base_odd; u32 base_even; u32 prot_addr; u32 pitch; u32 base_page; u32 num_line_byte; }; #define FORMAT_BYTE_SWAP 0x1 #define FORMAT_IS_PLANAR 0x2 struct saa7146_format { u32 pixelformat; u32 trans; u8 depth; u8 flags; u8 swap; }; struct saa7146_standard { char *name; v4l2_std_id id; int v_offset; /* number of lines of vertical offset before processing */ int v_field; /* number of lines in a field for HPS to process */ int h_offset; /* horizontal offset of processing window */ int h_pixels; /* number of horizontal pixels to process */ int v_max_out; int h_max_out; }; /* buffer for one video/vbi frame */ struct saa7146_buf { /* common v4l buffer stuff -- must be first */ struct videobuf_buffer vb; /* saa7146 specific */ struct v4l2_pix_format *fmt; int (*activate)(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next); /* page tables */ struct saa7146_pgtable pt[3]; }; struct saa7146_dmaqueue { struct saa7146_dev *dev; struct saa7146_buf *curr; struct list_head queue; struct timer_list timeout; }; struct saa7146_overlay { struct saa7146_fh *fh; struct v4l2_window win; struct v4l2_clip clips[16]; int nclips; }; /* per open data */ struct saa7146_fh { /* Must be the first field! */ struct v4l2_fh fh; struct saa7146_dev *dev; /* video capture */ struct videobuf_queue video_q; /* vbi capture */ struct videobuf_queue vbi_q; unsigned int resources; /* resource management for device open */ }; #define STATUS_OVERLAY 0x01 #define STATUS_CAPTURE 0x02 struct saa7146_vv { /* vbi capture */ struct saa7146_dmaqueue vbi_dmaq; struct v4l2_vbi_format vbi_fmt; struct timer_list vbi_read_timeout; struct file *vbi_read_timeout_file; /* vbi workaround interrupt queue */ wait_queue_head_t vbi_wq; int vbi_fieldcount; struct saa7146_fh *vbi_streaming; int video_status; struct saa7146_fh *video_fh; /* video overlay */ struct saa7146_overlay ov; struct v4l2_framebuffer ov_fb; struct saa7146_format *ov_fmt; struct saa7146_fh *ov_suspend; /* video capture */ struct saa7146_dmaqueue video_dmaq; struct v4l2_pix_format video_fmt; enum v4l2_field last_field; /* common: fixme? shouldn't this be in saa7146_fh? (this leads to a more complicated question: shall the driver store the different settings (for example S_INPUT) for every open and restore it appropriately, or should all settings be common for all opens? currently, we do the latter, like all other drivers do... */ struct saa7146_standard *standard; int vflip; int hflip; int current_hps_source; int current_hps_sync; struct saa7146_dma d_clipping; /* pointer to clipping memory */ unsigned int resources; /* resource management for device */ }; /* flags */ #define SAA7146_USE_PORT_B_FOR_VBI 0x2 /* use input port b for vbi hardware bug workaround */ struct saa7146_ext_vv { /* information about the video capabilities of the device */ int inputs; int audios; u32 capabilities; int flags; /* additionally supported transmission standards */ struct saa7146_standard *stds; int num_stds; int (*std_callback)(struct saa7146_dev*, struct saa7146_standard *); /* the extension can override this */ struct v4l2_ioctl_ops vid_ops; struct v4l2_ioctl_ops vbi_ops; /* pointer to the saa7146 core ops */ const struct v4l2_ioctl_ops *core_ops; struct v4l2_file_operations vbi_fops; }; struct saa7146_use_ops { void (*init)(struct saa7146_dev *, struct saa7146_vv *); int(*open)(struct saa7146_dev *, struct file *); void (*release)(struct saa7146_dev *, struct file *); void (*irq_done)(struct saa7146_dev *, unsigned long status); ssize_t (*read)(struct file *, char __user *, size_t, loff_t *); }; /* from saa7146_fops.c */ int saa7146_register_device(struct video_device *vid, struct saa7146_dev *dev, char *name, int type); int saa7146_unregister_device(struct video_device *vid, struct saa7146_dev *dev); void saa7146_buffer_finish(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, int state); void saa7146_buffer_next(struct saa7146_dev *dev, struct saa7146_dmaqueue *q,int vbi); int saa7146_buffer_queue(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, struct saa7146_buf *buf); void saa7146_buffer_timeout(struct timer_list *t); void saa7146_dma_free(struct saa7146_dev* dev,struct videobuf_queue *q, struct saa7146_buf *buf); int saa7146_vv_init(struct saa7146_dev* dev, struct saa7146_ext_vv *ext_vv); int saa7146_vv_release(struct saa7146_dev* dev); /* from saa7146_hlp.c */ int saa7146_enable_overlay(struct saa7146_fh *fh); void saa7146_disable_overlay(struct saa7146_fh *fh); void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next); void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma) ; void saa7146_set_hps_source_and_sync(struct saa7146_dev *saa, int source, int sync); void saa7146_set_gpio(struct saa7146_dev *saa, u8 pin, u8 data); /* from saa7146_video.c */ extern const struct v4l2_ioctl_ops saa7146_video_ioctl_ops; extern const struct v4l2_ioctl_ops saa7146_vbi_ioctl_ops; extern const struct saa7146_use_ops saa7146_video_uops; int saa7146_start_preview(struct saa7146_fh *fh); int saa7146_stop_preview(struct saa7146_fh *fh); long saa7146_video_do_ioctl(struct file *file, unsigned int cmd, void *arg); int saa7146_s_ctrl(struct v4l2_ctrl *ctrl); /* from saa7146_vbi.c */ extern const struct saa7146_use_ops saa7146_vbi_uops; /* resource management functions */ int saa7146_res_get(struct saa7146_fh *fh, unsigned int bit); void saa7146_res_free(struct saa7146_fh *fh, unsigned int bits); #define RESOURCE_DMA1_HPS 0x1 #define RESOURCE_DMA2_CLP 0x2 #define RESOURCE_DMA3_BRS 0x4 /* saa7146 source inputs */ #define SAA7146_HPS_SOURCE_PORT_A 0x00 #define SAA7146_HPS_SOURCE_PORT_B 0x01 #define SAA7146_HPS_SOURCE_YPB_CPA 0x02 #define SAA7146_HPS_SOURCE_YPA_CPB 0x03 /* sync inputs */ #define SAA7146_HPS_SYNC_PORT_A 0x00 #define SAA7146_HPS_SYNC_PORT_B 0x01 /* some memory sizes */ /* max. 16 clipping rectangles */ #define SAA7146_CLIPPING_MEM (16 * 4 * sizeof(u32)) /* some defines for the various clipping-modes */ #define SAA7146_CLIPPING_RECT 0x4 #define SAA7146_CLIPPING_RECT_INVERTED 0x5 #define SAA7146_CLIPPING_MASK 0x6 #define SAA7146_CLIPPING_MASK_INVERTED 0x7 /* output formats: each entry holds four information */ #define RGB08_COMPOSED 0x0217 /* composed is used in the sense of "not-planar" */ /* this means: planar?=0, yuv2rgb-conversation-mode=2, dither=yes(=1), format-mode = 7 */ #define RGB15_COMPOSED 0x0213 #define RGB16_COMPOSED 0x0210 #define RGB24_COMPOSED 0x0201 #define RGB32_COMPOSED 0x0202 #define Y8 0x0006 #define YUV411_COMPOSED 0x0003 #define YUV422_COMPOSED 0x0000 /* this means: planar?=1, yuv2rgb-conversion-mode=0, dither=no(=0), format-mode = b */ #define YUV411_DECOMPOSED 0x100b #define YUV422_DECOMPOSED 0x1009 #define YUV420_DECOMPOSED 0x100a #define IS_PLANAR(x) (x & 0xf000) /* misc defines */ #define SAA7146_NO_SWAP (0x0) #define SAA7146_TWO_BYTE_SWAP (0x1) #define SAA7146_FOUR_BYTE_SWAP (0x2) #endif PK ! �D��K K renesas-ceu.hnu �[��� // SPDX-License-Identifier: GPL-2.0 /* * renesas-ceu.h - Renesas CEU driver interface * * Copyright 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org> */ #ifndef __MEDIA_DRV_INTF_RENESAS_CEU_H__ #define __MEDIA_DRV_INTF_RENESAS_CEU_H__ #define CEU_MAX_SUBDEVS 2 struct ceu_async_subdev { unsigned long flags; unsigned char bus_width; unsigned char bus_shift; unsigned int i2c_adapter_id; unsigned int i2c_address; }; struct ceu_platform_data { unsigned int num_subdevs; struct ceu_async_subdev subdevs[CEU_MAX_SUBDEVS]; }; #endif /* ___MEDIA_DRV_INTF_RENESAS_CEU_H__ */ PK ! _��d d msp3400.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* msp3400.h - definition for msp3400 inputs and outputs Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) */ #ifndef _MSP3400_H_ #define _MSP3400_H_ /* msp3400 routing =============== The msp3400 has a complicated routing scheme with many possible combinations. The details are all in the datasheets but I will try to give a short description here. Inputs ====== There are 1) tuner inputs, 2) I2S inputs, 3) SCART inputs. You will have to select which tuner input to use and which SCART input to use. The selected tuner input, the selected SCART input and all I2S inputs go to the DSP (the tuner input first goes through the demodulator). The DSP handles things like volume, bass/treble, balance, and some chips have support for surround sound. It has several outputs: MAIN, AUX, I2S and SCART1/2. Each output can select which DSP input to use. So the MAIN output can select the tuner input while at the same time the SCART1 output uses the I2S input. Outputs ======= Most DSP outputs are also the outputs of the msp3400. However, the SCART outputs of the msp3400 can select which input to use: either the SCART1 or SCART2 output from the DSP, or the msp3400 SCART inputs, thus completely bypassing the DSP. Summary ======= So to specify a complete routing scheme for the msp3400 you will have to specify in the 'input' arg of the s_routing function: 1) which tuner input to use 2) which SCART input to use 3) which DSP input to use for each DSP output And in the 'output' arg of the s_routing function you specify: 1) which SCART input to use for each SCART output Depending on how the msp is wired to the other components you can ignore or mute certain inputs or outputs. Also, depending on the msp version only a subset of the inputs or outputs may be present. At the end of this header some tables are added containing a list of what is available for each msp version. */ /* Inputs to the DSP unit: two independent selections have to be made: 1) the tuner (SIF) input 2) the SCART input Bits 0-2 are used for the SCART input select, bit 3 is used for the tuner input, bits 4-7 are reserved. */ /* SCART input to DSP selection */ #define MSP_IN_SCART1 0 /* Pin SC1_IN */ #define MSP_IN_SCART2 1 /* Pin SC2_IN */ #define MSP_IN_SCART3 2 /* Pin SC3_IN */ #define MSP_IN_SCART4 3 /* Pin SC4_IN */ #define MSP_IN_MONO 6 /* Pin MONO_IN */ #define MSP_IN_MUTE 7 /* Mute DSP input */ #define MSP_SCART_TO_DSP(in) (in) /* Tuner input to demodulator and DSP selection */ #define MSP_IN_TUNER1 0 /* Analog Sound IF input pin ANA_IN1 */ #define MSP_IN_TUNER2 1 /* Analog Sound IF input pin ANA_IN2 */ #define MSP_TUNER_TO_DSP(in) ((in) << 3) /* The msp has up to 5 DSP outputs, each output can independently select a DSP input. The DSP outputs are: loudspeaker output (aka MAIN), headphones output (aka AUX), SCART1 DA output, SCART2 DA output and an I2S output. There also is a quasi-peak detector output, but that is not used by this driver and is set to the same input as the loudspeaker output. Not all outputs are supported by all msp models. Setting the input of an unsupported output will be ignored by the driver. There are up to 16 DSP inputs to choose from, so each output is assigned 4 bits. Note: the 44x8G can mix two inputs and feed the result back to the DSP. This is currently not implemented. Also not implemented is the multi-channel capable I2S3 input of the 44x0G. If someone can demonstrate a need for one of those features then additional support can be added. */ #define MSP_DSP_IN_TUNER 0 /* Tuner DSP input */ #define MSP_DSP_IN_SCART 2 /* SCART DSP input */ #define MSP_DSP_IN_I2S1 5 /* I2S1 DSP input */ #define MSP_DSP_IN_I2S2 6 /* I2S2 DSP input */ #define MSP_DSP_IN_I2S3 7 /* I2S3 DSP input */ #define MSP_DSP_IN_MAIN_AVC 11 /* MAIN AVC processed DSP input */ #define MSP_DSP_IN_MAIN 12 /* MAIN DSP input */ #define MSP_DSP_IN_AUX 13 /* AUX DSP input */ #define MSP_DSP_TO_MAIN(in) ((in) << 4) #define MSP_DSP_TO_AUX(in) ((in) << 8) #define MSP_DSP_TO_SCART1(in) ((in) << 12) #define MSP_DSP_TO_SCART2(in) ((in) << 16) #define MSP_DSP_TO_I2S(in) ((in) << 20) /* Output SCART select: the SCART outputs can select which input to use. */ #define MSP_SC_IN_SCART1 0 /* SCART1 input, bypassing the DSP */ #define MSP_SC_IN_SCART2 1 /* SCART2 input, bypassing the DSP */ #define MSP_SC_IN_SCART3 2 /* SCART3 input, bypassing the DSP */ #define MSP_SC_IN_SCART4 3 /* SCART4 input, bypassing the DSP */ #define MSP_SC_IN_DSP_SCART1 4 /* DSP SCART1 input */ #define MSP_SC_IN_DSP_SCART2 5 /* DSP SCART2 input */ #define MSP_SC_IN_MONO 6 /* MONO input, bypassing the DSP */ #define MSP_SC_IN_MUTE 7 /* MUTE output */ #define MSP_SC_TO_SCART1(in) (in) #define MSP_SC_TO_SCART2(in) ((in) << 4) /* Shortcut macros */ #define MSP_INPUT(sc, t, main_aux_src, sc_i2s_src) \ (MSP_SCART_TO_DSP(sc) | \ MSP_TUNER_TO_DSP(t) | \ MSP_DSP_TO_MAIN(main_aux_src) | \ MSP_DSP_TO_AUX(main_aux_src) | \ MSP_DSP_TO_SCART1(sc_i2s_src) | \ MSP_DSP_TO_SCART2(sc_i2s_src) | \ MSP_DSP_TO_I2S(sc_i2s_src)) #define MSP_INPUT_DEFAULT MSP_INPUT(MSP_IN_SCART1, MSP_IN_TUNER1, \ MSP_DSP_IN_TUNER, MSP_DSP_IN_TUNER) #define MSP_OUTPUT(sc) \ (MSP_SC_TO_SCART1(sc) | \ MSP_SC_TO_SCART2(sc)) /* This equals the RESET position of the msp3400 ACB register */ #define MSP_OUTPUT_DEFAULT (MSP_SC_TO_SCART1(MSP_SC_IN_SCART3) | \ MSP_SC_TO_SCART2(MSP_SC_IN_DSP_SCART1)) /* Tuner inputs vs. msp version */ /* Chip TUNER_1 TUNER_2 ------------------------- msp34x0b y y msp34x0c y y msp34x0d y y msp34x5d y n msp34x7d y n msp34x0g y y msp34x1g y y msp34x2g y y msp34x5g y n msp34x7g y n msp44x0g y y msp44x8g y y */ /* SCART inputs vs. msp version */ /* Chip SC1 SC2 SC3 SC4 ------------------------- msp34x0b y y y n msp34x0c y y y n msp34x0d y y y y msp34x5d y y n n msp34x7d y n n n msp34x0g y y y y msp34x1g y y y y msp34x2g y y y y msp34x5g y y n n msp34x7g y n n n msp44x0g y y y y msp44x8g y y y y */ /* DSP inputs vs. msp version (tuner and SCART inputs are always available) */ /* Chip I2S1 I2S2 I2S3 MAIN_AVC MAIN AUX ------------------------------------------ msp34x0b y n n n n n msp34x0c y y n n n n msp34x0d y y n n n n msp34x5d y y n n n n msp34x7d n n n n n n msp34x0g y y n n n n msp34x1g y y n n n n msp34x2g y y n y y y msp34x5g y y n n n n msp34x7g n n n n n n msp44x0g y y y y y y msp44x8g y y y n n n */ /* DSP outputs vs. msp version */ /* Chip MAIN AUX SCART1 SCART2 I2S ------------------------------------ msp34x0b y y y n y msp34x0c y y y n y msp34x0d y y y y y msp34x5d y n y n y msp34x7d y n y n n msp34x0g y y y y y msp34x1g y y y y y msp34x2g y y y y y msp34x5g y n y n y msp34x7g y n y n n msp44x0g y y y y y msp44x8g y y y y y */ #endif /* MSP3400_H */ PK ! ʞ -*F *F saa7146.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __SAA7146__ #define __SAA7146__ #include <linux/delay.h> /* for delay-stuff */ #include <linux/slab.h> /* for kmalloc/kfree */ #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */ #include <linux/init.h> /* for "__init" */ #include <linux/interrupt.h> /* for IMMEDIATE_BH */ #include <linux/kmod.h> /* for kernel module loader */ #include <linux/i2c.h> /* for i2c subsystem */ #include <asm/io.h> /* for accessing devices */ #include <linux/stringify.h> #include <linux/mutex.h> #include <linux/scatterlist.h> #include <media/v4l2-device.h> #include <media/v4l2-ctrls.h> #include <linux/vmalloc.h> /* for vmalloc() */ #include <linux/mm.h> /* for vmalloc_to_page() */ #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr))) #define saa7146_read(sxy,adr) readl(sxy->mem+(adr)) extern unsigned int saa7146_debug; #ifndef DEBUG_VARIABLE #define DEBUG_VARIABLE saa7146_debug #endif #define ERR(fmt, ...) pr_err("%s: " fmt, __func__, ##__VA_ARGS__) #define _DBG(mask, fmt, ...) \ do { \ if (DEBUG_VARIABLE & mask) \ pr_debug("%s(): " fmt, __func__, ##__VA_ARGS__); \ } while (0) /* simple debug messages */ #define DEB_S(fmt, ...) _DBG(0x01, fmt, ##__VA_ARGS__) /* more detailed debug messages */ #define DEB_D(fmt, ...) _DBG(0x02, fmt, ##__VA_ARGS__) /* print enter and exit of functions */ #define DEB_EE(fmt, ...) _DBG(0x04, fmt, ##__VA_ARGS__) /* i2c debug messages */ #define DEB_I2C(fmt, ...) _DBG(0x08, fmt, ##__VA_ARGS__) /* vbi debug messages */ #define DEB_VBI(fmt, ...) _DBG(0x10, fmt, ##__VA_ARGS__) /* interrupt debug messages */ #define DEB_INT(fmt, ...) _DBG(0x20, fmt, ##__VA_ARGS__) /* capture debug messages */ #define DEB_CAP(fmt, ...) _DBG(0x40, fmt, ##__VA_ARGS__) #define SAA7146_ISR_CLEAR(x,y) \ saa7146_write(x, ISR, (y)); struct module; struct saa7146_dev; struct saa7146_extension; struct saa7146_vv; /* saa7146 page table */ struct saa7146_pgtable { unsigned int size; __le32 *cpu; dma_addr_t dma; /* used for offsets for u,v planes for planar capture modes */ unsigned long offset; /* used for custom pagetables (used for example by budget dvb cards) */ struct scatterlist *slist; int nents; }; struct saa7146_pci_extension_data { struct saa7146_extension *ext; void *ext_priv; /* most likely a name string */ }; #define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \ { \ .vendor = PCI_VENDOR_ID_PHILIPS, \ .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \ .subvendor = x_vendor, \ .subdevice = x_device, \ .driver_data = (unsigned long)& x_var, \ } struct saa7146_extension { char name[32]; /* name of the device */ #define SAA7146_USE_I2C_IRQ 0x1 #define SAA7146_I2C_SHORT_DELAY 0x2 int flags; /* pairs of subvendor and subdevice ids for supported devices, last entry 0xffff, 0xfff */ struct module *module; struct pci_driver driver; const struct pci_device_id *pci_tbl; /* extension functions */ int (*probe)(struct saa7146_dev *); int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *); int (*detach)(struct saa7146_dev*); u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */ void (*irq_func)(struct saa7146_dev*, u32* irq_mask); }; struct saa7146_dma { dma_addr_t dma_handle; __le32 *cpu_addr; }; struct saa7146_dev { struct module *module; struct v4l2_device v4l2_dev; struct v4l2_ctrl_handler ctrl_handler; /* different device locks */ spinlock_t slock; struct mutex v4l2_lock; unsigned char __iomem *mem; /* pointer to mapped IO memory */ u32 revision; /* chip revision; needed for bug-workarounds*/ /* pci-device & irq stuff*/ char name[32]; struct pci_dev *pci; u32 int_todo; spinlock_t int_slock; /* extension handling */ struct saa7146_extension *ext; /* indicates if handled by extension */ void *ext_priv; /* pointer for extension private use (most likely some private data) */ struct saa7146_ext_vv *ext_vv_data; /* per device video/vbi information (if available) */ struct saa7146_vv *vv_data; void (*vv_callback)(struct saa7146_dev *dev, unsigned long status); /* i2c-stuff */ struct mutex i2c_lock; u32 i2c_bitrate; struct saa7146_dma d_i2c; /* pointer to i2c memory */ wait_queue_head_t i2c_wq; int i2c_op; /* memories */ struct saa7146_dma d_rps0; struct saa7146_dma d_rps1; }; static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev) { return container_of(v4l2_dev, struct saa7146_dev, v4l2_dev); } /* from saa7146_i2c.c */ int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); /* from saa7146_core.c */ int saa7146_register_extension(struct saa7146_extension*); int saa7146_unregister_extension(struct saa7146_extension*); struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc); int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt); void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); /* some memory sizes */ #define SAA7146_I2C_MEM ( 1*PAGE_SIZE) #define SAA7146_RPS_MEM ( 1*PAGE_SIZE) /* some i2c constants */ #define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */ #define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */ #define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */ /* unsorted defines */ #define ME1 0x0000000800 #define PV1 0x0000000008 /* gpio defines */ #define SAA7146_GPIO_INPUT 0x00 #define SAA7146_GPIO_IRQHI 0x10 #define SAA7146_GPIO_IRQLO 0x20 #define SAA7146_GPIO_IRQHL 0x30 #define SAA7146_GPIO_OUTLO 0x40 #define SAA7146_GPIO_OUTHI 0x50 /* debi defines */ #define DEBINOSWAP 0x000e0000 /* define for the register programming sequencer (rps) */ #define CMD_NOP 0x00000000 /* No operation */ #define CMD_CLR_EVENT 0x00000000 /* Clear event */ #define CMD_SET_EVENT 0x10000000 /* Set signal event */ #define CMD_PAUSE 0x20000000 /* Pause */ #define CMD_CHECK_LATE 0x30000000 /* Check late */ #define CMD_UPLOAD 0x40000000 /* Upload */ #define CMD_STOP 0x50000000 /* Stop */ #define CMD_INTERRUPT 0x60000000 /* Interrupt */ #define CMD_JUMP 0x80000000 /* Jump */ #define CMD_WR_REG 0x90000000 /* Write (load) register */ #define CMD_RD_REG 0xa0000000 /* Read (store) register */ #define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */ #define CMD_OAN MASK_27 #define CMD_INV MASK_26 #define CMD_SIG4 MASK_25 #define CMD_SIG3 MASK_24 #define CMD_SIG2 MASK_23 #define CMD_SIG1 MASK_22 #define CMD_SIG0 MASK_21 #define CMD_O_FID_B MASK_14 #define CMD_E_FID_B MASK_13 #define CMD_O_FID_A MASK_12 #define CMD_E_FID_A MASK_11 /* some events and command modifiers for rps1 squarewave generator */ #define EVT_HS (1<<15) // Source Line Threshold reached #define EVT_VBI_B (1<<9) // VSYNC Event #define RPS_OAN (1<<27) // 1: OR events, 0: AND events #define RPS_INV (1<<26) // Invert (compound) event #define GPIO3_MSK 0xFF000000 // GPIO #3 control bits /* Bit mask constants */ #define MASK_00 0x00000001 /* Mask value for bit 0 */ #define MASK_01 0x00000002 /* Mask value for bit 1 */ #define MASK_02 0x00000004 /* Mask value for bit 2 */ #define MASK_03 0x00000008 /* Mask value for bit 3 */ #define MASK_04 0x00000010 /* Mask value for bit 4 */ #define MASK_05 0x00000020 /* Mask value for bit 5 */ #define MASK_06 0x00000040 /* Mask value for bit 6 */ #define MASK_07 0x00000080 /* Mask value for bit 7 */ #define MASK_08 0x00000100 /* Mask value for bit 8 */ #define MASK_09 0x00000200 /* Mask value for bit 9 */ #define MASK_10 0x00000400 /* Mask value for bit 10 */ #define MASK_11 0x00000800 /* Mask value for bit 11 */ #define MASK_12 0x00001000 /* Mask value for bit 12 */ #define MASK_13 0x00002000 /* Mask value for bit 13 */ #define MASK_14 0x00004000 /* Mask value for bit 14 */ #define MASK_15 0x00008000 /* Mask value for bit 15 */ #define MASK_16 0x00010000 /* Mask value for bit 16 */ #define MASK_17 0x00020000 /* Mask value for bit 17 */ #define MASK_18 0x00040000 /* Mask value for bit 18 */ #define MASK_19 0x00080000 /* Mask value for bit 19 */ #define MASK_20 0x00100000 /* Mask value for bit 20 */ #define MASK_21 0x00200000 /* Mask value for bit 21 */ #define MASK_22 0x00400000 /* Mask value for bit 22 */ #define MASK_23 0x00800000 /* Mask value for bit 23 */ #define MASK_24 0x01000000 /* Mask value for bit 24 */ #define MASK_25 0x02000000 /* Mask value for bit 25 */ #define MASK_26 0x04000000 /* Mask value for bit 26 */ #define MASK_27 0x08000000 /* Mask value for bit 27 */ #define MASK_28 0x10000000 /* Mask value for bit 28 */ #define MASK_29 0x20000000 /* Mask value for bit 29 */ #define MASK_30 0x40000000 /* Mask value for bit 30 */ #define MASK_31 0x80000000 /* Mask value for bit 31 */ #define MASK_B0 0x000000ff /* Mask value for byte 0 */ #define MASK_B1 0x0000ff00 /* Mask value for byte 1 */ #define MASK_B2 0x00ff0000 /* Mask value for byte 2 */ #define MASK_B3 0xff000000 /* Mask value for byte 3 */ #define MASK_W0 0x0000ffff /* Mask value for word 0 */ #define MASK_W1 0xffff0000 /* Mask value for word 1 */ #define MASK_PA 0xfffffffc /* Mask value for physical address */ #define MASK_PR 0xfffffffe /* Mask value for protection register */ #define MASK_ER 0xffffffff /* Mask value for the entire register */ #define MASK_NONE 0x00000000 /* No mask */ /* register aliases */ #define BASE_ODD1 0x00 /* Video DMA 1 registers */ #define BASE_EVEN1 0x04 #define PROT_ADDR1 0x08 #define PITCH1 0x0C #define BASE_PAGE1 0x10 /* Video DMA 1 base page */ #define NUM_LINE_BYTE1 0x14 #define BASE_ODD2 0x18 /* Video DMA 2 registers */ #define BASE_EVEN2 0x1C #define PROT_ADDR2 0x20 #define PITCH2 0x24 #define BASE_PAGE2 0x28 /* Video DMA 2 base page */ #define NUM_LINE_BYTE2 0x2C #define BASE_ODD3 0x30 /* Video DMA 3 registers */ #define BASE_EVEN3 0x34 #define PROT_ADDR3 0x38 #define PITCH3 0x3C #define BASE_PAGE3 0x40 /* Video DMA 3 base page */ #define NUM_LINE_BYTE3 0x44 #define PCI_BT_V1 0x48 /* Video/FIFO 1 */ #define PCI_BT_V2 0x49 /* Video/FIFO 2 */ #define PCI_BT_V3 0x4A /* Video/FIFO 3 */ #define PCI_BT_DEBI 0x4B /* DEBI */ #define PCI_BT_A 0x4C /* Audio */ #define DD1_INIT 0x50 /* Init setting of DD1 interface */ #define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */ #define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */ #define BRS_CTRL 0x58 /* BRS control register */ #define HPS_CTRL 0x5C /* HPS control register */ #define HPS_V_SCALE 0x60 /* HPS vertical scale */ #define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */ #define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */ #define HPS_H_SCALE 0x6C /* HPS horizontal scale */ #define BCS_CTRL 0x70 /* BCS control */ #define CHROMA_KEY_RANGE 0x74 #define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */ #define DEBI_CONFIG 0x7C #define DEBI_COMMAND 0x80 #define DEBI_PAGE 0x84 #define DEBI_AD 0x88 #define I2C_TRANSFER 0x8C #define I2C_STATUS 0x90 #define BASE_A1_IN 0x94 /* Audio 1 input DMA */ #define PROT_A1_IN 0x98 #define PAGE_A1_IN 0x9C #define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */ #define PROT_A1_OUT 0xA4 #define PAGE_A1_OUT 0xA8 #define BASE_A2_IN 0xAC /* Audio 2 input DMA */ #define PROT_A2_IN 0xB0 #define PAGE_A2_IN 0xB4 #define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */ #define PROT_A2_OUT 0xBC #define PAGE_A2_OUT 0xC0 #define RPS_PAGE0 0xC4 /* RPS task 0 page register */ #define RPS_PAGE1 0xC8 /* RPS task 1 page register */ #define RPS_THRESH0 0xCC /* HBI threshold for task 0 */ #define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */ #define RPS_TOV0 0xD4 /* RPS timeout for task 0 */ #define RPS_TOV1 0xD8 /* RPS timeout for task 1 */ #define IER 0xDC /* Interrupt enable register */ #define GPIO_CTRL 0xE0 /* GPIO 0-3 register */ #define EC1SSR 0xE4 /* Event cnt set 1 source select */ #define EC2SSR 0xE8 /* Event cnt set 2 source select */ #define ECT1R 0xEC /* Event cnt set 1 thresholds */ #define ECT2R 0xF0 /* Event cnt set 2 thresholds */ #define ACON1 0xF4 #define ACON2 0xF8 #define MC1 0xFC /* Main control register 1 */ #define MC2 0x100 /* Main control register 2 */ #define RPS_ADDR0 0x104 /* RPS task 0 address register */ #define RPS_ADDR1 0x108 /* RPS task 1 address register */ #define ISR 0x10C /* Interrupt status register */ #define PSR 0x110 /* Primary status register */ #define SSR 0x114 /* Secondary status register */ #define EC1R 0x118 /* Event counter set 1 register */ #define EC2R 0x11C /* Event counter set 2 register */ #define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */ #define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */ #define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */ #define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */ #define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */ #define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */ #define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */ #define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */ #define LEVEL_REP 0x140, #define A_TIME_SLOT1 0x180, /* from 180 - 1BC */ #define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */ /* isr masks */ #define SPCI_PPEF 0x80000000 /* PCI parity error */ #define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */ #define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */ #define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */ #define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */ #define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */ #define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */ #define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */ #define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */ #define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */ #define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */ #define SPCI_UPLD 0x00100000 /* RPS in upload */ #define SPCI_DEBI_S 0x00080000 /* DEBI status */ #define SPCI_DEBI_E 0x00040000 /* DEBI error */ #define SPCI_IIC_S 0x00020000 /* I2C status */ #define SPCI_IIC_E 0x00010000 /* I2C error */ #define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */ #define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */ #define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */ #define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */ #define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */ #define SPCI_V_PE 0x00000400 /* Video protection address */ #define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */ #define SPCI_FIDA 0x00000100 /* Field ID video port A */ #define SPCI_FIDB 0x00000080 /* Field ID video port B */ #define SPCI_PIN3 0x00000040 /* GPIO pin 3 */ #define SPCI_PIN2 0x00000020 /* GPIO pin 2 */ #define SPCI_PIN1 0x00000010 /* GPIO pin 1 */ #define SPCI_PIN0 0x00000008 /* GPIO pin 0 */ #define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */ #define SPCI_EC3S 0x00000002 /* Event counter 3 */ #define SPCI_EC0S 0x00000001 /* Event counter 0 */ /* i2c */ #define SAA7146_I2C_ABORT (1<<7) #define SAA7146_I2C_SPERR (1<<6) #define SAA7146_I2C_APERR (1<<5) #define SAA7146_I2C_DTERR (1<<4) #define SAA7146_I2C_DRERR (1<<3) #define SAA7146_I2C_AL (1<<2) #define SAA7146_I2C_ERR (1<<1) #define SAA7146_I2C_BUSY (1<<0) #define SAA7146_I2C_START (0x3) #define SAA7146_I2C_CONT (0x2) #define SAA7146_I2C_STOP (0x1) #define SAA7146_I2C_NOP (0x0) #define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500) #define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100) #define SAA7146_I2C_BUS_BIT_RATE_480 (0x400) #define SAA7146_I2C_BUS_BIT_RATE_320 (0x600) #define SAA7146_I2C_BUS_BIT_RATE_240 (0x700) #define SAA7146_I2C_BUS_BIT_RATE_120 (0x000) #define SAA7146_I2C_BUS_BIT_RATE_80 (0x200) #define SAA7146_I2C_BUS_BIT_RATE_60 (0x300) static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y) { unsigned long flags; spin_lock_irqsave(&x->int_slock, flags); saa7146_write(x, IER, saa7146_read(x, IER) & ~y); spin_unlock_irqrestore(&x->int_slock, flags); } static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y) { unsigned long flags; spin_lock_irqsave(&x->int_slock, flags); saa7146_write(x, IER, saa7146_read(x, IER) | y); spin_unlock_irqrestore(&x->int_slock, flags); } #endif PK ! HMZ�Y Y si476x.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * include/media/drv-intf/si476x.h -- Common definitions for si476x driver * * Copyright (C) 2012 Innovative Converged Devices(ICD) * Copyright (C) 2013 Andrey Smirnov * * Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #ifndef SI476X_H #define SI476X_H #include <linux/types.h> #include <linux/videodev2.h> #include <linux/mfd/si476x-reports.h> enum si476x_ctrl_id { V4L2_CID_SI476X_RSSI_THRESHOLD = (V4L2_CID_USER_SI476X_BASE + 1), V4L2_CID_SI476X_SNR_THRESHOLD = (V4L2_CID_USER_SI476X_BASE + 2), V4L2_CID_SI476X_MAX_TUNE_ERROR = (V4L2_CID_USER_SI476X_BASE + 3), V4L2_CID_SI476X_HARMONICS_COUNT = (V4L2_CID_USER_SI476X_BASE + 4), V4L2_CID_SI476X_DIVERSITY_MODE = (V4L2_CID_USER_SI476X_BASE + 5), V4L2_CID_SI476X_INTERCHIP_LINK = (V4L2_CID_USER_SI476X_BASE + 6), }; #endif /* SI476X_H*/ PK ! ��X�X X exynos-fimc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Samsung S5P/Exynos4 SoC series camera interface driver header * * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd. * Sylwester Nawrocki <s.nawrocki@samsung.com> */ #ifndef S5P_FIMC_H_ #define S5P_FIMC_H_ #include <media/media-entity.h> #include <media/v4l2-dev.h> #include <media/v4l2-mediabus.h> /* * Enumeration of data inputs to the camera subsystem. */ enum fimc_input { FIMC_INPUT_PARALLEL_0 = 1, FIMC_INPUT_PARALLEL_1, FIMC_INPUT_MIPI_CSI2_0 = 3, FIMC_INPUT_MIPI_CSI2_1, FIMC_INPUT_WRITEBACK_A = 5, FIMC_INPUT_WRITEBACK_B, FIMC_INPUT_WRITEBACK_ISP = 5, }; /* * Enumeration of the FIMC data bus types. */ enum fimc_bus_type { /* Camera parallel bus */ FIMC_BUS_TYPE_ITU_601 = 1, /* Camera parallel bus with embedded synchronization */ FIMC_BUS_TYPE_ITU_656, /* Camera MIPI-CSI2 serial bus */ FIMC_BUS_TYPE_MIPI_CSI2, /* FIFO link from LCD controller (WriteBack A) */ FIMC_BUS_TYPE_LCD_WRITEBACK_A, /* FIFO link from LCD controller (WriteBack B) */ FIMC_BUS_TYPE_LCD_WRITEBACK_B, /* FIFO link from FIMC-IS */ FIMC_BUS_TYPE_ISP_WRITEBACK = FIMC_BUS_TYPE_LCD_WRITEBACK_B, }; #define fimc_input_is_parallel(x) ((x) == 1 || (x) == 2) #define fimc_input_is_mipi_csi(x) ((x) == 3 || (x) == 4) /* * The subdevices' group IDs. */ #define GRP_ID_SENSOR (1 << 8) #define GRP_ID_FIMC_IS_SENSOR (1 << 9) #define GRP_ID_WRITEBACK (1 << 10) #define GRP_ID_CSIS (1 << 11) #define GRP_ID_FIMC (1 << 12) #define GRP_ID_FLITE (1 << 13) #define GRP_ID_FIMC_IS (1 << 14) /** * struct fimc_source_info - video source description required for the host * interface configuration * * @fimc_bus_type: FIMC camera input type * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc. * @flags: the parallel sensor bus flags defining signals polarity (V4L2_MBUS_*) * @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU) */ struct fimc_source_info { enum fimc_bus_type fimc_bus_type; enum fimc_bus_type sensor_bus_type; u16 flags; u16 mux_id; }; /* * v4l2_device notification id. This is only for internal use in the kernel. * Sensor subdevs should issue S5P_FIMC_TX_END_NOTIFY notification in single * frame capture mode when there is only one VSYNC pulse issued by the sensor * at beginning of the frame transmission. */ #define S5P_FIMC_TX_END_NOTIFY _IO('e', 0) #define FIMC_MAX_PLANES 3 /** * struct fimc_fmt - color format data structure * @mbus_code: media bus pixel code, -1 if not applicable * @fourcc: fourcc code for this format, 0 if not applicable * @color: the driver's private color format id * @memplanes: number of physically non-contiguous data planes * @colplanes: number of physically contiguous data planes * @colorspace: v4l2 colorspace (V4L2_COLORSPACE_*) * @depth: per plane driver's private 'number of bits per pixel' * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no) * @flags: flags indicating which operation mode format applies to */ struct fimc_fmt { u32 mbus_code; u32 fourcc; u32 color; u16 memplanes; u16 colplanes; u8 colorspace; u8 depth[FIMC_MAX_PLANES]; u16 mdataplanes; u16 flags; #define FMT_FLAGS_CAM (1 << 0) #define FMT_FLAGS_M2M_IN (1 << 1) #define FMT_FLAGS_M2M_OUT (1 << 2) #define FMT_FLAGS_M2M (1 << 1 | 1 << 2) #define FMT_HAS_ALPHA (1 << 3) #define FMT_FLAGS_COMPRESSED (1 << 4) #define FMT_FLAGS_WRITEBACK (1 << 5) #define FMT_FLAGS_RAW_BAYER (1 << 6) #define FMT_FLAGS_YUV (1 << 7) }; struct exynos_media_pipeline; /* * Media pipeline operations to be called from within a video node, i.e. the * last entity within the pipeline. Implemented by related media device driver. */ struct exynos_media_pipeline_ops { int (*prepare)(struct exynos_media_pipeline *p, struct media_entity *me); int (*unprepare)(struct exynos_media_pipeline *p); int (*open)(struct exynos_media_pipeline *p, struct media_entity *me, bool resume); int (*close)(struct exynos_media_pipeline *p); int (*set_stream)(struct exynos_media_pipeline *p, bool state); }; struct exynos_video_entity { struct video_device vdev; struct exynos_media_pipeline *pipe; }; struct exynos_media_pipeline { struct media_pipeline mp; const struct exynos_media_pipeline_ops *ops; }; static inline struct exynos_video_entity *vdev_to_exynos_video_entity( struct video_device *vdev) { return container_of(vdev, struct exynos_video_entity, vdev); } #define fimc_pipeline_call(ent, op, args...) \ ((!(ent) || !(ent)->pipe) ? -ENOENT : \ (((ent)->pipe->ops && (ent)->pipe->ops->op) ? \ (ent)->pipe->ops->op(((ent)->pipe), ##args) : -ENOIOCTLCMD)) \ #endif /* S5P_FIMC_H_ */ PK ! �ϐ�: : sh_vou.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * SuperH Video Output Unit (VOU) driver header * * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> */ #ifndef SH_VOU_H #define SH_VOU_H #include <linux/i2c.h> /* Bus flags */ #define SH_VOU_PCLK_FALLING (1 << 0) #define SH_VOU_HSYNC_LOW (1 << 1) #define SH_VOU_VSYNC_LOW (1 << 2) enum sh_vou_bus_fmt { SH_VOU_BUS_8BIT, SH_VOU_BUS_16BIT, SH_VOU_BUS_BT656, }; struct sh_vou_pdata { enum sh_vou_bus_fmt bus_fmt; int i2c_adap; struct i2c_board_info *board_info; unsigned long flags; }; #endif PK ! �� �1 1 s3c_camif.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * s3c24xx/s3c64xx SoC series Camera Interface (CAMIF) driver * * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com> */ #ifndef MEDIA_S3C_CAMIF_ #define MEDIA_S3C_CAMIF_ #include <linux/i2c.h> #include <media/v4l2-mediabus.h> /** * struct s3c_camif_sensor_info - an image sensor description * @i2c_board_info: pointer to an I2C sensor subdevice board info * @clock_frequency: frequency of the clock the host provides to a sensor * @mbus_type: media bus type * @i2c_bus_num: i2c control bus id the sensor is attached to * @flags: the parallel bus flags defining signals polarity (V4L2_MBUS_*) * @use_field: 1 if parallel bus FIELD signal is used (only s3c64xx) */ struct s3c_camif_sensor_info { struct i2c_board_info i2c_board_info; unsigned long clock_frequency; enum v4l2_mbus_type mbus_type; u16 i2c_bus_num; u16 flags; u8 use_field; }; struct s3c_camif_plat_data { struct s3c_camif_sensor_info sensor; int (*gpio_get)(void); int (*gpio_put)(void); }; #endif /* MEDIA_S3C_CAMIF_ */ PK ! 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