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PK ! e[� � nbpfaxi.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd. * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> */ #ifndef DT_BINDINGS_NBPFAXI_H #define DT_BINDINGS_NBPFAXI_H /** * Use "#dma-cells = <2>;" with the second integer defining slave DMA flags: */ #define NBPF_SLAVE_RQ_HIGH 1 #define NBPF_SLAVE_RQ_LOW 2 #define NBPF_SLAVE_RQ_LEVEL 4 #endif PK ! N�v~K K x2000-dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides macros for X2000 DMA bindings. * * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> */ #ifndef __DT_BINDINGS_DMA_X2000_DMA_H__ #define __DT_BINDINGS_DMA_X2000_DMA_H__ /* * Request type numbers for the X2000 DMA controller (written to the DRTn * register for the channel). */ #define X2000_DMA_AUTO 0x8 #define X2000_DMA_UART5_TX 0xa #define X2000_DMA_UART5_RX 0xb #define X2000_DMA_UART4_TX 0xc #define X2000_DMA_UART4_RX 0xd #define X2000_DMA_UART3_TX 0xe #define X2000_DMA_UART3_RX 0xf #define X2000_DMA_UART2_TX 0x10 #define X2000_DMA_UART2_RX 0x11 #define X2000_DMA_UART1_TX 0x12 #define X2000_DMA_UART1_RX 0x13 #define X2000_DMA_UART0_TX 0x14 #define X2000_DMA_UART0_RX 0x15 #define X2000_DMA_SSI0_TX 0x16 #define X2000_DMA_SSI0_RX 0x17 #define X2000_DMA_SSI1_TX 0x18 #define X2000_DMA_SSI1_RX 0x19 #define X2000_DMA_I2C0_TX 0x24 #define X2000_DMA_I2C0_RX 0x25 #define X2000_DMA_I2C1_TX 0x26 #define X2000_DMA_I2C1_RX 0x27 #define X2000_DMA_I2C2_TX 0x28 #define X2000_DMA_I2C2_RX 0x29 #define X2000_DMA_I2C3_TX 0x2a #define X2000_DMA_I2C3_RX 0x2b #define X2000_DMA_I2C4_TX 0x2c #define X2000_DMA_I2C4_RX 0x2d #define X2000_DMA_I2C5_TX 0x2e #define X2000_DMA_I2C5_RX 0x2f #define X2000_DMA_UART6_TX 0x30 #define X2000_DMA_UART6_RX 0x31 #define X2000_DMA_UART7_TX 0x32 #define X2000_DMA_UART7_RX 0x33 #define X2000_DMA_UART8_TX 0x34 #define X2000_DMA_UART8_RX 0x35 #define X2000_DMA_UART9_TX 0x36 #define X2000_DMA_UART9_RX 0x37 #define X2000_DMA_SADC_RX 0x38 #endif /* __DT_BINDINGS_DMA_X2000_DMA_H__ */ PK ! �8� dw-dmac.hnu �[��� /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ #ifndef __DT_BINDINGS_DMA_DW_DMAC_H__ #define __DT_BINDINGS_DMA_DW_DMAC_H__ /* * Protection Control bits provide protection against illegal transactions. * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals. */ #define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */ #define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */ #define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */ #endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */ PK ! �d�S S axi-dmac.hnu �[��� /* * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __DT_BINDINGS_DMA_AXI_DMAC_H__ #define __DT_BINDINGS_DMA_AXI_DMAC_H__ #define AXI_DMAC_BUS_TYPE_AXI_MM 0 #define AXI_DMAC_BUS_TYPE_AXI_STREAM 1 #define AXI_DMAC_BUS_TYPE_FIFO 2 #endif PK ! @q6�| | x1000-dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides macros for X1000 DMA bindings. * * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com> */ #ifndef __DT_BINDINGS_DMA_X1000_DMA_H__ #define __DT_BINDINGS_DMA_X1000_DMA_H__ /* * Request type numbers for the X1000 DMA controller (written to the DRTn * register for the channel). */ #define X1000_DMA_DMIC_RX 0x5 #define X1000_DMA_I2S0_TX 0x6 #define X1000_DMA_I2S0_RX 0x7 #define X1000_DMA_AUTO 0x8 #define X1000_DMA_UART2_TX 0x10 #define X1000_DMA_UART2_RX 0x11 #define X1000_DMA_UART1_TX 0x12 #define X1000_DMA_UART1_RX 0x13 #define X1000_DMA_UART0_TX 0x14 #define X1000_DMA_UART0_RX 0x15 #define X1000_DMA_SSI0_TX 0x16 #define X1000_DMA_SSI0_RX 0x17 #define X1000_DMA_MSC0_TX 0x1a #define X1000_DMA_MSC0_RX 0x1b #define X1000_DMA_MSC1_TX 0x1c #define X1000_DMA_MSC1_RX 0x1d #define X1000_DMA_PCM0_TX 0x20 #define X1000_DMA_PCM0_RX 0x21 #define X1000_DMA_SMB0_TX 0x24 #define X1000_DMA_SMB0_RX 0x25 #define X1000_DMA_SMB1_TX 0x26 #define X1000_DMA_SMB1_RX 0x27 #define X1000_DMA_SMB2_TX 0x28 #define X1000_DMA_SMB2_RX 0x29 #endif /* __DT_BINDINGS_DMA_X1000_DMA_H__ */ PK ! 4� � at91.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides macros for at91 dma bindings. * * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> */ #ifndef __DT_BINDINGS_AT91_DMA_H__ #define __DT_BINDINGS_AT91_DMA_H__ /* ---------- HDMAC ---------- */ /* * Source and/or destination peripheral ID */ #define AT91_DMA_CFG_PER_ID_MASK (0xff) #define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) /* * FIFO configuration: it defines when a request is serviced. */ #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) #define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ /* ---------- XDMAC ---------- */ #define AT91_XDMAC_DT_MEM_IF_MASK (0x1) #define AT91_XDMAC_DT_MEM_IF_OFFSET (13) #define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ << AT91_XDMAC_DT_MEM_IF_OFFSET) #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ & AT91_XDMAC_DT_MEM_IF_MASK) #define AT91_XDMAC_DT_PER_IF_MASK (0x1) #define AT91_XDMAC_DT_PER_IF_OFFSET (14) #define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ << AT91_XDMAC_DT_PER_IF_OFFSET) #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ & AT91_XDMAC_DT_PER_IF_MASK) #define AT91_XDMAC_DT_PERID_MASK (0x7f) #define AT91_XDMAC_DT_PERID_OFFSET (24) #define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ << AT91_XDMAC_DT_PERID_OFFSET) #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ & AT91_XDMAC_DT_PERID_MASK) #endif /* __DT_BINDINGS_AT91_DMA_H__ */ PK ! "�- - jz4775-dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides macros for JZ4775 DMA bindings. * * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> */ #ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__ #define __DT_BINDINGS_DMA_JZ4775_DMA_H__ /* * Request type numbers for the JZ4775 DMA controller (written to the DRTn * register for the channel). */ #define JZ4775_DMA_I2S0_TX 0x6 #define JZ4775_DMA_I2S0_RX 0x7 #define JZ4775_DMA_AUTO 0x8 #define JZ4775_DMA_SADC_RX 0x9 #define JZ4775_DMA_UART3_TX 0x0e #define JZ4775_DMA_UART3_RX 0x0f #define JZ4775_DMA_UART2_TX 0x10 #define JZ4775_DMA_UART2_RX 0x11 #define JZ4775_DMA_UART1_TX 0x12 #define JZ4775_DMA_UART1_RX 0x13 #define JZ4775_DMA_UART0_TX 0x14 #define JZ4775_DMA_UART0_RX 0x15 #define JZ4775_DMA_SSI0_TX 0x16 #define JZ4775_DMA_SSI0_RX 0x17 #define JZ4775_DMA_MSC0_TX 0x1a #define JZ4775_DMA_MSC0_RX 0x1b #define JZ4775_DMA_MSC1_TX 0x1c #define JZ4775_DMA_MSC1_RX 0x1d #define JZ4775_DMA_MSC2_TX 0x1e #define JZ4775_DMA_MSC2_RX 0x1f #define JZ4775_DMA_PCM0_TX 0x20 #define JZ4775_DMA_PCM0_RX 0x21 #define JZ4775_DMA_SMB0_TX 0x24 #define JZ4775_DMA_SMB0_RX 0x25 #define JZ4775_DMA_SMB1_TX 0x26 #define JZ4775_DMA_SMB1_RX 0x27 #define JZ4775_DMA_SMB2_TX 0x28 #define JZ4775_DMA_SMB2_RX 0x29 #endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */ PK ! ���$ $ qcom-gpi.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ /* Copyright (c) 2020, Linaro Ltd. */ #ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ #define __DT_BINDINGS_DMA_QCOM_GPI_H__ #define QCOM_GPI_SPI 1 #define QCOM_GPI_UART 2 #define QCOM_GPI_I2C 3 #endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ PK ! <�uB� � xlnx-zynqmp-dpdma.hnu �[��� /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com> */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ PK ! [c,�� � jz4780-dma.hnu �[��� #ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__ #define __DT_BINDINGS_DMA_JZ4780_DMA_H__ /* * Request type numbers for the JZ4780 DMA controller (written to the DRTn * register for the channel). */ #define JZ4780_DMA_I2S1_TX 0x4 #define JZ4780_DMA_I2S1_RX 0x5 #define JZ4780_DMA_I2S0_TX 0x6 #define JZ4780_DMA_I2S0_RX 0x7 #define JZ4780_DMA_AUTO 0x8 #define JZ4780_DMA_SADC_RX 0x9 #define JZ4780_DMA_UART4_TX 0xc #define JZ4780_DMA_UART4_RX 0xd #define JZ4780_DMA_UART3_TX 0xe #define JZ4780_DMA_UART3_RX 0xf #define JZ4780_DMA_UART2_TX 0x10 #define JZ4780_DMA_UART2_RX 0x11 #define JZ4780_DMA_UART1_TX 0x12 #define JZ4780_DMA_UART1_RX 0x13 #define JZ4780_DMA_UART0_TX 0x14 #define JZ4780_DMA_UART0_RX 0x15 #define JZ4780_DMA_SSI0_TX 0x16 #define JZ4780_DMA_SSI0_RX 0x17 #define JZ4780_DMA_SSI1_TX 0x18 #define JZ4780_DMA_SSI1_RX 0x19 #define JZ4780_DMA_MSC0_TX 0x1a #define JZ4780_DMA_MSC0_RX 0x1b #define JZ4780_DMA_MSC1_TX 0x1c #define JZ4780_DMA_MSC1_RX 0x1d #define JZ4780_DMA_MSC2_TX 0x1e #define JZ4780_DMA_MSC2_RX 0x1f #define JZ4780_DMA_PCM0_TX 0x20 #define JZ4780_DMA_PCM0_RX 0x21 #define JZ4780_DMA_SMB0_TX 0x24 #define JZ4780_DMA_SMB0_RX 0x25 #define JZ4780_DMA_SMB1_TX 0x26 #define JZ4780_DMA_SMB1_RX 0x27 #define JZ4780_DMA_SMB2_TX 0x28 #define JZ4780_DMA_SMB2_RX 0x29 #define JZ4780_DMA_SMB3_TX 0x2a #define JZ4780_DMA_SMB3_RX 0x2b #define JZ4780_DMA_SMB4_TX 0x2c #define JZ4780_DMA_SMB4_RX 0x2d #define JZ4780_DMA_DES_TX 0x2e #define JZ4780_DMA_DES_RX 0x2f #endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */ PK ! k2P� � sun4i-a10.hnu �[��� /* * Copyright 2014 Maxime Ripard * * Maxime Ripard <maxime.ripard@free-electrons.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public * License along with this file; if not, write to the Free * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * MA 02110-1301 USA * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_ #define __DT_BINDINGS_DMA_SUN4I_A10_H_ #define SUN4I_DMA_NORMAL 0 #define SUN4I_DMA_DEDICATED 1 #endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */ PK ! �?k k x1830-dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides macros for X1830 DMA bindings. * * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> */ #ifndef __DT_BINDINGS_DMA_X1830_DMA_H__ #define __DT_BINDINGS_DMA_X1830_DMA_H__ /* * Request type numbers for the X1830 DMA controller (written to the DRTn * register for the channel). */ #define X1830_DMA_I2S0_TX 0x6 #define X1830_DMA_I2S0_RX 0x7 #define X1830_DMA_AUTO 0x8 #define X1830_DMA_SADC_RX 0x9 #define X1830_DMA_UART1_TX 0x12 #define X1830_DMA_UART1_RX 0x13 #define X1830_DMA_UART0_TX 0x14 #define X1830_DMA_UART0_RX 0x15 #define X1830_DMA_SSI0_TX 0x16 #define X1830_DMA_SSI0_RX 0x17 #define X1830_DMA_SSI1_TX 0x18 #define X1830_DMA_SSI1_RX 0x19 #define X1830_DMA_MSC0_TX 0x1a #define X1830_DMA_MSC0_RX 0x1b #define X1830_DMA_MSC1_TX 0x1c #define X1830_DMA_MSC1_RX 0x1d #define X1830_DMA_DMIC_RX 0x21 #define X1830_DMA_SMB0_TX 0x24 #define X1830_DMA_SMB0_RX 0x25 #define X1830_DMA_SMB1_TX 0x26 #define X1830_DMA_SMB1_RX 0x27 #define X1830_DMA_DES_TX 0x2e #define X1830_DMA_DES_RX 0x2f #endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */ PK ! �&��� � Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0 menu "DMA support" config SH_DMA bool "SuperH on-chip DMA controller (DMAC) support" depends on CPU_SH3 || CPU_SH4 default n config SH_DMA_IRQ_MULTI bool depends on SH_DMA default y if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \ CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091 || \ CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7780 || \ CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7760 config SH_DMA_API depends on SH_DMA bool "SuperH DMA API support" default n help SH_DMA_API always enabled DMA API of used SuperH. If you want to use DMA ENGINE, you must not enable this. Please enable DMA_ENGINE and SH_DMAE. config NR_ONCHIP_DMA_CHANNELS int depends on SH_DMA default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ CPU_SUBTYPE_SH7760 default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \ CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724 default "6" help This allows you to specify the number of channels that the on-chip DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. config SH_DMABRG bool "SH7760 DMABRG support" depends on CPU_SUBTYPE_SH7760 help The DMABRG does data transfers from main memory to Audio/USB units of the SH7760. Say Y if you want to use Audio/USB DMA on your SH7760 board. config PVR2_DMA tristate "PowerVR 2 DMAC support" depends on SH_DREAMCAST && SH_DMA help Selecting this will enable support for the PVR2 DMA controller. As this chains off of the on-chip DMAC, that must also be enabled by default. This is primarily used by the pvr2fb framebuffer driver for certain optimizations, but is not necessary for functionality. If in doubt, say N. config G2_DMA tristate "G2 Bus DMA support" depends on SH_DREAMCAST && SH_DMA_API help This enables support for the DMA controller for the Dreamcast's G2 bus. Drivers that want this will generally enable this on their own. If in doubt, say N. endmenu PK ! ��3� Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 # # Makefile for the SuperH DMA specific kernel interface routines under Linux. # obj-$(CONFIG_SH_DMA_API) += dma-sh.o dma-api.o dma-sysfs.o obj-$(CONFIG_PVR2_DMA) += dma-pvr2.o obj-$(CONFIG_G2_DMA) += dma-g2.o obj-$(CONFIG_SH_DMABRG) += dmabrg.o PK ! e[� � nbpfaxi.hnu �[��� PK ! N�v~K K � x2000-dma.hnu �[��� PK ! �8� X dw-dmac.hnu �[��� PK ! �d�S S � axi-dmac.hnu �[��� PK ! @q6�| | 2 x1000-dma.hnu �[��� PK ! 4� � � at91.hnu �[��� PK ! "�- - � jz4775-dma.hnu �[��� PK ! ���$ $ % qcom-gpi.hnu �[��� PK ! <�uB� � n& xlnx-zynqmp-dpdma.hnu �[��� PK ! [c,�� � �( jz4780-dma.hnu �[��� PK ! k2P� � �. sun4i-a10.hnu �[��� PK ! �?k k h8 x1830-dma.hnu �[��� PK ! �&��� � = Kconfignu �[��� PK ! ��3� F Makefilenu �[��� PK jG
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