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PK ! K� +1 1 unistd.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_UNISTD_H #define _ALPHA_UNISTD_H #include <uapi/asm/unistd.h> #define NR_SYSCALLS __NR_syscalls #define __ARCH_WANT_NEW_STAT #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_STAT64 #define __ARCH_WANT_SYS_GETHOSTNAME #define __ARCH_WANT_SYS_FADVISE64 #define __ARCH_WANT_SYS_GETPGRP #define __ARCH_WANT_SYS_OLDUMOUNT #define __ARCH_WANT_SYS_SIGPENDING #define __ARCH_WANT_SYS_UTIME #define __ARCH_WANT_SYS_FORK #define __ARCH_WANT_SYS_VFORK #define __ARCH_WANT_SYS_CLONE #endif /* _ALPHA_UNISTD_H */ PK ! t� -� � setup.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __ALPHA_SETUP_H #define __ALPHA_SETUP_H #include <uapi/asm/setup.h> /* * We leave one page for the initial stack page, and one page for * the initial process structure. Also, the console eats 3 MB for * the initial bootloader (one of which we can reclaim later). */ #define BOOT_PCB 0x20000000 #define BOOT_ADDR 0x20000000 /* Remove when official MILO sources have ELF support: */ #define BOOT_SIZE (16*1024) #ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS #define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */ #else #define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */ #endif #define KERNEL_START (PAGE_OFFSET+KERNEL_START_PHYS) #define SWAPPER_PGD KERNEL_START #define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000) #define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000) #define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000) #define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000) #define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000) /* * This is setup by the secondary bootstrap loader. Because * the zero page is zeroed out as soon as the vm system is * initialized, we need to copy things out into a more permanent * place. */ #define PARAM ZERO_PGE #define COMMAND_LINE ((char *)(absolute_pointer(PARAM + 0x0000))) #define INITRD_START (*(unsigned long *) (PARAM+0x100)) #define INITRD_SIZE (*(unsigned long *) (PARAM+0x108)) #endif PK ! � ��� � Kbuildnu �[��� # SPDX-License-Identifier: GPL-2.0 generated-y += syscall_table.h generic-y += export.h generic-y += kvm_para.h generic-y += mcs_spinlock.h PK ! �^r�] ] page.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_PAGE_H #define _ALPHA_PAGE_H #include <linux/const.h> #include <asm/pal.h> /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 13 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) #ifndef __ASSEMBLY__ #define STRICT_MM_TYPECHECKS extern void clear_page(void *page); #define clear_user_page(page, vaddr, pg) clear_page(page) #define alloc_zeroed_user_highpage_movable(vma, vaddr) \ alloc_page_vma(GFP_HIGHUSER_MOVABLE | __GFP_ZERO, vma, vaddr) #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE_MOVABLE extern void copy_page(void * _to, void * _from); #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) #ifdef STRICT_MM_TYPECHECKS /* * These are used to make use of C type-checking.. */ typedef struct { unsigned long pte; } pte_t; typedef struct { unsigned long pmd; } pmd_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; #define pte_val(x) ((x).pte) #define pmd_val(x) ((x).pmd) #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) #define __pte(x) ((pte_t) { (x) } ) #define __pmd(x) ((pmd_t) { (x) } ) #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) #else /* * .. while these make it easier on the compiler */ typedef unsigned long pte_t; typedef unsigned long pmd_t; typedef unsigned long pgd_t; typedef unsigned long pgprot_t; #define pte_val(x) (x) #define pmd_val(x) (x) #define pgd_val(x) (x) #define pgprot_val(x) (x) #define __pte(x) (x) #define __pgd(x) (x) #define __pgprot(x) (x) #endif /* STRICT_MM_TYPECHECKS */ typedef struct page *pgtable_t; #ifdef USE_48_BIT_KSEG #define PAGE_OFFSET 0xffff800000000000UL #else #define PAGE_OFFSET 0xfffffc0000000000UL #endif #else #ifdef USE_48_BIT_KSEG #define PAGE_OFFSET 0xffff800000000000 #else #define PAGE_OFFSET 0xfffffc0000000000 #endif #endif /* !__ASSEMBLY__ */ #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define virt_addr_valid(kaddr) pfn_valid((__pa(kaddr) >> PAGE_SHIFT)) #ifdef CONFIG_FLATMEM #define pfn_valid(pfn) ((pfn) < max_mapnr) #endif /* CONFIG_FLATMEM */ #include <asm-generic/memory_model.h> #include <asm-generic/getorder.h> #endif /* _ALPHA_PAGE_H */ PK ! 9u��s s signal.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASMAXP_SIGNAL_H #define _ASMAXP_SIGNAL_H #include <uapi/asm/signal.h> /* Digital Unix defines 64 signals. Most things should be clean enough to redefine this at will, if care is taken to make libc match. */ #define _NSIG 64 #define _NSIG_BPW 64 #define _NSIG_WORDS (_NSIG / _NSIG_BPW) typedef unsigned long old_sigset_t; /* at least 32 bits */ typedef struct { unsigned long sig[_NSIG_WORDS]; } sigset_t; struct osf_sigaction { __sighandler_t sa_handler; old_sigset_t sa_mask; int sa_flags; }; #define __ARCH_HAS_KA_RESTORER #include <asm/sigcontext.h> #endif PK ! ���o� � ptrace.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASMAXP_PTRACE_H #define _ASMAXP_PTRACE_H #include <uapi/asm/ptrace.h> #define arch_has_single_step() (1) #define user_mode(regs) (((regs)->ps & 8) != 0) #define instruction_pointer(regs) ((regs)->pc) #define profile_pc(regs) instruction_pointer(regs) #define current_user_stack_pointer() rdusp() #define task_pt_regs(task) \ ((struct pt_regs *) (task_stack_page(task) + 2*PAGE_SIZE) - 1) #define current_pt_regs() \ ((struct pt_regs *) ((char *)current_thread_info() + 2*PAGE_SIZE) - 1) #define signal_pt_regs current_pt_regs #define force_successful_syscall_return() (current_pt_regs()->r0 = 0) static inline unsigned long regs_return_value(struct pt_regs *regs) { return regs->r0; } #endif PK ! Ӽ�4G G byteorder.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Copyright (C) 2012 ARM Ltd. * Copyright (C) 2015 Regents of the University of California */ #ifndef _UAPI_ASM_RISCV_BYTEORDER_H #define _UAPI_ASM_RISCV_BYTEORDER_H #include <linux/byteorder/little_endian.h> #endif /* _UAPI_ASM_RISCV_BYTEORDER_H */ PK ! ?��� sigcontext.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Copyright (C) 2012 Regents of the University of California */ #ifndef _UAPI_ASM_RISCV_SIGCONTEXT_H #define _UAPI_ASM_RISCV_SIGCONTEXT_H #include <asm/ptrace.h> /* * Signal context structure * * This contains the context saved before a signal handler is invoked; * it is restored by sys_sigreturn / sys_rt_sigreturn. */ struct sigcontext { struct user_regs_struct sc_regs; union __riscv_fp_state sc_fpregs; }; #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */ PK ! ��� swab.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_SWAB_H #define _ASM_IA64_SWAB_H /* * Modified 1998, 1999 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co. */ #include <linux/types.h> #include <asm/intrinsics.h> #include <linux/compiler.h> static __inline__ __attribute_const__ __u64 __arch_swab64(__u64 x) { __u64 result; result = ia64_mux1(x, ia64_mux1_rev); return result; } #define __arch_swab64 __arch_swab64 static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 x) { return __arch_swab64(x) >> 32; } #define __arch_swab32 __arch_swab32 static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 x) { return __arch_swab64(x) >> 48; } #define __arch_swab16 __arch_swab16 #endif /* _ASM_IA64_SWAB_H */ PK ! ��� � elf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ALPHA_ELF_H #define __ASM_ALPHA_ELF_H #include <asm/auxvec.h> #include <asm/special_insns.h> /* Special values for the st_other field in the symbol table. */ #define STO_ALPHA_NOPV 0x80 #define STO_ALPHA_STD_GPLOAD 0x88 /* * Alpha ELF relocation types */ #define R_ALPHA_NONE 0 /* No reloc */ #define R_ALPHA_REFLONG 1 /* Direct 32 bit */ #define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ #define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ #define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ #define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ #define R_ALPHA_GPDISP 6 /* Add displacement to GP */ #define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ #define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ #define R_ALPHA_SREL16 9 /* PC relative 16 bit */ #define R_ALPHA_SREL32 10 /* PC relative 32 bit */ #define R_ALPHA_SREL64 11 /* PC relative 64 bit */ #define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ #define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ #define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ #define R_ALPHA_COPY 24 /* Copy symbol at runtime */ #define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ #define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ #define R_ALPHA_RELATIVE 27 /* Adjust by program base */ #define R_ALPHA_BRSGP 28 #define R_ALPHA_TLSGD 29 #define R_ALPHA_TLS_LDM 30 #define R_ALPHA_DTPMOD64 31 #define R_ALPHA_GOTDTPREL 32 #define R_ALPHA_DTPREL64 33 #define R_ALPHA_DTPRELHI 34 #define R_ALPHA_DTPRELLO 35 #define R_ALPHA_DTPREL16 36 #define R_ALPHA_GOTTPREL 37 #define R_ALPHA_TPREL64 38 #define R_ALPHA_TPRELHI 39 #define R_ALPHA_TPRELLO 40 #define R_ALPHA_TPREL16 41 #define SHF_ALPHA_GPREL 0x10000000 /* Legal values for e_flags field of Elf64_Ehdr. */ #define EF_ALPHA_32BIT 1 /* All addresses are below 2GB */ /* * ELF register definitions.. */ /* * The OSF/1 version of <sys/procfs.h> makes gregset_t 46 entries long. * I have no idea why that is so. For now, we just leave it at 33 * (32 general regs + processor status word). */ #define ELF_NGREG 33 #define ELF_NFPREG 32 typedef unsigned long elf_greg_t; typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; /* * This is used to ensure we don't load something for the wrong architecture. */ #define elf_check_arch(x) (((x)->e_machine == EM_ALPHA) && !((x)->e_flags & EF_ALPHA_32BIT)) /* * These are used to set parameters in the core dumps. */ #define ELF_CLASS ELFCLASS64 #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_ALPHA #define ELF_EXEC_PAGESIZE 8192 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical use of this is to invoke "./ld.so someprog" to test out a new version of the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ #define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x1000000) /* $0 is set by ld.so to a pointer to a function which might be registered using atexit. This provides a mean for the dynamic linker to call DT_FINI functions for shared libraries that have been loaded before the code runs. So that we can use the same startup file with static executables, we start programs with a value of 0 to indicate that there is no such function. */ #define ELF_PLAT_INIT(_r, load_addr) _r->r0 = 0 /* The registers are laid out in pt_regs for PAL and syscall convenience. Re-order them for the linear elf_gregset_t. */ struct pt_regs; struct thread_info; struct task_struct; extern void dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt, struct thread_info *ti); #define ELF_CORE_COPY_REGS(DEST, REGS) \ dump_elf_thread(DEST, REGS, current_thread_info()); /* Similar, but for a thread other than current. */ extern int dump_elf_task(elf_greg_t *dest, struct task_struct *task); #define ELF_CORE_COPY_TASK_REGS(TASK, DEST) \ dump_elf_task(*(DEST), TASK) /* Similar, but for the FP registers. */ extern int dump_elf_task_fp(elf_fpreg_t *dest, struct task_struct *task); #define ELF_CORE_COPY_FPREGS(TASK, DEST) \ dump_elf_task_fp(*(DEST), TASK) /* This yields a mask that user programs can use to figure out what instruction set this CPU supports. This is trivial on Alpha, but not so on other machines. */ #define ELF_HWCAP (~amask(-1)) /* This yields a string that ld.so will use to load implementation specific libraries for optimization. This is more specific in intent than poking at uname or /proc/cpuinfo. */ #define ELF_PLATFORM \ ({ \ enum implver_enum i_ = implver(); \ ( i_ == IMPLVER_EV4 ? "ev4" \ : i_ == IMPLVER_EV5 \ ? (amask(AMASK_BWX) ? "ev5" : "ev56") \ : amask (AMASK_CIX) ? "ev6" : "ev67"); \ }) extern int alpha_l1i_cacheshape; extern int alpha_l1d_cacheshape; extern int alpha_l2_cacheshape; extern int alpha_l3_cacheshape; /* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */ #define ARCH_DLINFO \ do { \ NEW_AUX_ENT(AT_L1I_CACHESHAPE, alpha_l1i_cacheshape); \ NEW_AUX_ENT(AT_L1D_CACHESHAPE, alpha_l1d_cacheshape); \ NEW_AUX_ENT(AT_L2_CACHESHAPE, alpha_l2_cacheshape); \ NEW_AUX_ENT(AT_L3_CACHESHAPE, alpha_l3_cacheshape); \ } while (0) #endif /* __ASM_ALPHA_ELF_H */ PK ! �`�E cachectl.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_CSKY_CACHECTL_H #define __ASM_CSKY_CACHECTL_H /* * See "man cacheflush" */ #define ICACHE (1<<0) #define DCACHE (1<<1) #define BCACHE (ICACHE|DCACHE) #endif /* __ASM_CSKY_CACHECTL_H */ PK ! 2 msgbuf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_MSGBUF_H #define _ASM_MSGBUF_H #include <asm/ipcbuf.h> /* * The msqid64_ds structure for the MIPS architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. * * Pad space is left for: * - 2 miscellaneous unsigned long values */ #if defined(__mips64) struct msqid64_ds { struct ipc64_perm msg_perm; long msg_stime; /* last msgsnd time */ long msg_rtime; /* last msgrcv time */ long msg_ctime; /* last change time */ unsigned long msg_cbytes; /* current number of bytes on queue */ unsigned long msg_qnum; /* number of messages in queue */ unsigned long msg_qbytes; /* max number of bytes on queue */ __kernel_pid_t msg_lspid; /* pid of last msgsnd */ __kernel_pid_t msg_lrpid; /* last receive pid */ unsigned long __unused4; unsigned long __unused5; }; #elif defined (__MIPSEB__) struct msqid64_ds { struct ipc64_perm msg_perm; unsigned long msg_stime_high; unsigned long msg_stime; /* last msgsnd time */ unsigned long msg_rtime_high; unsigned long msg_rtime; /* last msgrcv time */ unsigned long msg_ctime_high; unsigned long msg_ctime; /* last change time */ unsigned long msg_cbytes; /* current number of bytes on queue */ unsigned long msg_qnum; /* number of messages in queue */ unsigned long msg_qbytes; /* max number of bytes on queue */ __kernel_pid_t msg_lspid; /* pid of last msgsnd */ __kernel_pid_t msg_lrpid; /* last receive pid */ unsigned long __unused4; unsigned long __unused5; }; #elif defined (__MIPSEL__) struct msqid64_ds { struct ipc64_perm msg_perm; unsigned long msg_stime; /* last msgsnd time */ unsigned long msg_stime_high; unsigned long msg_rtime; /* last msgrcv time */ unsigned long msg_rtime_high; unsigned long msg_ctime; /* last change time */ unsigned long msg_ctime_high; unsigned long msg_cbytes; /* current number of bytes on queue */ unsigned long msg_qnum; /* number of messages in queue */ unsigned long msg_qbytes; /* max number of bytes on queue */ __kernel_pid_t msg_lspid; /* pid of last msgsnd */ __kernel_pid_t msg_lrpid; /* last receive pid */ unsigned long __unused4; unsigned long __unused5; }; #else #warning no endianess set #endif #endif /* _ASM_MSGBUF_H */ PK ! c��^� � ipcbuf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * include/asm-xtensa/ipcbuf.h * * The ipc64_perm structure for the Xtensa architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. * * Copyright (C) 2001 - 2005 Tensilica Inc. */ #ifndef _XTENSA_IPCBUF_H #define _XTENSA_IPCBUF_H #include <linux/posix_types.h> /* * Pad space is left for: * - 32-bit mode_t and seq * - 2 miscellaneous 32-bit values * * This file is subject to the terms and conditions of the GNU General * Public License. See the file "COPYING" in the main directory of * this archive for more details. */ struct ipc64_perm { __kernel_key_t key; __kernel_uid32_t uid; __kernel_gid32_t gid; __kernel_uid32_t cuid; __kernel_gid32_t cgid; __kernel_mode_t mode; unsigned long seq; unsigned long __unused1; unsigned long __unused2; }; #endif /* _XTENSA_IPCBUF_H */ PK ! � 7�� � mman.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Based on <asm-i386/mman.h>. * * Modified 1998-2000, 2002 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co */ #ifndef _UAPI_ASM_IA64_MMAN_H #define _UAPI_ASM_IA64_MMAN_H #include <asm-generic/mman.h> #define MAP_GROWSUP 0x0200 /* register stack-like segment */ #endif /* _UAPI_ASM_IA64_MMAN_H */ PK ! �7��7 7 sembuf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_SEMBUF_H #define _ASM_SEMBUF_H #include <asm/ipcbuf.h> /* * The semid64_ds structure for the MIPS architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. * * Pad space is left for 2 miscellaneous 64-bit values on mips64, * but used for the upper 32 bit of the time values on mips32. */ #ifdef __mips64 struct semid64_ds { struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ long sem_otime; /* last semop time */ long sem_ctime; /* last change time */ unsigned long sem_nsems; /* no. of semaphores in array */ unsigned long __unused1; unsigned long __unused2; }; #else struct semid64_ds { struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ unsigned long sem_otime; /* last semop time */ unsigned long sem_ctime; /* last change time */ unsigned long sem_nsems; /* no. of semaphores in array */ unsigned long sem_otime_high; unsigned long sem_ctime_high; }; #endif #endif /* _ASM_SEMBUF_H */ PK ! |�^ posix_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_POSIX_TYPES_H #define _ASM_IA64_POSIX_TYPES_H typedef unsigned long __kernel_sigset_t; /* at least 32 bits */ #include <asm-generic/posix_types.h> #endif /* _ASM_IA64_POSIX_TYPES_H */ PK ! w�^� � types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_TYPES_H #define _ALPHA_TYPES_H #include <uapi/asm/types.h> #endif /* _ALPHA_TYPES_H */ PK ! �ة param.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ALPHA_PARAM_H #define _ASM_ALPHA_PARAM_H #include <uapi/asm/param.h> # undef HZ # define HZ CONFIG_HZ # define USER_HZ 1024 # define CLOCKS_PER_SEC USER_HZ /* frequency at which times() counts */ #endif /* _ASM_ALPHA_PARAM_H */ PK ! �ʻ� sockios.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Socket-level I/O control calls. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995 by Ralf Baechle */ #ifndef _ASM_SOCKIOS_H #define _ASM_SOCKIOS_H #include <asm/ioctl.h> /* Socket-level I/O control calls. */ #define FIOGETOWN _IOR('f', 123, int) #define FIOSETOWN _IOW('f', 124, int) #define SIOCATMARK _IOR('s', 7, int) #define SIOCSPGRP _IOW('s', 8, pid_t) #define SIOCGPGRP _IOR('s', 9, pid_t) #define SIOCGSTAMP_OLD 0x8906 /* Get stamp (timeval) */ #define SIOCGSTAMPNS_OLD 0x8907 /* Get stamp (timespec) */ #endif /* _ASM_SOCKIOS_H */ PK ! W��� � poll.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef __ASM_POLL_H #define __ASM_POLL_H #define POLLWRNORM POLLOUT #define POLLWRBAND 0x0100 #include <asm-generic/poll.h> #endif /* __ASM_POLL_H */ PK ! ��Yg g stat.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_STAT_H #define _ASM_IA64_STAT_H /* * Modified 1998, 1999 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co */ struct stat { unsigned long st_dev; unsigned long st_ino; unsigned long st_nlink; unsigned int st_mode; unsigned int st_uid; unsigned int st_gid; unsigned int __pad0; unsigned long st_rdev; unsigned long st_size; unsigned long st_atime; unsigned long st_atime_nsec; unsigned long st_mtime; unsigned long st_mtime_nsec; unsigned long st_ctime; unsigned long st_ctime_nsec; unsigned long st_blksize; long st_blocks; unsigned long __unused[3]; }; #define STAT_HAVE_NSEC 1 struct ia64_oldstat { unsigned int st_dev; unsigned int st_ino; unsigned int st_mode; unsigned int st_nlink; unsigned int st_uid; unsigned int st_gid; unsigned int st_rdev; unsigned int __pad1; unsigned long st_size; unsigned long st_atime; unsigned long st_mtime; unsigned long st_ctime; unsigned int st_blksize; int st_blocks; unsigned int __unused1; unsigned int __unused2; }; #endif /* _ASM_IA64_STAT_H */ PK ! ��� � ioctls.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995, 1996, 2001 Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. */ #ifndef __ASM_IOCTLS_H #define __ASM_IOCTLS_H #include <asm/ioctl.h> #define TCGETA 0x5401 #define TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */ #define TCSETAW 0x5403 #define TCSETAF 0x5404 #define TCSBRK 0x5405 #define TCXONC 0x5406 #define TCFLSH 0x5407 #define TCGETS 0x540d #define TCSETS 0x540e #define TCSETSW 0x540f #define TCSETSF 0x5410 #define TIOCEXCL 0x740d /* set exclusive use of tty */ #define TIOCNXCL 0x740e /* reset exclusive use of tty */ #define TIOCOUTQ 0x7472 /* output queue size */ #define TIOCSTI 0x5472 /* simulate terminal input */ #define TIOCMGET 0x741d /* get all modem bits */ #define TIOCMBIS 0x741b /* bis modem bits */ #define TIOCMBIC 0x741c /* bic modem bits */ #define TIOCMSET 0x741a /* set all modem bits */ #define TIOCPKT 0x5470 /* pty: set/clear packet mode */ #define TIOCPKT_DATA 0x00 /* data packet */ #define TIOCPKT_FLUSHREAD 0x01 /* flush packet */ #define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */ #define TIOCPKT_STOP 0x04 /* stop output */ #define TIOCPKT_START 0x08 /* start output */ #define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */ #define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */ #define TIOCPKT_IOCTL 0x40 /* state change of pty driver */ #define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */ #define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */ #define TIOCNOTTY 0x5471 /* void tty association */ #define TIOCSETD 0x7401 #define TIOCGETD 0x7400 #define FIOCLEX 0x6601 #define FIONCLEX 0x6602 #define FIOASYNC 0x667d #define FIONBIO 0x667e #define FIOQSIZE 0x667f #define TIOCGLTC 0x7474 /* get special local chars */ #define TIOCSLTC 0x7475 /* set special local chars */ #define TIOCSPGRP _IOW('t', 118, int) /* set pgrp of tty */ #define TIOCGPGRP _IOR('t', 119, int) /* get pgrp of tty */ #define TIOCCONS _IOW('t', 120, int) /* become virtual console */ #define FIONREAD 0x467f #define TIOCINQ FIONREAD #define TIOCGETP 0x7408 #define TIOCSETP 0x7409 #define TIOCSETN 0x740a /* TIOCSETP wo flush */ /* #define TIOCSETA _IOW('t', 20, struct termios) set termios struct */ /* #define TIOCSETAW _IOW('t', 21, struct termios) drain output, set */ /* #define TIOCSETAF _IOW('t', 22, struct termios) drn out, fls in, set */ /* #define TIOCGETD _IOR('t', 26, int) get line discipline */ /* #define TIOCSETD _IOW('t', 27, int) set line discipline */ /* 127-124 compat */ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x7416 /* Return the session ID of FD */ #define TCGETS2 _IOR('T', 0x2A, struct termios2) #define TCSETS2 _IOW('T', 0x2B, struct termios2) #define TCSETSW2 _IOW('T', 0x2C, struct termios2) #define TCSETSF2 _IOW('T', 0x2D, struct termios2) #define TIOCGRS485 _IOR('T', 0x2E, struct serial_rs485) #define TIOCSRS485 _IOWR('T', 0x2F, struct serial_rs485) #define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ #define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */ #define TIOCSIG _IOW('T', 0x36, int) /* Generate signal on Pty slave */ #define TIOCVHANGUP 0x5437 #define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */ #define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */ #define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */ #define TIOCGPTPEER _IO('T', 0x41) /* Safely open the slave */ #define TIOCGISO7816 _IOR('T', 0x42, struct serial_iso7816) #define TIOCSISO7816 _IOWR('T', 0x43, struct serial_iso7816) /* I hope the range from 0x5480 on is free ... */ #define TIOCSCTTY 0x5480 /* become controlling tty */ #define TIOCGSOFTCAR 0x5481 #define TIOCSSOFTCAR 0x5482 #define TIOCLINUX 0x5483 #define TIOCGSERIAL 0x5484 #define TIOCSSERIAL 0x5485 #define TCSBRKP 0x5486 /* Needed for POSIX tcsendbreak() */ #define TIOCSERCONFIG 0x5488 #define TIOCSERGWILD 0x5489 #define TIOCSERSWILD 0x548a #define TIOCGLCKTRMIOS 0x548b #define TIOCSLCKTRMIOS 0x548c #define TIOCSERGSTRUCT 0x548d /* For debugging only */ #define TIOCSERGETLSR 0x548e /* Get line status register */ #define TIOCSERGETMULTI 0x548f /* Get multiport config */ #define TIOCSERSETMULTI 0x5490 /* Set multiport config */ #define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */ #define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */ #endif /* __ASM_IOCTLS_H */ PK ! ��E�K K shmbuf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_SHMBUF_H #define _ASM_SHMBUF_H /* * The shmid64_ds structure for the MIPS architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. * * As MIPS was lacking proper padding after shm_?time, we use 48 bits * of the padding at the end to store a few additional bits of the time. * libc implementations need to take care to convert this into a proper * data structure when moving to 64-bit time_t. */ #ifdef __mips64 struct shmid64_ds { struct ipc64_perm shm_perm; /* operation perms */ size_t shm_segsz; /* size of segment (bytes) */ long shm_atime; /* last attach time */ long shm_dtime; /* last detach time */ long shm_ctime; /* last change time */ __kernel_pid_t shm_cpid; /* pid of creator */ __kernel_pid_t shm_lpid; /* pid of last operator */ unsigned long shm_nattch; /* no. of current attaches */ unsigned long __unused1; unsigned long __unused2; }; #else struct shmid64_ds { struct ipc64_perm shm_perm; /* operation perms */ size_t shm_segsz; /* size of segment (bytes) */ unsigned long shm_atime; /* last attach time */ unsigned long shm_dtime; /* last detach time */ unsigned long shm_ctime; /* last change time */ __kernel_pid_t shm_cpid; /* pid of creator */ __kernel_pid_t shm_lpid; /* pid of last operator */ unsigned long shm_nattch; /* no. of current attaches */ unsigned short shm_atime_high; unsigned short shm_dtime_high; unsigned short shm_ctime_high; unsigned short __unused1; }; #endif struct shminfo64 { unsigned long shmmax; unsigned long shmmin; unsigned long shmmni; unsigned long shmseg; unsigned long shmall; unsigned long __unused1; unsigned long __unused2; unsigned long __unused3; unsigned long __unused4; }; #endif /* _ASM_SHMBUF_H */ PK ! ��ʎy y auxvec.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Copyright (C) 2012 ARM Ltd. * Copyright (C) 2015 Regents of the University of California */ #ifndef _UAPI_ASM_RISCV_AUXVEC_H #define _UAPI_ASM_RISCV_AUXVEC_H /* vDSO location */ #define AT_SYSINFO_EHDR 33 /* * The set of entries below represent more extensive information * about the caches, in the form of two entry per cache type, * one entry containing the cache size in bytes, and the other * containing the cache line size in bytes in the bottom 16 bits * and the cache associativity in the next 16 bits. * * The associativity is such that if N is the 16-bit value, the * cache is N way set associative. A value if 0xffff means fully * associative, a value of 1 means directly mapped. * * For all these fields, a value of 0 means that the information * is not known. */ #define AT_L1I_CACHESIZE 40 #define AT_L1I_CACHEGEOMETRY 41 #define AT_L1D_CACHESIZE 42 #define AT_L1D_CACHEGEOMETRY 43 #define AT_L2_CACHESIZE 44 #define AT_L2_CACHEGEOMETRY 45 /* entries in ARCH_DLINFO */ #define AT_VECTOR_SIZE_ARCH 7 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ PK ! @n�s termbits.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_TERMBITS_H #define _ASM_IA64_TERMBITS_H /* * Based on <asm-i386/termbits.h>. * * Modified 1999 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co * * 99/01/28 Added new baudrates */ #include <linux/posix_types.h> typedef unsigned char cc_t; typedef unsigned int speed_t; typedef unsigned int tcflag_t; #define NCCS 19 struct termios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ cc_t c_cc[NCCS]; /* control characters */ }; struct termios2 { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ cc_t c_cc[NCCS]; /* control characters */ speed_t c_ispeed; /* input speed */ speed_t c_ospeed; /* output speed */ }; struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ cc_t c_line; /* line discipline */ cc_t c_cc[NCCS]; /* control characters */ speed_t c_ispeed; /* input speed */ speed_t c_ospeed; /* output speed */ }; /* c_cc characters */ #define VINTR 0 #define VQUIT 1 #define VERASE 2 #define VKILL 3 #define VEOF 4 #define VTIME 5 #define VMIN 6 #define VSWTC 7 #define VSTART 8 #define VSTOP 9 #define VSUSP 10 #define VEOL 11 #define VREPRINT 12 #define VDISCARD 13 #define VWERASE 14 #define VLNEXT 15 #define VEOL2 16 /* c_iflag bits */ #define IGNBRK 0000001 #define BRKINT 0000002 #define IGNPAR 0000004 #define PARMRK 0000010 #define INPCK 0000020 #define ISTRIP 0000040 #define INLCR 0000100 #define IGNCR 0000200 #define ICRNL 0000400 #define IUCLC 0001000 #define IXON 0002000 #define IXANY 0004000 #define IXOFF 0010000 #define IMAXBEL 0020000 #define IUTF8 0040000 /* c_oflag bits */ #define OPOST 0000001 #define OLCUC 0000002 #define ONLCR 0000004 #define OCRNL 0000010 #define ONOCR 0000020 #define ONLRET 0000040 #define OFILL 0000100 #define OFDEL 0000200 #define NLDLY 0000400 #define NL0 0000000 #define NL1 0000400 #define CRDLY 0003000 #define CR0 0000000 #define CR1 0001000 #define CR2 0002000 #define CR3 0003000 #define TABDLY 0014000 #define TAB0 0000000 #define TAB1 0004000 #define TAB2 0010000 #define TAB3 0014000 #define XTABS 0014000 #define BSDLY 0020000 #define BS0 0000000 #define BS1 0020000 #define VTDLY 0040000 #define VT0 0000000 #define VT1 0040000 #define FFDLY 0100000 #define FF0 0000000 #define FF1 0100000 /* c_cflag bit meaning */ #define CBAUD 0010017 #define B0 0000000 /* hang up */ #define B50 0000001 #define B75 0000002 #define B110 0000003 #define B134 0000004 #define B150 0000005 #define B200 0000006 #define B300 0000007 #define B600 0000010 #define B1200 0000011 #define B1800 0000012 #define B2400 0000013 #define B4800 0000014 #define B9600 0000015 #define B19200 0000016 #define B38400 0000017 #define EXTA B19200 #define EXTB B38400 #define CSIZE 0000060 #define CS5 0000000 #define CS6 0000020 #define CS7 0000040 #define CS8 0000060 #define CSTOPB 0000100 #define CREAD 0000200 #define PARENB 0000400 #define PARODD 0001000 #define HUPCL 0002000 #define CLOCAL 0004000 #define CBAUDEX 0010000 #define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 #define B460800 0010004 #define B500000 0010005 #define B576000 0010006 #define B921600 0010007 #define B1000000 0010010 #define B1152000 0010011 #define B1500000 0010012 #define B2000000 0010013 #define B2500000 0010014 #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 #define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ #define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ /* c_lflag bits */ #define ISIG 0000001 #define ICANON 0000002 #define XCASE 0000004 #define ECHO 0000010 #define ECHOE 0000020 #define ECHOK 0000040 #define ECHONL 0000100 #define NOFLSH 0000200 #define TOSTOP 0000400 #define ECHOCTL 0001000 #define ECHOPRT 0002000 #define ECHOKE 0004000 #define FLUSHO 0010000 #define PENDIN 0040000 #define IEXTEN 0100000 #define EXTPROC 0200000 /* tcflow() and TCXONC use these */ #define TCOOFF 0 #define TCOON 1 #define TCIOFF 2 #define TCION 3 /* tcflush() and TCFLSH use these */ #define TCIFLUSH 0 #define TCOFLUSH 1 #define TCIOFLUSH 2 /* tcsetattr uses these */ #define TCSANOW 0 #define TCSADRAIN 1 #define TCSAFLUSH 2 #endif /* _ASM_IA64_TERMBITS_H */ PK ! �R�� � break.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_BREAK_H #define _ASM_IA64_BREAK_H /* * IA-64 Linux break numbers. * * Copyright (C) 1999 Hewlett-Packard Co * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com> */ /* * OS-specific debug break numbers: */ #define __IA64_BREAK_KDB 0x80100 #define __IA64_BREAK_KPROBE 0x81000 /* .. 0x81fff */ /* * OS-specific break numbers: */ #define __IA64_BREAK_SYSCALL 0x100000 #endif /* _ASM_IA64_BREAK_H */ PK ! W̢� � cmpxchg.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_CMPXCHG_H #define _ALPHA_CMPXCHG_H /* * Atomic exchange routines. */ #define ____xchg(type, args...) __xchg ## type ## _local(args) #define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args) #include <asm/xchg.h> #define xchg_local(ptr, x) \ ({ \ __typeof__(*(ptr)) _x_ = (x); \ (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \ sizeof(*(ptr))); \ }) #define arch_cmpxchg_local(ptr, o, n) \ ({ \ __typeof__(*(ptr)) _o_ = (o); \ __typeof__(*(ptr)) _n_ = (n); \ (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \ (unsigned long)_n_, \ sizeof(*(ptr))); \ }) #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ cmpxchg_local((ptr), (o), (n)); \ }) #undef ____xchg #undef ____cmpxchg #define ____xchg(type, args...) __xchg ##type(args) #define ____cmpxchg(type, args...) __cmpxchg ##type(args) #include <asm/xchg.h> /* * The leading and the trailing memory barriers guarantee that these * operations are fully ordered. */ #define arch_xchg(ptr, x) \ ({ \ __typeof__(*(ptr)) __ret; \ __typeof__(*(ptr)) _x_ = (x); \ smp_mb(); \ __ret = (__typeof__(*(ptr))) \ __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ smp_mb(); \ __ret; \ }) #define arch_cmpxchg(ptr, o, n) \ ({ \ __typeof__(*(ptr)) __ret; \ __typeof__(*(ptr)) _o_ = (o); \ __typeof__(*(ptr)) _n_ = (n); \ smp_mb(); \ __ret = (__typeof__(*(ptr))) __cmpxchg((ptr), \ (unsigned long)_o_, (unsigned long)_n_, sizeof(*(ptr)));\ smp_mb(); \ __ret; \ }) #define arch_cmpxchg64(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ arch_cmpxchg((ptr), (o), (n)); \ }) #undef ____cmpxchg #endif /* _ALPHA_CMPXCHG_H */ PK ! �N�� � rse.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_RSE_H #define _ASM_IA64_RSE_H /* * Copyright (C) 1998, 1999 Hewlett-Packard Co * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com> * * Register stack engine related helper functions. This file may be * used in applications, so be careful about the name-space and give * some consideration to non-GNU C compilers (though __inline__ is * fine). */ static __inline__ unsigned long ia64_rse_slot_num (unsigned long *addr) { return (((unsigned long) addr) >> 3) & 0x3f; } /* * Return TRUE if ADDR is the address of an RNAT slot. */ static __inline__ unsigned long ia64_rse_is_rnat_slot (unsigned long *addr) { return ia64_rse_slot_num(addr) == 0x3f; } /* * Returns the address of the RNAT slot that covers the slot at * address SLOT_ADDR. */ static __inline__ unsigned long * ia64_rse_rnat_addr (unsigned long *slot_addr) { return (unsigned long *) ((unsigned long) slot_addr | (0x3f << 3)); } /* * Calculate the number of registers in the dirty partition starting at BSPSTORE and * ending at BSP. This isn't simply (BSP-BSPSTORE)/8 because every 64th slot stores * ar.rnat. */ static __inline__ unsigned long ia64_rse_num_regs (unsigned long *bspstore, unsigned long *bsp) { unsigned long slots = (bsp - bspstore); return slots - (ia64_rse_slot_num(bspstore) + slots)/0x40; } /* * The inverse of the above: given bspstore and the number of * registers, calculate ar.bsp. */ static __inline__ unsigned long * ia64_rse_skip_regs (unsigned long *addr, long num_regs) { long delta = ia64_rse_slot_num(addr) + num_regs; if (num_regs < 0) delta -= 0x3e; return addr + num_regs + delta/0x3f; } #endif /* _ASM_IA64_RSE_H */ PK ! :-��G �G gcc_intrin.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com> * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com> */ #ifndef _UAPI_ASM_IA64_GCC_INTRIN_H #define _UAPI_ASM_IA64_GCC_INTRIN_H #include <linux/types.h> #include <linux/compiler.h> /* define this macro to get some asm stmts included in 'c' files */ #define ASM_SUPPORTED /* Optimization barrier */ /* The "volatile" is due to gcc bugs */ #define ia64_barrier() asm volatile ("":::"memory") #define ia64_stop() asm volatile (";;"::) #define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum)) #define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" :: "i"(regnum)) #define ia64_flushrs() asm volatile ("flushrs;;":::"memory") #define ia64_loadrs() asm volatile ("loadrs;;":::"memory") extern void ia64_bad_param_for_setreg (void); extern void ia64_bad_param_for_getreg (void); #define ia64_setreg(regnum, val) \ ({ \ switch (regnum) { \ case _IA64_REG_PSR_L: \ asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \ break; \ case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ asm volatile ("mov ar%0=%1" :: \ "i" (regnum - _IA64_REG_AR_KR0), \ "r"(val): "memory"); \ break; \ case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ asm volatile ("mov cr%0=%1" :: \ "i" (regnum - _IA64_REG_CR_DCR), \ "r"(val): "memory" ); \ break; \ case _IA64_REG_SP: \ asm volatile ("mov r12=%0" :: \ "r"(val): "memory"); \ break; \ case _IA64_REG_GP: \ asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \ break; \ default: \ ia64_bad_param_for_setreg(); \ break; \ } \ }) #define ia64_getreg(regnum) \ ({ \ __u64 ia64_intri_res; \ \ switch (regnum) { \ case _IA64_REG_GP: \ asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \ break; \ case _IA64_REG_IP: \ asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \ break; \ case _IA64_REG_PSR: \ asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \ break; \ case _IA64_REG_TP: /* for current() */ \ ia64_intri_res = ia64_r13; \ break; \ case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \ : "i"(regnum - _IA64_REG_AR_KR0)); \ break; \ case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \ : "i" (regnum - _IA64_REG_CR_DCR)); \ break; \ case _IA64_REG_SP: \ asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \ break; \ default: \ ia64_bad_param_for_getreg(); \ break; \ } \ ia64_intri_res; \ }) #define ia64_hint_pause 0 #define ia64_hint(mode) \ ({ \ switch (mode) { \ case ia64_hint_pause: \ asm volatile ("hint @pause" ::: "memory"); \ break; \ } \ }) /* Integer values for mux1 instruction */ #define ia64_mux1_brcst 0 #define ia64_mux1_mix 8 #define ia64_mux1_shuf 9 #define ia64_mux1_alt 10 #define ia64_mux1_rev 11 #define ia64_mux1(x, mode) \ ({ \ __u64 ia64_intri_res; \ \ switch (mode) { \ case ia64_mux1_brcst: \ asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \ break; \ case ia64_mux1_mix: \ asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \ break; \ case ia64_mux1_shuf: \ asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \ break; \ case ia64_mux1_alt: \ asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \ break; \ case ia64_mux1_rev: \ asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \ break; \ } \ ia64_intri_res; \ }) #if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) # define ia64_popcnt(x) __builtin_popcountl(x) #else # define ia64_popcnt(x) \ ({ \ __u64 ia64_intri_res; \ asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ \ ia64_intri_res; \ }) #endif #define ia64_getf_exp(x) \ ({ \ long ia64_intri_res; \ \ asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \ \ ia64_intri_res; \ }) #define ia64_shrp(a, b, count) \ ({ \ __u64 ia64_intri_res; \ asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \ ia64_intri_res; \ }) #define ia64_ldfs(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldfd(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldfe(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldf8(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldf_fill(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_st4_rel_nta(m, val) \ ({ \ asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \ }) #define ia64_stfs(x, regnum) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) #define ia64_stfd(x, regnum) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) #define ia64_stfe(x, regnum) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) #define ia64_stf8(x, regnum) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) #define ia64_stf_spill(x, regnum) \ ({ \ register double __f__ asm ("f"#regnum); \ asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) #define ia64_fetchadd4_acq(p, inc) \ ({ \ \ __u64 ia64_intri_res; \ asm volatile ("fetchadd4.acq %0=[%1],%2" \ : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ : "memory"); \ \ ia64_intri_res; \ }) #define ia64_fetchadd4_rel(p, inc) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("fetchadd4.rel %0=[%1],%2" \ : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ : "memory"); \ \ ia64_intri_res; \ }) #define ia64_fetchadd8_acq(p, inc) \ ({ \ \ __u64 ia64_intri_res; \ asm volatile ("fetchadd8.acq %0=[%1],%2" \ : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ : "memory"); \ \ ia64_intri_res; \ }) #define ia64_fetchadd8_rel(p, inc) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("fetchadd8.rel %0=[%1],%2" \ : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ : "memory"); \ \ ia64_intri_res; \ }) #define ia64_xchg1(ptr,x) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("xchg1 %0=[%1],%2" \ : "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) #define ia64_xchg2(ptr,x) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \ : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) #define ia64_xchg4(ptr,x) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \ : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) #define ia64_xchg8(ptr,x) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \ : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg1_acq(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg1_rel(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg2_acq(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg2_rel(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ \ asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg4_acq(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg4_rel(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg8_acq(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_cmpxchg8_rel(ptr, new, old) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ \ asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \ "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ ia64_intri_res; \ }) #define ia64_mf() asm volatile ("mf" ::: "memory") #define ia64_mfa() asm volatile ("mf.a" ::: "memory") #define ia64_invala() asm volatile ("invala" ::: "memory") #define ia64_thash(addr) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \ ia64_intri_res; \ }) #define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory") #define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory"); #ifdef HAVE_SERIALIZE_DIRECTIVE # define ia64_dv_serialize_data() asm volatile (".serialize.data"); # define ia64_dv_serialize_instruction() asm volatile (".serialize.instruction"); #else # define ia64_dv_serialize_data() # define ia64_dv_serialize_instruction() #endif #define ia64_nop(x) asm volatile ("nop %0"::"i"(x)); #define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory") #define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory") #define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1" \ :: "r"(trnum), "r"(addr) : "memory") #define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1" \ :: "r"(trnum), "r"(addr) : "memory") #define ia64_tpa(addr) \ ({ \ unsigned long ia64_pa; \ asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \ ia64_pa; \ }) #define __ia64_set_dbr(index, val) \ asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory") #define ia64_set_ibr(index, val) \ asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory") #define ia64_set_pkr(index, val) \ asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory") #define ia64_set_pmc(index, val) \ asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory") #define ia64_set_pmd(index, val) \ asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory") #define ia64_set_rr(index, val) \ asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory"); #define ia64_get_cpuid(index) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \ ia64_intri_res; \ }) #define __ia64_get_dbr(index) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ ia64_intri_res; \ }) #define ia64_get_ibr(index) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ ia64_intri_res; \ }) #define ia64_get_pkr(index) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ ia64_intri_res; \ }) #define ia64_get_pmc(index) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ ia64_intri_res; \ }) #define ia64_get_pmd(index) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ ia64_intri_res; \ }) #define ia64_get_rr(index) \ ({ \ unsigned long ia64_intri_res; \ asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \ ia64_intri_res; \ }) #define ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory") #define ia64_sync_i() asm volatile (";; sync.i" ::: "memory") #define ia64_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory") #define ia64_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory") #define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory") #define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory") #define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr)) #define ia64_ptcga(addr, size) \ do { \ asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \ ia64_dv_serialize_data(); \ } while (0) #define ia64_ptcl(addr, size) \ do { \ asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory"); \ ia64_dv_serialize_data(); \ } while (0) #define ia64_ptri(addr, size) \ asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory") #define ia64_ptrd(addr, size) \ asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory") #define ia64_ttag(addr) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \ ia64_intri_res; \ }) /* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */ #define ia64_lfhint_none 0 #define ia64_lfhint_nt1 1 #define ia64_lfhint_nt2 2 #define ia64_lfhint_nta 3 #define ia64_lfetch(lfhint, y) \ ({ \ switch (lfhint) { \ case ia64_lfhint_none: \ asm volatile ("lfetch [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nt1: \ asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nt2: \ asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nta: \ asm volatile ("lfetch.nta [%0]" : : "r"(y)); \ break; \ } \ }) #define ia64_lfetch_excl(lfhint, y) \ ({ \ switch (lfhint) { \ case ia64_lfhint_none: \ asm volatile ("lfetch.excl [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt1: \ asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt2: \ asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nta: \ asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \ break; \ } \ }) #define ia64_lfetch_fault(lfhint, y) \ ({ \ switch (lfhint) { \ case ia64_lfhint_none: \ asm volatile ("lfetch.fault [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nt1: \ asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nt2: \ asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nta: \ asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \ break; \ } \ }) #define ia64_lfetch_fault_excl(lfhint, y) \ ({ \ switch (lfhint) { \ case ia64_lfhint_none: \ asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt1: \ asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt2: \ asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nta: \ asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \ break; \ } \ }) #define ia64_intrin_local_irq_restore(x) \ do { \ asm volatile (";; cmp.ne p6,p7=%0,r0;;" \ "(p6) ssm psr.i;" \ "(p7) rsm psr.i;;" \ "(p6) srlz.d" \ :: "r"((x)) : "p6", "p7", "memory"); \ } while (0) #endif /* _UAPI_ASM_IA64_GCC_INTRIN_H */ PK ! �u�� � termios.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_TERMIOS_H #define _ALPHA_TERMIOS_H #include <uapi/asm/termios.h> /* eof=^D eol=\0 eol2=\0 erase=del werase=^W kill=^U reprint=^R sxtc=\0 intr=^C quit=^\ susp=^Z <OSF/1 VDSUSP> start=^Q stop=^S lnext=^V discard=^U vmin=\1 vtime=\0 */ #define INIT_C_CC "\004\000\000\177\027\025\022\000\003\034\032\000\021\023\026\025\001\000" /* * Translate a "termio" structure into a "termios". Ugh. */ #define user_termio_to_kernel_termios(a_termios, u_termio) \ ({ \ struct ktermios *k_termios = (a_termios); \ struct termio k_termio; \ int canon, ret; \ \ ret = copy_from_user(&k_termio, u_termio, sizeof(k_termio)); \ if (!ret) { \ /* Overwrite only the low bits. */ \ *(unsigned short *)&k_termios->c_iflag = k_termio.c_iflag; \ *(unsigned short *)&k_termios->c_oflag = k_termio.c_oflag; \ *(unsigned short *)&k_termios->c_cflag = k_termio.c_cflag; \ *(unsigned short *)&k_termios->c_lflag = k_termio.c_lflag; \ canon = k_termio.c_lflag & ICANON; \ \ k_termios->c_cc[VINTR] = k_termio.c_cc[_VINTR]; \ k_termios->c_cc[VQUIT] = k_termio.c_cc[_VQUIT]; \ k_termios->c_cc[VERASE] = k_termio.c_cc[_VERASE]; \ k_termios->c_cc[VKILL] = k_termio.c_cc[_VKILL]; \ k_termios->c_cc[VEOL2] = k_termio.c_cc[_VEOL2]; \ k_termios->c_cc[VSWTC] = k_termio.c_cc[_VSWTC]; \ k_termios->c_cc[canon ? VEOF : VMIN] = k_termio.c_cc[_VEOF]; \ k_termios->c_cc[canon ? VEOL : VTIME] = k_termio.c_cc[_VEOL]; \ } \ ret; \ }) /* * Translate a "termios" structure into a "termio". Ugh. * * Note the "fun" _VMIN overloading. */ #define kernel_termios_to_user_termio(u_termio, a_termios) \ ({ \ struct ktermios *k_termios = (a_termios); \ struct termio k_termio; \ int canon; \ \ k_termio.c_iflag = k_termios->c_iflag; \ k_termio.c_oflag = k_termios->c_oflag; \ k_termio.c_cflag = k_termios->c_cflag; \ canon = (k_termio.c_lflag = k_termios->c_lflag) & ICANON; \ \ k_termio.c_line = k_termios->c_line; \ k_termio.c_cc[_VINTR] = k_termios->c_cc[VINTR]; \ k_termio.c_cc[_VQUIT] = k_termios->c_cc[VQUIT]; \ k_termio.c_cc[_VERASE] = k_termios->c_cc[VERASE]; \ k_termio.c_cc[_VKILL] = k_termios->c_cc[VKILL]; \ k_termio.c_cc[_VEOF] = k_termios->c_cc[canon ? VEOF : VMIN]; \ k_termio.c_cc[_VEOL] = k_termios->c_cc[canon ? VEOL : VTIME]; \ k_termio.c_cc[_VEOL2] = k_termios->c_cc[VEOL2]; \ k_termio.c_cc[_VSWTC] = k_termios->c_cc[VSWTC]; \ \ copy_to_user(u_termio, &k_termio, sizeof(k_termio)); \ }) #define user_termios_to_kernel_termios(k, u) \ copy_from_user(k, u, sizeof(struct termios2)) #define kernel_termios_to_user_termios(u, k) \ copy_to_user(u, k, sizeof(struct termios2)) #define user_termios_to_kernel_termios_1(k, u) \ copy_from_user(k, u, sizeof(struct termios)) #define kernel_termios_to_user_termios_1(u, k) \ copy_to_user(u, k, sizeof(struct termios)) #endif /* _ALPHA_TERMIOS_H */ PK ! �K�?( ( ustack.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPI_ASM_IA64_USTACK_H #define _UAPI_ASM_IA64_USTACK_H /* * Constants for the user stack size */ /* Make a default stack size of 2GiB */ #define DEFAULT_USER_STACK_SIZE (1UL << 31) #endif /* _UAPI_ASM_IA64_USTACK_H */ PK ! �s��� � fcntl.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_FCNTL_H #define _ASM_IA64_FCNTL_H /* * Modified 1998-2000 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co. */ #define force_o_largefile() \ (personality(current->personality) != PER_LINUX32) #include <linux/personality.h> #include <asm-generic/fcntl.h> #endif /* _ASM_IA64_FCNTL_H */ PK ! �x; ; ia64regs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright (C) 2002,2003 Intel Corp. * Jun Nakajima <jun.nakajima@intel.com> * Suresh Siddha <suresh.b.siddha@intel.com> */ #ifndef _ASM_IA64_IA64REGS_H #define _ASM_IA64_IA64REGS_H /* * Register Names for getreg() and setreg(). * * The "magic" numbers happen to match the values used by the Intel compiler's * getreg()/setreg() intrinsics. */ /* Special Registers */ #define _IA64_REG_IP 1016 /* getreg only */ #define _IA64_REG_PSR 1019 #define _IA64_REG_PSR_L 1019 /* General Integer Registers */ #define _IA64_REG_GP 1025 /* R1 */ #define _IA64_REG_R8 1032 /* R8 */ #define _IA64_REG_R9 1033 /* R9 */ #define _IA64_REG_SP 1036 /* R12 */ #define _IA64_REG_TP 1037 /* R13 */ /* Application Registers */ #define _IA64_REG_AR_KR0 3072 #define _IA64_REG_AR_KR1 3073 #define _IA64_REG_AR_KR2 3074 #define _IA64_REG_AR_KR3 3075 #define _IA64_REG_AR_KR4 3076 #define _IA64_REG_AR_KR5 3077 #define _IA64_REG_AR_KR6 3078 #define _IA64_REG_AR_KR7 3079 #define _IA64_REG_AR_RSC 3088 #define _IA64_REG_AR_BSP 3089 #define _IA64_REG_AR_BSPSTORE 3090 #define _IA64_REG_AR_RNAT 3091 #define _IA64_REG_AR_FCR 3093 #define _IA64_REG_AR_EFLAG 3096 #define _IA64_REG_AR_CSD 3097 #define _IA64_REG_AR_SSD 3098 #define _IA64_REG_AR_CFLAG 3099 #define _IA64_REG_AR_FSR 3100 #define _IA64_REG_AR_FIR 3101 #define _IA64_REG_AR_FDR 3102 #define _IA64_REG_AR_CCV 3104 #define _IA64_REG_AR_UNAT 3108 #define _IA64_REG_AR_FPSR 3112 #define _IA64_REG_AR_ITC 3116 #define _IA64_REG_AR_PFS 3136 #define _IA64_REG_AR_LC 3137 #define _IA64_REG_AR_EC 3138 /* Control Registers */ #define _IA64_REG_CR_DCR 4096 #define _IA64_REG_CR_ITM 4097 #define _IA64_REG_CR_IVA 4098 #define _IA64_REG_CR_PTA 4104 #define _IA64_REG_CR_IPSR 4112 #define _IA64_REG_CR_ISR 4113 #define _IA64_REG_CR_IIP 4115 #define _IA64_REG_CR_IFA 4116 #define _IA64_REG_CR_ITIR 4117 #define _IA64_REG_CR_IIPA 4118 #define _IA64_REG_CR_IFS 4119 #define _IA64_REG_CR_IIM 4120 #define _IA64_REG_CR_IHA 4121 #define _IA64_REG_CR_LID 4160 #define _IA64_REG_CR_IVR 4161 /* getreg only */ #define _IA64_REG_CR_TPR 4162 #define _IA64_REG_CR_EOI 4163 #define _IA64_REG_CR_IRR0 4164 /* getreg only */ #define _IA64_REG_CR_IRR1 4165 /* getreg only */ #define _IA64_REG_CR_IRR2 4166 /* getreg only */ #define _IA64_REG_CR_IRR3 4167 /* getreg only */ #define _IA64_REG_CR_ITV 4168 #define _IA64_REG_CR_PMV 4169 #define _IA64_REG_CR_CMCV 4170 #define _IA64_REG_CR_LRR0 4176 #define _IA64_REG_CR_LRR1 4177 /* Indirect Registers for getindreg() and setindreg() */ #define _IA64_REG_INDR_CPUID 9000 /* getindreg only */ #define _IA64_REG_INDR_DBR 9001 #define _IA64_REG_INDR_IBR 9002 #define _IA64_REG_INDR_PKR 9003 #define _IA64_REG_INDR_PMC 9004 #define _IA64_REG_INDR_PMD 9005 #define _IA64_REG_INDR_RR 9006 #endif /* _ASM_IA64_IA64REGS_H */ PK ! ��̳� � ptrace_offsets.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_PTRACE_OFFSETS_H #define _ASM_IA64_PTRACE_OFFSETS_H /* * Copyright (C) 1999, 2003 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> */ /* * The "uarea" that can be accessed via PEEKUSER and POKEUSER is a * virtual structure that would have the following definition: * * struct uarea { * struct ia64_fpreg fph[96]; // f32-f127 * unsigned long nat_bits; * unsigned long empty1; * struct ia64_fpreg f2; // f2-f5 * : * struct ia64_fpreg f5; * struct ia64_fpreg f10; // f10-f31 * : * struct ia64_fpreg f31; * unsigned long r4; // r4-r7 * : * unsigned long r7; * unsigned long b1; // b1-b5 * : * unsigned long b5; * unsigned long ar_ec; * unsigned long ar_lc; * unsigned long empty2[5]; * unsigned long cr_ipsr; * unsigned long cr_iip; * unsigned long cfm; * unsigned long ar_unat; * unsigned long ar_pfs; * unsigned long ar_rsc; * unsigned long ar_rnat; * unsigned long ar_bspstore; * unsigned long pr; * unsigned long b6; * unsigned long ar_bsp; * unsigned long r1; * unsigned long r2; * unsigned long r3; * unsigned long r12; * unsigned long r13; * unsigned long r14; * unsigned long r15; * unsigned long r8; * unsigned long r9; * unsigned long r10; * unsigned long r11; * unsigned long r16; * : * unsigned long r31; * unsigned long ar_ccv; * unsigned long ar_fpsr; * unsigned long b0; * unsigned long b7; * unsigned long f6; * unsigned long f7; * unsigned long f8; * unsigned long f9; * unsigned long ar_csd; * unsigned long ar_ssd; * unsigned long rsvd1[710]; * unsigned long dbr[8]; * unsigned long rsvd2[504]; * unsigned long ibr[8]; * unsigned long rsvd3[504]; * unsigned long pmd[4]; * } */ /* fph: */ #define PT_F32 0x0000 #define PT_F33 0x0010 #define PT_F34 0x0020 #define PT_F35 0x0030 #define PT_F36 0x0040 #define PT_F37 0x0050 #define PT_F38 0x0060 #define PT_F39 0x0070 #define PT_F40 0x0080 #define PT_F41 0x0090 #define PT_F42 0x00a0 #define PT_F43 0x00b0 #define PT_F44 0x00c0 #define PT_F45 0x00d0 #define PT_F46 0x00e0 #define PT_F47 0x00f0 #define PT_F48 0x0100 #define PT_F49 0x0110 #define PT_F50 0x0120 #define PT_F51 0x0130 #define PT_F52 0x0140 #define PT_F53 0x0150 #define PT_F54 0x0160 #define PT_F55 0x0170 #define PT_F56 0x0180 #define PT_F57 0x0190 #define PT_F58 0x01a0 #define PT_F59 0x01b0 #define PT_F60 0x01c0 #define PT_F61 0x01d0 #define PT_F62 0x01e0 #define PT_F63 0x01f0 #define PT_F64 0x0200 #define PT_F65 0x0210 #define PT_F66 0x0220 #define PT_F67 0x0230 #define PT_F68 0x0240 #define PT_F69 0x0250 #define PT_F70 0x0260 #define PT_F71 0x0270 #define PT_F72 0x0280 #define PT_F73 0x0290 #define PT_F74 0x02a0 #define PT_F75 0x02b0 #define PT_F76 0x02c0 #define PT_F77 0x02d0 #define PT_F78 0x02e0 #define PT_F79 0x02f0 #define PT_F80 0x0300 #define PT_F81 0x0310 #define PT_F82 0x0320 #define PT_F83 0x0330 #define PT_F84 0x0340 #define PT_F85 0x0350 #define PT_F86 0x0360 #define PT_F87 0x0370 #define PT_F88 0x0380 #define PT_F89 0x0390 #define PT_F90 0x03a0 #define PT_F91 0x03b0 #define PT_F92 0x03c0 #define PT_F93 0x03d0 #define PT_F94 0x03e0 #define PT_F95 0x03f0 #define PT_F96 0x0400 #define PT_F97 0x0410 #define PT_F98 0x0420 #define PT_F99 0x0430 #define PT_F100 0x0440 #define PT_F101 0x0450 #define PT_F102 0x0460 #define PT_F103 0x0470 #define PT_F104 0x0480 #define PT_F105 0x0490 #define PT_F106 0x04a0 #define PT_F107 0x04b0 #define PT_F108 0x04c0 #define PT_F109 0x04d0 #define PT_F110 0x04e0 #define PT_F111 0x04f0 #define PT_F112 0x0500 #define PT_F113 0x0510 #define PT_F114 0x0520 #define PT_F115 0x0530 #define PT_F116 0x0540 #define PT_F117 0x0550 #define PT_F118 0x0560 #define PT_F119 0x0570 #define PT_F120 0x0580 #define PT_F121 0x0590 #define PT_F122 0x05a0 #define PT_F123 0x05b0 #define PT_F124 0x05c0 #define PT_F125 0x05d0 #define PT_F126 0x05e0 #define PT_F127 0x05f0 #define PT_NAT_BITS 0x0600 #define PT_F2 0x0610 #define PT_F3 0x0620 #define PT_F4 0x0630 #define PT_F5 0x0640 #define PT_F10 0x0650 #define PT_F11 0x0660 #define PT_F12 0x0670 #define PT_F13 0x0680 #define PT_F14 0x0690 #define PT_F15 0x06a0 #define PT_F16 0x06b0 #define PT_F17 0x06c0 #define PT_F18 0x06d0 #define PT_F19 0x06e0 #define PT_F20 0x06f0 #define PT_F21 0x0700 #define PT_F22 0x0710 #define PT_F23 0x0720 #define PT_F24 0x0730 #define PT_F25 0x0740 #define PT_F26 0x0750 #define PT_F27 0x0760 #define PT_F28 0x0770 #define PT_F29 0x0780 #define PT_F30 0x0790 #define PT_F31 0x07a0 #define PT_R4 0x07b0 #define PT_R5 0x07b8 #define PT_R6 0x07c0 #define PT_R7 0x07c8 #define PT_B1 0x07d8 #define PT_B2 0x07e0 #define PT_B3 0x07e8 #define PT_B4 0x07f0 #define PT_B5 0x07f8 #define PT_AR_EC 0x0800 #define PT_AR_LC 0x0808 #define PT_CR_IPSR 0x0830 #define PT_CR_IIP 0x0838 #define PT_CFM 0x0840 #define PT_AR_UNAT 0x0848 #define PT_AR_PFS 0x0850 #define PT_AR_RSC 0x0858 #define PT_AR_RNAT 0x0860 #define PT_AR_BSPSTORE 0x0868 #define PT_PR 0x0870 #define PT_B6 0x0878 #define PT_AR_BSP 0x0880 /* note: this points to the *end* of the backing store! */ #define PT_R1 0x0888 #define PT_R2 0x0890 #define PT_R3 0x0898 #define PT_R12 0x08a0 #define PT_R13 0x08a8 #define PT_R14 0x08b0 #define PT_R15 0x08b8 #define PT_R8 0x08c0 #define PT_R9 0x08c8 #define PT_R10 0x08d0 #define PT_R11 0x08d8 #define PT_R16 0x08e0 #define PT_R17 0x08e8 #define PT_R18 0x08f0 #define PT_R19 0x08f8 #define PT_R20 0x0900 #define PT_R21 0x0908 #define PT_R22 0x0910 #define PT_R23 0x0918 #define PT_R24 0x0920 #define PT_R25 0x0928 #define PT_R26 0x0930 #define PT_R27 0x0938 #define PT_R28 0x0940 #define PT_R29 0x0948 #define PT_R30 0x0950 #define PT_R31 0x0958 #define PT_AR_CCV 0x0960 #define PT_AR_FPSR 0x0968 #define PT_B0 0x0970 #define PT_B7 0x0978 #define PT_F6 0x0980 #define PT_F7 0x0990 #define PT_F8 0x09a0 #define PT_F9 0x09b0 #define PT_AR_CSD 0x09c0 #define PT_AR_SSD 0x09c8 #define PT_DBR 0x2000 /* data breakpoint registers */ #define PT_IBR 0x3000 /* instruction breakpoint registers */ #define PT_PMD 0x4000 /* performance monitoring counters */ #endif /* _ASM_IA64_PTRACE_OFFSETS_H */ PK ! �h$�\ \ ucontext.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASMAXP_UCONTEXT_H #define _ASMAXP_UCONTEXT_H struct ucontext { unsigned long uc_flags; struct ucontext *uc_link; old_sigset_t uc_osf_sigmask; stack_t uc_stack; struct sigcontext uc_mcontext; sigset_t uc_sigmask; /* mask last for extensibility */ }; #endif /* !_ASMAXP_UCONTEXT_H */ PK ! H��$@ @ intrinsics.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Compiler-dependent intrinsics. * * Copyright (C) 2002-2003 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> */ #ifndef _UAPI_ASM_IA64_INTRINSICS_H #define _UAPI_ASM_IA64_INTRINSICS_H #ifndef __ASSEMBLY__ #include <linux/types.h> /* include compiler specific intrinsics */ #include <asm/ia64regs.h> #ifdef __INTEL_COMPILER # include <asm/intel_intrin.h> #else # include <asm/gcc_intrin.h> #endif #include <asm/cmpxchg.h> #define ia64_set_rr0_to_rr4(val0, val1, val2, val3, val4) \ do { \ ia64_set_rr(0x0000000000000000UL, (val0)); \ ia64_set_rr(0x2000000000000000UL, (val1)); \ ia64_set_rr(0x4000000000000000UL, (val2)); \ ia64_set_rr(0x6000000000000000UL, (val3)); \ ia64_set_rr(0x8000000000000000UL, (val4)); \ } while (0) /* * Force an unresolved reference if someone tries to use * ia64_fetch_and_add() with a bad value. */ extern unsigned long __bad_size_for_ia64_fetch_and_add (void); extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); #define IA64_FETCHADD(tmp,v,n,sz,sem) \ ({ \ switch (sz) { \ case 4: \ tmp = ia64_fetchadd4_##sem((unsigned int *) v, n); \ break; \ \ case 8: \ tmp = ia64_fetchadd8_##sem((unsigned long *) v, n); \ break; \ \ default: \ __bad_size_for_ia64_fetch_and_add(); \ } \ }) #define ia64_fetchadd(i,v,sem) \ ({ \ __u64 _tmp; \ volatile __typeof__(*(v)) *_v = (v); \ /* Can't use a switch () here: gcc isn't always smart enough for that... */ \ if ((i) == -16) \ IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v)), sem); \ else if ((i) == -8) \ IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v)), sem); \ else if ((i) == -4) \ IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v)), sem); \ else if ((i) == -1) \ IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v)), sem); \ else if ((i) == 1) \ IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v)), sem); \ else if ((i) == 4) \ IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v)), sem); \ else if ((i) == 8) \ IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v)), sem); \ else if ((i) == 16) \ IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v)), sem); \ else \ _tmp = __bad_increment_for_ia64_fetch_and_add(); \ (__typeof__(*(v))) (_tmp); /* return old value */ \ }) #define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */ #endif #endif /* _UAPI_ASM_IA64_INTRINSICS_H */ PK ! -l�y y bitsperlong.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Copyright (C) 2012 ARM Ltd. * Copyright (C) 2015 Regents of the University of California */ #ifndef _UAPI_ASM_RISCV_BITSPERLONG_H #define _UAPI_ASM_RISCV_BITSPERLONG_H #define __BITS_PER_LONG (__SIZEOF_POINTER__ * 8) #include <asm-generic/bitsperlong.h> #endif /* _UAPI_ASM_RISCV_BITSPERLONG_H */ PK ! ˡ��" " intel_intrin.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_INTEL_INTRIN_H #define _ASM_IA64_INTEL_INTRIN_H /* * Intel Compiler Intrinsics * * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com> * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com> * Copyright (C) 2005,2006 Hongjiu Lu <hongjiu.lu@intel.com> * */ #include <ia64intrin.h> #define ia64_barrier() __memory_barrier() #define ia64_stop() /* Nothing: As of now stop bit is generated for each * intrinsic */ #define ia64_getreg __getReg #define ia64_setreg __setReg #define ia64_hint __hint #define ia64_hint_pause __hint_pause #define ia64_mux1_brcst _m64_mux1_brcst #define ia64_mux1_mix _m64_mux1_mix #define ia64_mux1_shuf _m64_mux1_shuf #define ia64_mux1_alt _m64_mux1_alt #define ia64_mux1_rev _m64_mux1_rev #define ia64_mux1(x,v) _m_to_int64(_m64_mux1(_m_from_int64(x), (v))) #define ia64_popcnt _m64_popcnt #define ia64_getf_exp __getf_exp #define ia64_shrp _m64_shrp #define ia64_tpa __tpa #define ia64_invala __invala #define ia64_invala_gr __invala_gr #define ia64_invala_fr __invala_fr #define ia64_nop __nop #define ia64_sum __sum #define ia64_ssm __ssm #define ia64_rum __rum #define ia64_rsm __rsm #define ia64_fc __fc #define ia64_ldfs __ldfs #define ia64_ldfd __ldfd #define ia64_ldfe __ldfe #define ia64_ldf8 __ldf8 #define ia64_ldf_fill __ldf_fill #define ia64_stfs __stfs #define ia64_stfd __stfd #define ia64_stfe __stfe #define ia64_stf8 __stf8 #define ia64_stf_spill __stf_spill #define ia64_mf __mf #define ia64_mfa __mfa #define ia64_fetchadd4_acq __fetchadd4_acq #define ia64_fetchadd4_rel __fetchadd4_rel #define ia64_fetchadd8_acq __fetchadd8_acq #define ia64_fetchadd8_rel __fetchadd8_rel #define ia64_xchg1 _InterlockedExchange8 #define ia64_xchg2 _InterlockedExchange16 #define ia64_xchg4 _InterlockedExchange #define ia64_xchg8 _InterlockedExchange64 #define ia64_cmpxchg1_rel _InterlockedCompareExchange8_rel #define ia64_cmpxchg1_acq _InterlockedCompareExchange8_acq #define ia64_cmpxchg2_rel _InterlockedCompareExchange16_rel #define ia64_cmpxchg2_acq _InterlockedCompareExchange16_acq #define ia64_cmpxchg4_rel _InterlockedCompareExchange_rel #define ia64_cmpxchg4_acq _InterlockedCompareExchange_acq #define ia64_cmpxchg8_rel _InterlockedCompareExchange64_rel #define ia64_cmpxchg8_acq _InterlockedCompareExchange64_acq #define __ia64_set_dbr(index, val) \ __setIndReg(_IA64_REG_INDR_DBR, index, val) #define ia64_set_ibr(index, val) \ __setIndReg(_IA64_REG_INDR_IBR, index, val) #define ia64_set_pkr(index, val) \ __setIndReg(_IA64_REG_INDR_PKR, index, val) #define ia64_set_pmc(index, val) \ __setIndReg(_IA64_REG_INDR_PMC, index, val) #define ia64_set_pmd(index, val) \ __setIndReg(_IA64_REG_INDR_PMD, index, val) #define ia64_set_rr(index, val) \ __setIndReg(_IA64_REG_INDR_RR, index, val) #define ia64_get_cpuid(index) \ __getIndReg(_IA64_REG_INDR_CPUID, index) #define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index) #define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index) #define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index) #define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index) #define ia64_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index) #define ia64_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index) #define ia64_srlz_d __dsrlz #define ia64_srlz_i __isrlz #define ia64_dv_serialize_data() #define ia64_dv_serialize_instruction() #define ia64_st1_rel __st1_rel #define ia64_st2_rel __st2_rel #define ia64_st4_rel __st4_rel #define ia64_st8_rel __st8_rel /* FIXME: need st4.rel.nta intrinsic */ #define ia64_st4_rel_nta __st4_rel #define ia64_ld1_acq __ld1_acq #define ia64_ld2_acq __ld2_acq #define ia64_ld4_acq __ld4_acq #define ia64_ld8_acq __ld8_acq #define ia64_sync_i __synci #define ia64_thash __thash #define ia64_ttag __ttag #define ia64_itcd __itcd #define ia64_itci __itci #define ia64_itrd __itrd #define ia64_itri __itri #define ia64_ptce __ptce #define ia64_ptcl __ptcl #define ia64_ptcg __ptcg #define ia64_ptcga __ptcga #define ia64_ptri __ptri #define ia64_ptrd __ptrd #define ia64_dep_mi _m64_dep_mi /* Values for lfhint in __lfetch and __lfetch_fault */ #define ia64_lfhint_none __lfhint_none #define ia64_lfhint_nt1 __lfhint_nt1 #define ia64_lfhint_nt2 __lfhint_nt2 #define ia64_lfhint_nta __lfhint_nta #define ia64_lfetch __lfetch #define ia64_lfetch_excl __lfetch_excl #define ia64_lfetch_fault __lfetch_fault #define ia64_lfetch_fault_excl __lfetch_fault_excl #define ia64_intrin_local_irq_restore(x) \ do { \ if ((x) != 0) { \ ia64_ssm(IA64_PSR_I); \ ia64_srlz_d(); \ } else { \ ia64_rsm(IA64_PSR_I); \ } \ } while (0) #define __builtin_trap() __break(0); #endif /* _ASM_IA64_INTEL_INTRIN_H */ PK ! tX��� � resource.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_RESOURCE_H #define _ASM_IA64_RESOURCE_H #include <asm/ustack.h> #include <asm-generic/resource.h> #endif /* _ASM_IA64_RESOURCE_H */ PK ! >�V�� � siginfo.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Based on <asm-i386/siginfo.h>. * * Modified 1998-2002 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co */ #ifndef _UAPI_ASM_IA64_SIGINFO_H #define _UAPI_ASM_IA64_SIGINFO_H #include <asm-generic/siginfo.h> #define si_imm _sifields._sigfault._imm /* as per UNIX SysV ABI spec */ #define si_flags _sifields._sigfault._flags /* * si_isr is valid for SIGILL, SIGFPE, SIGSEGV, SIGBUS, and SIGTRAP provided that * si_code is non-zero and __ISR_VALID is set in si_flags. */ #define si_isr _sifields._sigfault._isr /* * Flag values for si_flags: */ #define __ISR_VALID_BIT 0 #define __ISR_VALID (1 << __ISR_VALID_BIT) #endif /* _UAPI_ASM_IA64_SIGINFO_H */ PK ! '��� fpu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_ALPHA_FPU_H #define __ASM_ALPHA_FPU_H #include <asm/special_insns.h> #include <uapi/asm/fpu.h> /* The following two functions don't need trapb/excb instructions around the mf_fpcr/mt_fpcr instructions because (a) the kernel never generates arithmetic faults and (b) call_pal instructions are implied trap barriers. */ static inline unsigned long rdfpcr(void) { unsigned long tmp, ret; #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67) __asm__ __volatile__ ( "ftoit $f0,%0\n\t" "mf_fpcr $f0\n\t" "ftoit $f0,%1\n\t" "itoft %0,$f0" : "=r"(tmp), "=r"(ret)); #else __asm__ __volatile__ ( "stt $f0,%0\n\t" "mf_fpcr $f0\n\t" "stt $f0,%1\n\t" "ldt $f0,%0" : "=m"(tmp), "=m"(ret)); #endif return ret; } static inline void wrfpcr(unsigned long val) { unsigned long tmp; #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67) __asm__ __volatile__ ( "ftoit $f0,%0\n\t" "itoft %1,$f0\n\t" "mt_fpcr $f0\n\t" "itoft %0,$f0" : "=&r"(tmp) : "r"(val)); #else __asm__ __volatile__ ( "stt $f0,%0\n\t" "ldt $f0,%1\n\t" "mt_fpcr $f0\n\t" "ldt $f0,%0" : "=m"(tmp) : "m"(val)); #endif } static inline unsigned long swcr_update_status(unsigned long swcr, unsigned long fpcr) { /* EV6 implements most of the bits in hardware. Collect the acrued exception bits from the real fpcr. */ if (implver() == IMPLVER_EV6) { swcr &= ~IEEE_STATUS_MASK; swcr |= (fpcr >> 35) & IEEE_STATUS_MASK; } return swcr; } extern unsigned long alpha_read_fp_reg (unsigned long reg); extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); extern unsigned long alpha_read_fp_reg_s (unsigned long reg); extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); #endif /* __ASM_ALPHA_FPU_H */ PK ! �ˎ+ + statfs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_IA64_STATFS_H #define _ASM_IA64_STATFS_H /* * Based on <asm-i386/statfs.h>. * * Modified 1998, 1999, 2003 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co */ /* * We need compat_statfs64 to be packed, because the i386 ABI won't * add padding at the end to bring it to a multiple of 8 bytes, but * the IA64 ABI will. */ #define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4))) #include <asm-generic/statfs.h> #endif /* _ASM_IA64_STATFS_H */ PK ! ���G� � runtime_instr.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _S390_UAPI_RUNTIME_INSTR_H #define _S390_UAPI_RUNTIME_INSTR_H #include <linux/types.h> #define S390_RUNTIME_INSTR_START 0x1 #define S390_RUNTIME_INSTR_STOP 0x2 struct runtime_instr_cb { __u64 rca; __u64 roa; __u64 rla; __u32 v : 1; __u32 s : 1; __u32 k : 1; __u32 h : 1; __u32 a : 1; __u32 reserved1 : 3; __u32 ps : 1; __u32 qs : 1; __u32 pc : 1; __u32 qc : 1; __u32 reserved2 : 1; __u32 g : 1; __u32 u : 1; __u32 l : 1; __u32 key : 4; __u32 reserved3 : 8; __u32 t : 1; __u32 rgs : 3; __u32 m : 4; __u32 n : 1; __u32 mae : 1; __u32 reserved4 : 2; __u32 c : 1; __u32 r : 1; __u32 b : 1; __u32 j : 1; __u32 e : 1; __u32 x : 1; __u32 reserved5 : 2; __u32 bpxn : 1; __u32 bpxt : 1; __u32 bpti : 1; __u32 bpni : 1; __u32 reserved6 : 2; __u32 d : 1; __u32 f : 1; __u32 ic : 4; __u32 dc : 4; __u64 reserved7; __u64 sf; __u64 rsic; __u64 reserved8; } __attribute__((__packed__, __aligned__(8))); static inline void load_runtime_instr_cb(struct runtime_instr_cb *cb) { asm volatile(".insn rsy,0xeb0000000060,0,0,%0" /* LRIC */ : : "Q" (*cb)); } static inline void store_runtime_instr_cb(struct runtime_instr_cb *cb) { asm volatile(".insn rsy,0xeb0000000061,0,0,%0" /* STRIC */ : "=Q" (*cb) : : "cc"); } #endif /* _S390_UAPI_RUNTIME_INSTR_H */ PK ! k��$ �$ sie.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPI_ASM_S390_SIE_H #define _UAPI_ASM_S390_SIE_H #define diagnose_codes \ { 0x10, "DIAG (0x10) release pages" }, \ { 0x44, "DIAG (0x44) time slice end" }, \ { 0x9c, "DIAG (0x9c) time slice end directed" }, \ { 0x204, "DIAG (0x204) logical-cpu utilization" }, \ { 0x258, "DIAG (0x258) page-reference services" }, \ { 0x288, "DIAG (0x288) watchdog functions" }, \ { 0x308, "DIAG (0x308) ipl functions" }, \ { 0x500, "DIAG (0x500) KVM virtio functions" }, \ { 0x501, "DIAG (0x501) KVM breakpoint" } #define sigp_order_codes \ { 0x01, "SIGP sense" }, \ { 0x02, "SIGP external call" }, \ { 0x03, "SIGP emergency signal" }, \ { 0x04, "SIGP start" }, \ { 0x05, "SIGP stop" }, \ { 0x06, "SIGP restart" }, \ { 0x09, "SIGP stop and store status" }, \ { 0x0b, "SIGP initial cpu reset" }, \ { 0x0c, "SIGP cpu reset" }, \ { 0x0d, "SIGP set prefix" }, \ { 0x0e, "SIGP store status at address" }, \ { 0x12, "SIGP set architecture" }, \ { 0x13, "SIGP conditional emergency signal" }, \ { 0x15, "SIGP sense running" }, \ { 0x16, "SIGP set multithreading"}, \ { 0x17, "SIGP store additional status at address"} #define icpt_prog_codes \ { 0x0001, "Prog Operation" }, \ { 0x0002, "Prog Privileged Operation" }, \ { 0x0003, "Prog Execute" }, \ { 0x0004, "Prog Protection" }, \ { 0x0005, "Prog Addressing" }, \ { 0x0006, "Prog Specification" }, \ { 0x0007, "Prog Data" }, \ { 0x0008, "Prog Fixedpoint overflow" }, \ { 0x0009, "Prog Fixedpoint divide" }, \ { 0x000A, "Prog Decimal overflow" }, \ { 0x000B, "Prog Decimal divide" }, \ { 0x000C, "Prog HFP exponent overflow" }, \ { 0x000D, "Prog HFP exponent underflow" }, \ { 0x000E, "Prog HFP significance" }, \ { 0x000F, "Prog HFP divide" }, \ { 0x0010, "Prog Segment translation" }, \ { 0x0011, "Prog Page translation" }, \ { 0x0012, "Prog Translation specification" }, \ { 0x0013, "Prog Special operation" }, \ { 0x0015, "Prog Operand" }, \ { 0x0016, "Prog Trace table" }, \ { 0x0017, "Prog ASNtranslation specification" }, \ { 0x001C, "Prog Spaceswitch event" }, \ { 0x001D, "Prog HFP square root" }, \ { 0x001F, "Prog PCtranslation specification" }, \ { 0x0020, "Prog AFX translation" }, \ { 0x0021, "Prog ASX translation" }, \ { 0x0022, "Prog LX translation" }, \ { 0x0023, "Prog EX translation" }, \ { 0x0024, "Prog Primary authority" }, \ { 0x0025, "Prog Secondary authority" }, \ { 0x0026, "Prog LFXtranslation exception" }, \ { 0x0027, "Prog LSXtranslation exception" }, \ { 0x0028, "Prog ALET specification" }, \ { 0x0029, "Prog ALEN translation" }, \ { 0x002A, "Prog ALE sequence" }, \ { 0x002B, "Prog ASTE validity" }, \ { 0x002C, "Prog ASTE sequence" }, \ { 0x002D, "Prog Extended authority" }, \ { 0x002E, "Prog LSTE sequence" }, \ { 0x002F, "Prog ASTE instance" }, \ { 0x0030, "Prog Stack full" }, \ { 0x0031, "Prog Stack empty" }, \ { 0x0032, "Prog Stack specification" }, \ { 0x0033, "Prog Stack type" }, \ { 0x0034, "Prog Stack operation" }, \ { 0x0039, "Prog Region first translation" }, \ { 0x003A, "Prog Region second translation" }, \ { 0x003B, "Prog Region third translation" }, \ { 0x0040, "Prog Monitor event" }, \ { 0x0080, "Prog PER event" }, \ { 0x0119, "Prog Crypto operation" } #define exit_code_ipa0(ipa0, opcode, mnemonic) \ { (ipa0 << 8 | opcode), #ipa0 " " mnemonic } #define exit_code(opcode, mnemonic) \ { opcode, mnemonic } #define icpt_insn_codes \ exit_code_ipa0(0x01, 0x01, "PR"), \ exit_code_ipa0(0x01, 0x04, "PTFF"), \ exit_code_ipa0(0x01, 0x07, "SCKPF"), \ exit_code_ipa0(0xAA, 0x00, "RINEXT"), \ exit_code_ipa0(0xAA, 0x01, "RION"), \ exit_code_ipa0(0xAA, 0x02, "TRIC"), \ exit_code_ipa0(0xAA, 0x03, "RIOFF"), \ exit_code_ipa0(0xAA, 0x04, "RIEMIT"), \ exit_code_ipa0(0xB2, 0x02, "STIDP"), \ exit_code_ipa0(0xB2, 0x04, "SCK"), \ exit_code_ipa0(0xB2, 0x05, "STCK"), \ exit_code_ipa0(0xB2, 0x06, "SCKC"), \ exit_code_ipa0(0xB2, 0x07, "STCKC"), \ exit_code_ipa0(0xB2, 0x08, "SPT"), \ exit_code_ipa0(0xB2, 0x09, "STPT"), \ exit_code_ipa0(0xB2, 0x0d, "PTLB"), \ exit_code_ipa0(0xB2, 0x10, "SPX"), \ exit_code_ipa0(0xB2, 0x11, "STPX"), \ exit_code_ipa0(0xB2, 0x12, "STAP"), \ exit_code_ipa0(0xB2, 0x14, "SIE"), \ exit_code_ipa0(0xB2, 0x16, "SETR"), \ exit_code_ipa0(0xB2, 0x17, "STETR"), \ exit_code_ipa0(0xB2, 0x18, "PC"), \ exit_code_ipa0(0xB2, 0x20, "SERVC"), \ exit_code_ipa0(0xB2, 0x21, "IPTE"), \ exit_code_ipa0(0xB2, 0x28, "PT"), \ exit_code_ipa0(0xB2, 0x29, "ISKE"), \ exit_code_ipa0(0xB2, 0x2a, "RRBE"), \ exit_code_ipa0(0xB2, 0x2b, "SSKE"), \ exit_code_ipa0(0xB2, 0x2c, "TB"), \ exit_code_ipa0(0xB2, 0x2e, "PGIN"), \ exit_code_ipa0(0xB2, 0x2f, "PGOUT"), \ exit_code_ipa0(0xB2, 0x30, "CSCH"), \ exit_code_ipa0(0xB2, 0x31, "HSCH"), \ exit_code_ipa0(0xB2, 0x32, "MSCH"), \ exit_code_ipa0(0xB2, 0x33, "SSCH"), \ exit_code_ipa0(0xB2, 0x34, "STSCH"), \ exit_code_ipa0(0xB2, 0x35, "TSCH"), \ exit_code_ipa0(0xB2, 0x36, "TPI"), \ exit_code_ipa0(0xB2, 0x37, "SAL"), \ exit_code_ipa0(0xB2, 0x38, "RSCH"), \ exit_code_ipa0(0xB2, 0x39, "STCRW"), \ exit_code_ipa0(0xB2, 0x3a, "STCPS"), \ exit_code_ipa0(0xB2, 0x3b, "RCHP"), \ exit_code_ipa0(0xB2, 0x3c, "SCHM"), \ exit_code_ipa0(0xB2, 0x40, "BAKR"), \ exit_code_ipa0(0xB2, 0x48, "PALB"), \ exit_code_ipa0(0xB2, 0x4c, "TAR"), \ exit_code_ipa0(0xB2, 0x50, "CSP"), \ exit_code_ipa0(0xB2, 0x54, "MVPG"), \ exit_code_ipa0(0xB2, 0x56, "STHYI"), \ exit_code_ipa0(0xB2, 0x58, "BSG"), \ exit_code_ipa0(0xB2, 0x5a, "BSA"), \ exit_code_ipa0(0xB2, 0x5f, "CHSC"), \ exit_code_ipa0(0xB2, 0x74, "SIGA"), \ exit_code_ipa0(0xB2, 0x76, "XSCH"), \ exit_code_ipa0(0xB2, 0x78, "STCKE"), \ exit_code_ipa0(0xB2, 0x7c, "STCKF"), \ exit_code_ipa0(0xB2, 0x7d, "STSI"), \ exit_code_ipa0(0xB2, 0xb0, "STFLE"), \ exit_code_ipa0(0xB2, 0xb1, "STFL"), \ exit_code_ipa0(0xB2, 0xb2, "LPSWE"), \ exit_code_ipa0(0xB2, 0xf8, "TEND"), \ exit_code_ipa0(0xB2, 0xfc, "TABORT"), \ exit_code_ipa0(0xB9, 0x1e, "KMAC"), \ exit_code_ipa0(0xB9, 0x28, "PCKMO"), \ exit_code_ipa0(0xB9, 0x2a, "KMF"), \ exit_code_ipa0(0xB9, 0x2b, "KMO"), \ exit_code_ipa0(0xB9, 0x2d, "KMCTR"), \ exit_code_ipa0(0xB9, 0x2e, "KM"), \ exit_code_ipa0(0xB9, 0x2f, "KMC"), \ exit_code_ipa0(0xB9, 0x3e, "KIMD"), \ exit_code_ipa0(0xB9, 0x3f, "KLMD"), \ exit_code_ipa0(0xB9, 0x8a, "CSPG"), \ exit_code_ipa0(0xB9, 0x8d, "EPSW"), \ exit_code_ipa0(0xB9, 0x8e, "IDTE"), \ exit_code_ipa0(0xB9, 0x8f, "CRDTE"), \ exit_code_ipa0(0xB9, 0x9c, "EQBS"), \ exit_code_ipa0(0xB9, 0xa2, "PTF"), \ exit_code_ipa0(0xB9, 0xab, "ESSA"), \ exit_code_ipa0(0xB9, 0xae, "RRBM"), \ exit_code_ipa0(0xB9, 0xaf, "PFMF"), \ exit_code_ipa0(0xE3, 0x03, "LRAG"), \ exit_code_ipa0(0xE3, 0x13, "LRAY"), \ exit_code_ipa0(0xE3, 0x25, "NTSTG"), \ exit_code_ipa0(0xE5, 0x00, "LASP"), \ exit_code_ipa0(0xE5, 0x01, "TPROT"), \ exit_code_ipa0(0xE5, 0x60, "TBEGIN"), \ exit_code_ipa0(0xE5, 0x61, "TBEGINC"), \ exit_code_ipa0(0xEB, 0x25, "STCTG"), \ exit_code_ipa0(0xEB, 0x2f, "LCTLG"), \ exit_code_ipa0(0xEB, 0x60, "LRIC"), \ exit_code_ipa0(0xEB, 0x61, "STRIC"), \ exit_code_ipa0(0xEB, 0x62, "MRIC"), \ exit_code_ipa0(0xEB, 0x8a, "SQBS"), \ exit_code_ipa0(0xC8, 0x01, "ECTG"), \ exit_code(0x0a, "SVC"), \ exit_code(0x80, "SSM"), \ exit_code(0x82, "LPSW"), \ exit_code(0x83, "DIAG"), \ exit_code(0xae, "SIGP"), \ exit_code(0xac, "STNSM"), \ exit_code(0xad, "STOSM"), \ exit_code(0xb1, "LRA"), \ exit_code(0xb6, "STCTL"), \ exit_code(0xb7, "LCTL"), \ exit_code(0xee, "PLO") #define sie_intercept_code \ { 0x00, "Host interruption" }, \ { 0x04, "Instruction" }, \ { 0x08, "Program interruption" }, \ { 0x0c, "Instruction and program interruption" }, \ { 0x10, "External request" }, \ { 0x14, "External interruption" }, \ { 0x18, "I/O request" }, \ { 0x1c, "Wait state" }, \ { 0x20, "Validity" }, \ { 0x28, "Stop request" }, \ { 0x2c, "Operation exception" }, \ { 0x38, "Partial-execution" }, \ { 0x3c, "I/O interruption" }, \ { 0x40, "I/O instruction" }, \ { 0x48, "Timing subset" } /* * This is the simple interceptable instructions decoder. * * It will be used as userspace interface and it can be used in places * that does not allow to use general decoder functions, * such as trace events declarations. * * Some userspace tools may want to parse this code * and would be confused by switch(), if() and other statements, * but they can understand conditional operator. */ #define INSN_DECODE_IPA0(ipa0, insn, rshift, mask) \ (insn >> 56) == (ipa0) ? \ ((ipa0 << 8) | ((insn >> rshift) & mask)) : #define INSN_DECODE(insn) (insn >> 56) /* * The macro icpt_insn_decoder() takes an intercepted instruction * and returns a key, which can be used to find a mnemonic name * of the instruction in the icpt_insn_codes table. */ #define icpt_insn_decoder(insn) ( \ INSN_DECODE_IPA0(0x01, insn, 48, 0xff) \ INSN_DECODE_IPA0(0xaa, insn, 48, 0x0f) \ INSN_DECODE_IPA0(0xb2, insn, 48, 0xff) \ INSN_DECODE_IPA0(0xb9, insn, 48, 0xff) \ INSN_DECODE_IPA0(0xe3, insn, 48, 0xff) \ INSN_DECODE_IPA0(0xe5, insn, 48, 0xff) \ INSN_DECODE_IPA0(0xeb, insn, 16, 0xff) \ INSN_DECODE_IPA0(0xc8, insn, 48, 0x0f) \ INSN_DECODE(insn)) #endif /* _UAPI_ASM_S390_SIE_H */ PK ! H%v~� � kvm_para.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * User API definitions for paravirtual devices on s390 * * Copyright IBM Corp. 2008 * * Author(s): Christian Borntraeger <borntraeger@de.ibm.com> */ PK ! lb��� � chpid.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright IBM Corp. 2007, 2012 * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com> */ #ifndef _UAPI_ASM_S390_CHPID_H #define _UAPI_ASM_S390_CHPID_H #include <linux/string.h> #include <linux/types.h> #define __MAX_CHPID 255 struct chp_id { __u8 reserved1; __u8 cssid; __u8 reserved2; __u8 id; } __attribute__((packed)); #endif /* _UAPI_ASM_S390_CHPID_H */ PK ! �w� � perf_regs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */ #ifndef _ASM_RISCV_PERF_REGS_H #define _ASM_RISCV_PERF_REGS_H enum perf_event_riscv_regs { PERF_REG_RISCV_PC, PERF_REG_RISCV_RA, PERF_REG_RISCV_SP, PERF_REG_RISCV_GP, PERF_REG_RISCV_TP, PERF_REG_RISCV_T0, PERF_REG_RISCV_T1, PERF_REG_RISCV_T2, PERF_REG_RISCV_S0, PERF_REG_RISCV_S1, PERF_REG_RISCV_A0, PERF_REG_RISCV_A1, PERF_REG_RISCV_A2, PERF_REG_RISCV_A3, PERF_REG_RISCV_A4, PERF_REG_RISCV_A5, PERF_REG_RISCV_A6, PERF_REG_RISCV_A7, PERF_REG_RISCV_S2, PERF_REG_RISCV_S3, PERF_REG_RISCV_S4, PERF_REG_RISCV_S5, PERF_REG_RISCV_S6, PERF_REG_RISCV_S7, PERF_REG_RISCV_S8, PERF_REG_RISCV_S9, PERF_REG_RISCV_S10, PERF_REG_RISCV_S11, PERF_REG_RISCV_T3, PERF_REG_RISCV_T4, PERF_REG_RISCV_T5, PERF_REG_RISCV_T6, PERF_REG_RISCV_MAX, }; #endif /* _ASM_RISCV_PERF_REGS_H */ PK ! �Q8�� � uvdevice.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright IBM Corp. 2022 * Author(s): Steffen Eiden <seiden@linux.ibm.com> */ #ifndef __S390_ASM_UVDEVICE_H #define __S390_ASM_UVDEVICE_H #include <linux/types.h> struct uvio_ioctl_cb { __u32 flags; __u16 uv_rc; /* UV header rc value */ __u16 uv_rrc; /* UV header rrc value */ __u64 argument_addr; /* Userspace address of uvio argument */ __u32 argument_len; __u8 reserved14[0x40 - 0x14]; /* must be zero */ }; #define UVIO_ATT_USER_DATA_LEN 0x100 #define UVIO_ATT_UID_LEN 0x10 struct uvio_attest { __u64 arcb_addr; /* 0x0000 */ __u64 meas_addr; /* 0x0008 */ __u64 add_data_addr; /* 0x0010 */ __u8 user_data[UVIO_ATT_USER_DATA_LEN]; /* 0x0018 */ __u8 config_uid[UVIO_ATT_UID_LEN]; /* 0x0118 */ __u32 arcb_len; /* 0x0128 */ __u32 meas_len; /* 0x012c */ __u32 add_data_len; /* 0x0130 */ __u16 user_data_len; /* 0x0134 */ __u16 reserved136; /* 0x0136 */ }; /* * The following max values define an upper length for the IOCTL in/out buffers. * However, they do not represent the maximum the Ultravisor allows which is * often way smaller. By allowing larger buffer sizes we hopefully do not need * to update the code with every machine update. It is therefore possible for * userspace to request more memory than actually used by kernel/UV. */ #define UVIO_ATT_ARCB_MAX_LEN 0x100000 #define UVIO_ATT_MEASUREMENT_MAX_LEN 0x8000 #define UVIO_ATT_ADDITIONAL_MAX_LEN 0x8000 #define UVIO_DEVICE_NAME "uv" #define UVIO_TYPE_UVC 'u' #define UVIO_IOCTL_ATT _IOWR(UVIO_TYPE_UVC, 0x01, struct uvio_ioctl_cb) #endif /* __S390_ASM_UVDEVICE_H */ PK ! 6�A| | schid.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPIASM_SCHID_H #define _UAPIASM_SCHID_H #include <linux/types.h> #ifndef __ASSEMBLY__ struct subchannel_id { __u32 cssid : 8; __u32 : 4; __u32 m : 1; __u32 ssid : 2; __u32 one : 1; __u32 sch_no : 16; } __attribute__ ((packed, aligned(4))); #endif /* __ASSEMBLY__ */ #endif /* _UAPIASM_SCHID_H */ PK ! �z�+ + kvm.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2013 Cavium, Inc. * Authors: Sanjay Lal <sanjayl@kymasys.com> */ #ifndef __LINUX_KVM_MIPS_H #define __LINUX_KVM_MIPS_H #include <linux/types.h> /* * KVM MIPS specific structures and definitions. * * Some parts derived from the x86 version of this file. */ #define __KVM_HAVE_READONLY_MEM #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 /* * for KVM_GET_REGS and KVM_SET_REGS * * If Config[AT] is zero (32-bit CPU), the register contents are * stored in the lower 32-bits of the struct kvm_regs fields and sign * extended to 64-bits. */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ __u64 gpr[32]; __u64 hi; __u64 lo; __u64 pc; }; /* * for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { }; /* * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various * registers. The id field is broken down as follows: * * bits[63..52] - As per linux/kvm.h * bits[51..32] - Must be zero. * bits[31..16] - Register set. * * Register set = 0: GP registers from kvm_regs (see definitions below). * * Register set = 1: CP0 registers. * bits[15..8] - COP0 register set. * * COP0 register set = 0: Main CP0 registers. * bits[7..3] - Register 'rd' index. * bits[2..0] - Register 'sel' index. * * COP0 register set = 1: MAARs. * bits[7..0] - MAAR index. * * Register set = 2: KVM specific registers (see definitions below). * * Register set = 3: FPU / MSA registers (see definitions below). * * Other sets registers may be added in the future. Each set would * have its own identifier in bits[31..16]. */ #define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL) #define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL) #define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL) #define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL) /* * KVM_REG_MIPS_GP - General purpose registers from kvm_regs. */ #define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0) #define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1) #define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2) #define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3) #define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4) #define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5) #define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6) #define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7) #define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8) #define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9) #define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10) #define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11) #define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12) #define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13) #define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14) #define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15) #define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16) #define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17) #define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18) #define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19) #define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20) #define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21) #define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22) #define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23) #define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24) #define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25) #define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26) #define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27) #define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28) #define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29) #define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30) #define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31) #define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32) #define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33) #define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34) /* * KVM_REG_MIPS_CP0 - Coprocessor 0 registers. */ #define KVM_REG_MIPS_MAAR (KVM_REG_MIPS_CP0 | (1 << 8)) #define KVM_REG_MIPS_CP0_MAAR(n) (KVM_REG_MIPS_MAAR | \ KVM_REG_SIZE_U64 | (n)) /* * KVM_REG_MIPS_KVM - KVM specific control registers. */ /* * CP0_Count control * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now * Set 1: Master re-enable CP0_Count with unchanged bias, handling timer * interrupts since COUNT_RESUME * This can be used to freeze the timer to get a consistent snapshot of * the CP0_Count and timer interrupt pending state, while also resuming * safely without losing time or guest timer interrupts. * Other: Reserved, do not change. */ #define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0) #define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 /* * CP0_Count resume monotonic nanoseconds * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master * disable). Any reads and writes of Count related registers while * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is * cleared again (master enable) any timer interrupts since this time will be * emulated. * Modifications to times in the future are rejected. */ #define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1) /* * CP0_Count rate in Hz * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without * discontinuities in CP0_Count. */ #define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2) /* * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers. * * bits[15..8] - Register subset (see definitions below). * bits[7..5] - Must be zero. * bits[4..0] - Register number within register subset. */ #define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL) #define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL) #define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL) /* * KVM_REG_MIPS_FPR - Floating point / Vector registers. */ #define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n)) #define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n)) #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n)) /* * KVM_REG_MIPS_FCR - Floating point control registers. */ #define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0) #define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31) /* * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers. */ #define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0) #define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1) /* * KVM MIPS specific structures and definitions * */ struct kvm_debug_exit_arch { __u64 epc; }; /* for KVM_SET_GUEST_DEBUG */ struct kvm_guest_debug_arch { }; /* definition of registers in kvm_run */ struct kvm_sync_regs { }; /* dummy definition */ struct kvm_sregs { }; struct kvm_mips_interrupt { /* in */ __u32 cpu; __u32 irq; }; #endif /* __LINUX_KVM_MIPS_H */ PK ! �;� � sclp_ctl.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * IOCTL interface for SCLP * * Copyright IBM Corp. 2012 * * Author: Michael Holzheu <holzheu@linux.vnet.ibm.com> */ #ifndef _ASM_SCLP_CTL_H #define _ASM_SCLP_CTL_H #include <linux/types.h> struct sclp_ctl_sccb { __u32 cmdw; __u64 sccb; } __attribute__((packed)); #define SCLP_CTL_IOCTL_MAGIC 0x10 #define SCLP_CTL_SCCB \ _IOWR(SCLP_CTL_IOCTL_MAGIC, 0x10, struct sclp_ctl_sccb) #endif PK ! ;�{� � guarded_storage.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _GUARDED_STORAGE_H #define _GUARDED_STORAGE_H #include <linux/types.h> struct gs_cb { __u64 reserved; __u64 gsd; __u64 gssm; __u64 gs_epl_a; }; struct gs_epl { __u8 pad1; union { __u8 gs_eam; struct { __u8 : 6; __u8 e : 1; __u8 b : 1; }; }; union { __u8 gs_eci; struct { __u8 tx : 1; __u8 cx : 1; __u8 : 5; __u8 in : 1; }; }; union { __u8 gs_eai; struct { __u8 : 1; __u8 t : 1; __u8 as : 2; __u8 ar : 4; }; }; __u32 pad2; __u64 gs_eha; __u64 gs_eia; __u64 gs_eoa; __u64 gs_eir; __u64 gs_era; }; #define GS_ENABLE 0 #define GS_DISABLE 1 #define GS_SET_BC_CB 2 #define GS_CLEAR_BC_CB 3 #define GS_BROADCAST 4 static inline void load_gs_cb(struct gs_cb *gs_cb) { asm volatile(".insn rxy,0xe3000000004d,0,%0" : : "Q" (*gs_cb)); } static inline void store_gs_cb(struct gs_cb *gs_cb) { asm volatile(".insn rxy,0xe30000000049,0,%0" : : "Q" (*gs_cb)); } static inline void save_gs_cb(struct gs_cb *gs_cb) { if (gs_cb) store_gs_cb(gs_cb); } static inline void restore_gs_cb(struct gs_cb *gs_cb) { if (gs_cb) load_gs_cb(gs_cb); } #endif /* _GUARDED_STORAGE_H */ PK ! J;�v� � hwctrset.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright IBM Corp. 2021 * Interface implementation for communication with the CPU Measurement * counter facility device driver. * * Author(s): Thomas Richter <tmricht@linux.ibm.com> * * Define for ioctl() commands to communicate with the CPU Measurement * counter facility device driver. */ #ifndef _PERF_CPUM_CF_DIAG_H #define _PERF_CPUM_CF_DIAG_H #include <linux/ioctl.h> #include <linux/types.h> #define S390_HWCTR_DEVICE "hwctr" #define S390_HWCTR_START_VERSION 1 struct s390_ctrset_start { /* Set CPUs to operate on */ __u64 version; /* Version of interface */ __u64 data_bytes; /* # of bytes required */ __u64 cpumask_len; /* Length of CPU mask in bytes */ __u64 *cpumask; /* Pointer to CPU mask */ __u64 counter_sets; /* Bit mask of counter sets to get */ }; struct s390_ctrset_setdata { /* Counter set data */ __u32 set; /* Counter set number */ __u32 no_cnts; /* # of counters stored in cv[] */ __u64 cv[0]; /* Counter values (variable length) */ }; struct s390_ctrset_cpudata { /* Counter set data per CPU */ __u32 cpu_nr; /* CPU number */ __u32 no_sets; /* # of counters sets in data[] */ struct s390_ctrset_setdata data[0]; }; struct s390_ctrset_read { /* Structure to get all ctr sets */ __u64 no_cpus; /* Total # of CPUs data taken from */ struct s390_ctrset_cpudata data[0]; }; #define S390_HWCTR_MAGIC 'C' /* Random magic # for ioctls */ #define S390_HWCTR_START _IOWR(S390_HWCTR_MAGIC, 1, struct s390_ctrset_start) #define S390_HWCTR_STOP _IO(S390_HWCTR_MAGIC, 2) #define S390_HWCTR_READ _IOWR(S390_HWCTR_MAGIC, 3, struct s390_ctrset_read) #endif PK ! ��� cmb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPIS390_CMB_H #define _UAPIS390_CMB_H #include <linux/types.h> /** * struct cmbdata - channel measurement block data for user space * @size: size of the stored data * @elapsed_time: time since last sampling * @ssch_rsch_count: number of ssch and rsch * @sample_count: number of samples * @device_connect_time: time of device connect * @function_pending_time: time of function pending * @device_disconnect_time: time of device disconnect * @control_unit_queuing_time: time of control unit queuing * @device_active_only_time: time of device active only * @device_busy_time: time of device busy (ext. format) * @initial_command_response_time: initial command response time (ext. format) * * All values are stored as 64 bit for simplicity, especially * in 32 bit emulation mode. All time values are normalized to * nanoseconds. * Currently, two formats are known, which differ by the size of * this structure, i.e. the last two members are only set when * the extended channel measurement facility (first shipped in * z990 machines) is activated. * Potentially, more fields could be added, which would result in a * new ioctl number. */ struct cmbdata { __u64 size; __u64 elapsed_time; /* basic and exended format: */ __u64 ssch_rsch_count; __u64 sample_count; __u64 device_connect_time; __u64 function_pending_time; __u64 device_disconnect_time; __u64 control_unit_queuing_time; __u64 device_active_only_time; /* extended format only: */ __u64 device_busy_time; __u64 initial_command_response_time; }; /* enable channel measurement */ #define BIODASDCMFENABLE _IO(DASD_IOCTL_LETTER, 32) /* enable channel measurement */ #define BIODASDCMFDISABLE _IO(DASD_IOCTL_LETTER, 33) /* read channel measurement data */ #define BIODASDREADALLCMB _IOWR(DASD_IOCTL_LETTER, 33, struct cmbdata) #endif /* _UAPIS390_CMB_H */ PK ! /!�� bpf_perf_event.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ #define _UAPI__ASM_BPF_PERF_EVENT_H__ #include <asm/ptrace.h> typedef struct user_regs_struct bpf_user_pt_regs_t; #endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */ PK ! ��Xf f hypfs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Structures for hypfs interface * * Copyright IBM Corp. 2013 * * Author: Martin Schwidefsky <schwidefsky@de.ibm.com> */ #ifndef _ASM_HYPFS_H #define _ASM_HYPFS_H #include <linux/types.h> /* * IOCTL for binary interface /sys/kernel/debug/diag_304 */ struct hypfs_diag304 { __u32 args[2]; __u64 data; __u64 rc; } __attribute__((packed)); #define HYPFS_IOCTL_MAGIC 0x10 #define HYPFS_DIAG304 \ _IOWR(HYPFS_IOCTL_MAGIC, 0x20, struct hypfs_diag304) /* * Structures for binary interface /sys/kernel/debug/diag_0c */ struct hypfs_diag0c_hdr { __u64 len; /* Length of diag0c buffer without header */ __u16 version; /* Version of header */ char reserved1[6]; /* Reserved */ char tod_ext[16]; /* TOD clock for diag0c */ __u64 count; /* Number of entries (CPUs) in diag0c array */ char reserved2[24]; /* Reserved */ }; struct hypfs_diag0c_entry { char date[8]; /* MM/DD/YY in EBCDIC */ char time[8]; /* HH:MM:SS in EBCDIC */ __u64 virtcpu; /* Virtual time consumed by the virt CPU (us) */ __u64 totalproc; /* Total of virtual and simulation time (us) */ __u32 cpu; /* Linux logical CPU number */ __u32 reserved; /* Align to 8 byte */ }; struct hypfs_diag0c_data { struct hypfs_diag0c_hdr hdr; /* 64 byte header */ struct hypfs_diag0c_entry entry[]; /* diag0c entry array */ }; #endif PK ! �#Ɨ/ / qeth.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * ioctl definitions for qeth driver * * Copyright IBM Corp. 2004 * * Author(s): Thomas Spatzier <tspat@de.ibm.com> * */ #ifndef __ASM_S390_QETH_IOCTL_H__ #define __ASM_S390_QETH_IOCTL_H__ #include <linux/types.h> #include <linux/ioctl.h> #define SIOC_QETH_ARP_SET_NO_ENTRIES (SIOCDEVPRIVATE) #define SIOC_QETH_ARP_QUERY_INFO (SIOCDEVPRIVATE + 1) #define SIOC_QETH_ARP_ADD_ENTRY (SIOCDEVPRIVATE + 2) #define SIOC_QETH_ARP_REMOVE_ENTRY (SIOCDEVPRIVATE + 3) #define SIOC_QETH_ARP_FLUSH_CACHE (SIOCDEVPRIVATE + 4) #define SIOC_QETH_ADP_SET_SNMP_CONTROL (SIOCDEVPRIVATE + 5) #define SIOC_QETH_GET_CARD_TYPE (SIOCDEVPRIVATE + 6) #define SIOC_QETH_QUERY_OAT (SIOCDEVPRIVATE + 7) struct qeth_arp_cache_entry { __u8 macaddr[6]; __u8 reserved1[2]; __u8 ipaddr[16]; /* for both IPv4 and IPv6 */ __u8 reserved2[32]; } __attribute__ ((packed)); enum qeth_arp_ipaddrtype { QETHARP_IP_ADDR_V4 = 1, QETHARP_IP_ADDR_V6 = 2, }; struct qeth_arp_entrytype { __u8 mac; __u8 ip; } __attribute__((packed)); #define QETH_QARP_MEDIASPECIFIC_BYTES 32 #define QETH_QARP_MACADDRTYPE_BYTES 1 struct qeth_arp_qi_entry7 { __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES]; struct qeth_arp_entrytype type; __u8 macaddr[6]; __u8 ipaddr[4]; } __attribute__((packed)); struct qeth_arp_qi_entry7_ipv6 { __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES]; struct qeth_arp_entrytype type; __u8 macaddr[6]; __u8 ipaddr[16]; } __attribute__((packed)); struct qeth_arp_qi_entry7_short { struct qeth_arp_entrytype type; __u8 macaddr[6]; __u8 ipaddr[4]; } __attribute__((packed)); struct qeth_arp_qi_entry7_short_ipv6 { struct qeth_arp_entrytype type; __u8 macaddr[6]; __u8 ipaddr[16]; } __attribute__((packed)); struct qeth_arp_qi_entry5 { __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES]; struct qeth_arp_entrytype type; __u8 ipaddr[4]; } __attribute__((packed)); struct qeth_arp_qi_entry5_ipv6 { __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES]; struct qeth_arp_entrytype type; __u8 ipaddr[16]; } __attribute__((packed)); struct qeth_arp_qi_entry5_short { struct qeth_arp_entrytype type; __u8 ipaddr[4]; } __attribute__((packed)); struct qeth_arp_qi_entry5_short_ipv6 { struct qeth_arp_entrytype type; __u8 ipaddr[16]; } __attribute__((packed)); /* * can be set by user if no "media specific information" is wanted * -> saves a lot of space in user space buffer */ #define QETH_QARP_STRIP_ENTRIES 0x8000 #define QETH_QARP_WITH_IPV6 0x4000 #define QETH_QARP_REQUEST_MASK 0x00ff /* data sent to user space as result of query arp ioctl */ #define QETH_QARP_USER_DATA_SIZE 20000 #define QETH_QARP_MASK_OFFSET 4 #define QETH_QARP_ENTRIES_OFFSET 6 struct qeth_arp_query_user_data { union { __u32 data_len; /* set by user space program */ __u32 no_entries; /* set by kernel */ } u; __u16 mask_bits; char *entries; } __attribute__((packed)); struct qeth_query_oat_data { __u32 command; __u32 buffer_len; __u32 response_len; __u64 ptr; }; #endif /* __ASM_S390_QETH_IOCTL_H__ */ PK ! S�#� � vmcp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright IBM Corp. 2004, 2005 * Interface implementation for communication with the z/VM control program * Version 1.0 * Author(s): Christian Borntraeger <cborntra@de.ibm.com> * * * z/VMs CP offers the possibility to issue commands via the diagnose code 8 * this driver implements a character device that issues these commands and * returns the answer of CP. * * The idea of this driver is based on cpint from Neale Ferguson */ #ifndef _UAPI_ASM_VMCP_H #define _UAPI_ASM_VMCP_H #include <linux/ioctl.h> #define VMCP_GETCODE _IOR(0x10, 1, int) #define VMCP_SETBUF _IOW(0x10, 2, int) #define VMCP_GETSIZE _IOR(0x10, 3, int) #endif /* _UAPI_ASM_VMCP_H */ PK ! ٘u7 tape390.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /************************************************************************* * * enables user programs to display messages and control encryption * on s390 tape devices * * Copyright IBM Corp. 2001, 2006 * Author(s): Michael Holzheu <holzheu@de.ibm.com> * *************************************************************************/ #ifndef _TAPE390_H #define _TAPE390_H #define TAPE390_DISPLAY _IOW('d', 1, struct display_struct) /* * The TAPE390_DISPLAY ioctl calls the Load Display command * which transfers 17 bytes of data from the channel to the subsystem: * - 1 format control byte, and * - two 8-byte messages * * Format control byte: * 0-2: New Message Overlay * 3: Alternate Messages * 4: Blink Message * 5: Display Low/High Message * 6: Reserved * 7: Automatic Load Request * */ typedef struct display_struct { char cntrl; char message1[8]; char message2[8]; } display_struct; /* * Tape encryption support */ struct tape390_crypt_info { char capability; char status; char medium_status; } __attribute__ ((packed)); /* Macros for "capable" field */ #define TAPE390_CRYPT_SUPPORTED_MASK 0x01 #define TAPE390_CRYPT_SUPPORTED(x) \ ((x.capability & TAPE390_CRYPT_SUPPORTED_MASK)) /* Macros for "status" field */ #define TAPE390_CRYPT_ON_MASK 0x01 #define TAPE390_CRYPT_ON(x) (((x.status) & TAPE390_CRYPT_ON_MASK)) /* Macros for "medium status" field */ #define TAPE390_MEDIUM_LOADED_MASK 0x01 #define TAPE390_MEDIUM_ENCRYPTED_MASK 0x02 #define TAPE390_MEDIUM_ENCRYPTED(x) \ (((x.medium_status) & TAPE390_MEDIUM_ENCRYPTED_MASK)) #define TAPE390_MEDIUM_LOADED(x) \ (((x.medium_status) & TAPE390_MEDIUM_LOADED_MASK)) /* * The TAPE390_CRYPT_SET ioctl is used to switch on/off encryption. * The "encryption_capable" and "tape_status" fields are ignored for this ioctl! */ #define TAPE390_CRYPT_SET _IOW('d', 2, struct tape390_crypt_info) /* * The TAPE390_CRYPT_QUERY ioctl is used to query the encryption state. */ #define TAPE390_CRYPT_QUERY _IOR('d', 3, struct tape390_crypt_info) /* Values for "kekl1/2_type" and "kekl1/2_type_on_tape" fields */ #define TAPE390_KEKL_TYPE_NONE 0 #define TAPE390_KEKL_TYPE_LABEL 1 #define TAPE390_KEKL_TYPE_HASH 2 struct tape390_kekl { unsigned char type; unsigned char type_on_tape; char label[65]; } __attribute__ ((packed)); struct tape390_kekl_pair { struct tape390_kekl kekl[2]; } __attribute__ ((packed)); /* * The TAPE390_KEKL_SET ioctl is used to set Key Encrypting Key labels. */ #define TAPE390_KEKL_SET _IOW('d', 4, struct tape390_kekl_pair) /* * The TAPE390_KEKL_QUERY ioctl is used to query Key Encrypting Key labels. */ #define TAPE390_KEKL_QUERY _IOR('d', 5, struct tape390_kekl_pair) #endif PK ! ��]YQ Q pkey.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Userspace interface to the pkey device driver * * Copyright IBM Corp. 2017, 2019 * * Author: Harald Freudenberger <freude@de.ibm.com> * */ #ifndef _UAPI_PKEY_H #define _UAPI_PKEY_H #include <linux/ioctl.h> #include <linux/types.h> /* * Ioctl calls supported by the pkey device driver */ #define PKEY_IOCTL_MAGIC 'p' #define SECKEYBLOBSIZE 64 /* secure key blob size is always 64 bytes */ #define PROTKEYBLOBSIZE 80 /* protected key blob size is always 80 bytes */ #define MAXPROTKEYSIZE 64 /* a protected key blob may be up to 64 bytes */ #define MAXCLRKEYSIZE 32 /* a clear key value may be up to 32 bytes */ #define MAXAESCIPHERKEYSIZE 136 /* our aes cipher keys have always 136 bytes */ #define MINEP11AESKEYBLOBSIZE 256 /* min EP11 AES key blob size */ #define MAXEP11AESKEYBLOBSIZE 320 /* max EP11 AES key blob size */ /* Minimum size of a key blob */ #define MINKEYBLOBSIZE SECKEYBLOBSIZE /* defines for the type field within the pkey_protkey struct */ #define PKEY_KEYTYPE_AES_128 1 #define PKEY_KEYTYPE_AES_192 2 #define PKEY_KEYTYPE_AES_256 3 #define PKEY_KEYTYPE_ECC 4 /* the newer ioctls use a pkey_key_type enum for type information */ enum pkey_key_type { PKEY_TYPE_CCA_DATA = (__u32) 1, PKEY_TYPE_CCA_CIPHER = (__u32) 2, PKEY_TYPE_EP11 = (__u32) 3, PKEY_TYPE_CCA_ECC = (__u32) 0x1f, PKEY_TYPE_EP11_AES = (__u32) 6, PKEY_TYPE_EP11_ECC = (__u32) 7, }; /* the newer ioctls use a pkey_key_size enum for key size information */ enum pkey_key_size { PKEY_SIZE_AES_128 = (__u32) 128, PKEY_SIZE_AES_192 = (__u32) 192, PKEY_SIZE_AES_256 = (__u32) 256, PKEY_SIZE_UNKNOWN = (__u32) 0xFFFFFFFF, }; /* some of the newer ioctls use these flags */ #define PKEY_FLAGS_MATCH_CUR_MKVP 0x00000002 #define PKEY_FLAGS_MATCH_ALT_MKVP 0x00000004 /* keygenflags defines for CCA AES cipher keys */ #define PKEY_KEYGEN_XPRT_SYM 0x00008000 #define PKEY_KEYGEN_XPRT_UASY 0x00004000 #define PKEY_KEYGEN_XPRT_AASY 0x00002000 #define PKEY_KEYGEN_XPRT_RAW 0x00001000 #define PKEY_KEYGEN_XPRT_CPAC 0x00000800 #define PKEY_KEYGEN_XPRT_DES 0x00000080 #define PKEY_KEYGEN_XPRT_AES 0x00000040 #define PKEY_KEYGEN_XPRT_RSA 0x00000008 /* Struct to hold apqn target info (card/domain pair) */ struct pkey_apqn { __u16 card; __u16 domain; }; /* Struct to hold a CCA AES secure key blob */ struct pkey_seckey { __u8 seckey[SECKEYBLOBSIZE]; /* the secure key blob */ }; /* Struct to hold protected key and length info */ struct pkey_protkey { __u32 type; /* key type, one of the PKEY_KEYTYPE_AES values */ __u32 len; /* bytes actually stored in protkey[] */ __u8 protkey[MAXPROTKEYSIZE]; /* the protected key blob */ }; /* Struct to hold an AES clear key value */ struct pkey_clrkey { __u8 clrkey[MAXCLRKEYSIZE]; /* 16, 24, or 32 byte clear key value */ }; /* * EP11 key blobs of type PKEY_TYPE_EP11_AES and PKEY_TYPE_EP11_ECC * are ep11 blobs prepended by this header: */ struct ep11kblob_header { __u8 type; /* always 0x00 */ __u8 hver; /* header version, currently needs to be 0x00 */ __u16 len; /* total length in bytes (including this header) */ __u8 version; /* PKEY_TYPE_EP11_AES or PKEY_TYPE_EP11_ECC */ __u8 res0; /* unused */ __u16 bitlen; /* clear key bit len, 0 for unknown */ __u8 res1[8]; /* unused */ } __packed; /* * Generate CCA AES secure key. */ struct pkey_genseck { __u16 cardnr; /* in: card to use or FFFF for any */ __u16 domain; /* in: domain or FFFF for any */ __u32 keytype; /* in: key type to generate */ struct pkey_seckey seckey; /* out: the secure key blob */ }; #define PKEY_GENSECK _IOWR(PKEY_IOCTL_MAGIC, 0x01, struct pkey_genseck) /* * Construct CCA AES secure key from clear key value */ struct pkey_clr2seck { __u16 cardnr; /* in: card to use or FFFF for any */ __u16 domain; /* in: domain or FFFF for any */ __u32 keytype; /* in: key type to generate */ struct pkey_clrkey clrkey; /* in: the clear key value */ struct pkey_seckey seckey; /* out: the secure key blob */ }; #define PKEY_CLR2SECK _IOWR(PKEY_IOCTL_MAGIC, 0x02, struct pkey_clr2seck) /* * Fabricate AES protected key from a CCA AES secure key */ struct pkey_sec2protk { __u16 cardnr; /* in: card to use or FFFF for any */ __u16 domain; /* in: domain or FFFF for any */ struct pkey_seckey seckey; /* in: the secure key blob */ struct pkey_protkey protkey; /* out: the protected key */ }; #define PKEY_SEC2PROTK _IOWR(PKEY_IOCTL_MAGIC, 0x03, struct pkey_sec2protk) /* * Fabricate AES protected key from clear key value */ struct pkey_clr2protk { __u32 keytype; /* in: key type to generate */ struct pkey_clrkey clrkey; /* in: the clear key value */ struct pkey_protkey protkey; /* out: the protected key */ }; #define PKEY_CLR2PROTK _IOWR(PKEY_IOCTL_MAGIC, 0x04, struct pkey_clr2protk) /* * Search for matching crypto card based on the Master Key * Verification Pattern provided inside a CCA AES secure key. */ struct pkey_findcard { struct pkey_seckey seckey; /* in: the secure key blob */ __u16 cardnr; /* out: card number */ __u16 domain; /* out: domain number */ }; #define PKEY_FINDCARD _IOWR(PKEY_IOCTL_MAGIC, 0x05, struct pkey_findcard) /* * Combined together: findcard + sec2prot */ struct pkey_skey2pkey { struct pkey_seckey seckey; /* in: the secure key blob */ struct pkey_protkey protkey; /* out: the protected key */ }; #define PKEY_SKEY2PKEY _IOWR(PKEY_IOCTL_MAGIC, 0x06, struct pkey_skey2pkey) /* * Verify the given CCA AES secure key for being able to be useable with * the pkey module. Check for correct key type and check for having at * least one crypto card being able to handle this key (master key * or old master key verification pattern matches). * Return some info about the key: keysize in bits, keytype (currently * only AES), flag if key is wrapped with an old MKVP. */ struct pkey_verifykey { struct pkey_seckey seckey; /* in: the secure key blob */ __u16 cardnr; /* out: card number */ __u16 domain; /* out: domain number */ __u16 keysize; /* out: key size in bits */ __u32 attributes; /* out: attribute bits */ }; #define PKEY_VERIFYKEY _IOWR(PKEY_IOCTL_MAGIC, 0x07, struct pkey_verifykey) #define PKEY_VERIFY_ATTR_AES 0x00000001 /* key is an AES key */ #define PKEY_VERIFY_ATTR_OLD_MKVP 0x00000100 /* key has old MKVP value */ /* * Generate AES random protected key. */ struct pkey_genprotk { __u32 keytype; /* in: key type to generate */ struct pkey_protkey protkey; /* out: the protected key */ }; #define PKEY_GENPROTK _IOWR(PKEY_IOCTL_MAGIC, 0x08, struct pkey_genprotk) /* * Verify an AES protected key. */ struct pkey_verifyprotk { struct pkey_protkey protkey; /* in: the protected key to verify */ }; #define PKEY_VERIFYPROTK _IOW(PKEY_IOCTL_MAGIC, 0x09, struct pkey_verifyprotk) /* * Transform an key blob (of any type) into a protected key */ struct pkey_kblob2pkey { __u8 __user *key; /* in: the key blob */ __u32 keylen; /* in: the key blob length */ struct pkey_protkey protkey; /* out: the protected key */ }; #define PKEY_KBLOB2PROTK _IOWR(PKEY_IOCTL_MAGIC, 0x0A, struct pkey_kblob2pkey) /* * Generate secure key, version 2. * Generate CCA AES secure key, CCA AES cipher key or EP11 AES secure key. * There needs to be a list of apqns given with at least one entry in there. * All apqns in the list need to be exact apqns, 0xFFFF as ANY card or domain * is not supported. The implementation walks through the list of apqns and * tries to send the request to each apqn without any further checking (like * card type or online state). If the apqn fails, simple the next one in the * list is tried until success (return 0) or the end of the list is reached * (return -1 with errno ENODEV). You may use the PKEY_APQNS4KT ioctl to * generate a list of apqns based on the key type to generate. * The keygenflags argument is passed to the low level generation functions * individual for the key type and has a key type specific meaning. When * generating CCA cipher keys you can use one or more of the PKEY_KEYGEN_* * flags to widen the export possibilities. By default a cipher key is * only exportable for CPACF (PKEY_KEYGEN_XPRT_CPAC). * The keygenflag argument for generating an EP11 AES key should either be 0 * to use the defaults which are XCP_BLOB_ENCRYPT, XCP_BLOB_DECRYPT and * XCP_BLOB_PROTKEY_EXTRACTABLE or a valid combination of XCP_BLOB_* flags. */ struct pkey_genseck2 { struct pkey_apqn __user *apqns; /* in: ptr to list of apqn targets*/ __u32 apqn_entries; /* in: # of apqn target list entries */ enum pkey_key_type type; /* in: key type to generate */ enum pkey_key_size size; /* in: key size to generate */ __u32 keygenflags; /* in: key generation flags */ __u8 __user *key; /* in: pointer to key blob buffer */ __u32 keylen; /* in: available key blob buffer size */ /* out: actual key blob size */ }; #define PKEY_GENSECK2 _IOWR(PKEY_IOCTL_MAGIC, 0x11, struct pkey_genseck2) /* * Generate secure key from clear key value, version 2. * Construct an CCA AES secure key, CCA AES cipher key or EP11 AES secure * key from a given clear key value. * There needs to be a list of apqns given with at least one entry in there. * All apqns in the list need to be exact apqns, 0xFFFF as ANY card or domain * is not supported. The implementation walks through the list of apqns and * tries to send the request to each apqn without any further checking (like * card type or online state). If the apqn fails, simple the next one in the * list is tried until success (return 0) or the end of the list is reached * (return -1 with errno ENODEV). You may use the PKEY_APQNS4KT ioctl to * generate a list of apqns based on the key type to generate. * The keygenflags argument is passed to the low level generation functions * individual for the key type and has a key type specific meaning. When * generating CCA cipher keys you can use one or more of the PKEY_KEYGEN_* * flags to widen the export possibilities. By default a cipher key is * only exportable for CPACF (PKEY_KEYGEN_XPRT_CPAC). * The keygenflag argument for generating an EP11 AES key should either be 0 * to use the defaults which are XCP_BLOB_ENCRYPT, XCP_BLOB_DECRYPT and * XCP_BLOB_PROTKEY_EXTRACTABLE or a valid combination of XCP_BLOB_* flags. */ struct pkey_clr2seck2 { struct pkey_apqn __user *apqns; /* in: ptr to list of apqn targets */ __u32 apqn_entries; /* in: # of apqn target list entries */ enum pkey_key_type type; /* in: key type to generate */ enum pkey_key_size size; /* in: key size to generate */ __u32 keygenflags; /* in: key generation flags */ struct pkey_clrkey clrkey; /* in: the clear key value */ __u8 __user *key; /* in: pointer to key blob buffer */ __u32 keylen; /* in: available key blob buffer size */ /* out: actual key blob size */ }; #define PKEY_CLR2SECK2 _IOWR(PKEY_IOCTL_MAGIC, 0x12, struct pkey_clr2seck2) /* * Verify the given secure key, version 2. * Check for correct key type. If cardnr and domain are given (are not * 0xFFFF) also check if this apqn is able to handle this type of key. * If cardnr and/or domain is 0xFFFF, on return these values are filled * with one apqn able to handle this key. * The function also checks for the master key verification patterns * of the key matching to the current or alternate mkvp of the apqn. * For CCA AES secure keys and CCA AES cipher keys this means to check * the key's mkvp against the current or old mkvp of the apqns. The flags * field is updated with some additional info about the apqn mkvp * match: If the current mkvp matches to the key's mkvp then the * PKEY_FLAGS_MATCH_CUR_MKVP bit is set, if the alternate mkvp matches to * the key's mkvp the PKEY_FLAGS_MATCH_ALT_MKVP is set. For CCA keys the * alternate mkvp is the old master key verification pattern. * CCA AES secure keys are also checked to have the CPACF export allowed * bit enabled (XPRTCPAC) in the kmf1 field. * EP11 keys are also supported and the wkvp of the key is checked against * the current wkvp of the apqns. There is no alternate for this type of * key and so on a match the flag PKEY_FLAGS_MATCH_CUR_MKVP always is set. * EP11 keys are also checked to have XCP_BLOB_PROTKEY_EXTRACTABLE set. * The ioctl returns 0 as long as the given or found apqn matches to * matches with the current or alternate mkvp to the key's mkvp. If the given * apqn does not match or there is no such apqn found, -1 with errno * ENODEV is returned. */ struct pkey_verifykey2 { __u8 __user *key; /* in: pointer to key blob */ __u32 keylen; /* in: key blob size */ __u16 cardnr; /* in/out: card number */ __u16 domain; /* in/out: domain number */ enum pkey_key_type type; /* out: the key type */ enum pkey_key_size size; /* out: the key size */ __u32 flags; /* out: additional key info flags */ }; #define PKEY_VERIFYKEY2 _IOWR(PKEY_IOCTL_MAGIC, 0x17, struct pkey_verifykey2) /* * Transform a key blob into a protected key, version 2. * There needs to be a list of apqns given with at least one entry in there. * All apqns in the list need to be exact apqns, 0xFFFF as ANY card or domain * is not supported. The implementation walks through the list of apqns and * tries to send the request to each apqn without any further checking (like * card type or online state). If the apqn fails, simple the next one in the * list is tried until success (return 0) or the end of the list is reached * (return -1 with errno ENODEV). You may use the PKEY_APQNS4K ioctl to * generate a list of apqns based on the key. * Deriving ECC protected keys from ECC secure keys is not supported with * this ioctl, use PKEY_KBLOB2PROTK3 for this purpose. */ struct pkey_kblob2pkey2 { __u8 __user *key; /* in: pointer to key blob */ __u32 keylen; /* in: key blob size */ struct pkey_apqn __user *apqns; /* in: ptr to list of apqn targets */ __u32 apqn_entries; /* in: # of apqn target list entries */ struct pkey_protkey protkey; /* out: the protected key */ }; #define PKEY_KBLOB2PROTK2 _IOWR(PKEY_IOCTL_MAGIC, 0x1A, struct pkey_kblob2pkey2) /* * Build a list of APQNs based on a key blob given. * Is able to find out which type of secure key is given (CCA AES secure * key, CCA AES cipher key, CCA ECC private key, EP11 AES key, EP11 ECC private * key) and tries to find all matching crypto cards based on the MKVP and maybe * other criterias (like CCA AES cipher keys need a CEX5C or higher, EP11 keys * with BLOB_PKEY_EXTRACTABLE need a CEX7 and EP11 api version 4). The list of * APQNs is further filtered by the key's mkvp which needs to match to either * the current mkvp (CCA and EP11) or the alternate mkvp (old mkvp, CCA adapters * only) of the apqns. The flags argument may be used to limit the matching * apqns. If the PKEY_FLAGS_MATCH_CUR_MKVP is given, only the current mkvp of * each apqn is compared. Likewise with the PKEY_FLAGS_MATCH_ALT_MKVP. If both * are given, it is assumed to return apqns where either the current or the * alternate mkvp matches. At least one of the matching flags needs to be given. * The flags argument for EP11 keys has no further action and is currently * ignored (but needs to be given as PKEY_FLAGS_MATCH_CUR_MKVP) as there is only * the wkvp from the key to match against the apqn's wkvp. * The list of matching apqns is stored into the space given by the apqns * argument and the number of stored entries goes into apqn_entries. If the list * is empty (apqn_entries is 0) the apqn_entries field is updated to the number * of apqn targets found and the ioctl returns with 0. If apqn_entries is > 0 * but the number of apqn targets does not fit into the list, the apqn_targets * field is updatedd with the number of reqired entries but there are no apqn * values stored in the list and the ioctl returns with ENOSPC. If no matching * APQN is found, the ioctl returns with 0 but the apqn_entries value is 0. */ struct pkey_apqns4key { __u8 __user *key; /* in: pointer to key blob */ __u32 keylen; /* in: key blob size */ __u32 flags; /* in: match controlling flags */ struct pkey_apqn __user *apqns; /* in/out: ptr to list of apqn targets*/ __u32 apqn_entries; /* in: max # of apqn entries in the list */ /* out: # apqns stored into the list */ }; #define PKEY_APQNS4K _IOWR(PKEY_IOCTL_MAGIC, 0x1B, struct pkey_apqns4key) /* * Build a list of APQNs based on a key type given. * Build a list of APQNs based on a given key type and maybe further * restrict the list by given master key verification patterns. * For different key types there may be different ways to match the * master key verification patterns. For CCA keys (CCA data key and CCA * cipher key) the first 8 bytes of cur_mkvp refer to the current AES mkvp value * of the apqn and the first 8 bytes of the alt_mkvp refer to the old AES mkvp. * For CCA ECC keys it is similar but the match is against the APKA current/old * mkvp. The flags argument controls if the apqns current and/or alternate mkvp * should match. If the PKEY_FLAGS_MATCH_CUR_MKVP is given, only the current * mkvp of each apqn is compared. Likewise with the PKEY_FLAGS_MATCH_ALT_MKVP. * If both are given, it is assumed to return apqns where either the * current or the alternate mkvp matches. If no match flag is given * (flags is 0) the mkvp values are ignored for the match process. * For EP11 keys there is only the current wkvp. So if the apqns should also * match to a given wkvp, then the PKEY_FLAGS_MATCH_CUR_MKVP flag should be * set. The wkvp value is 32 bytes but only the leftmost 16 bytes are compared * against the leftmost 16 byte of the wkvp of the apqn. * The list of matching apqns is stored into the space given by the apqns * argument and the number of stored entries goes into apqn_entries. If the list * is empty (apqn_entries is 0) the apqn_entries field is updated to the number * of apqn targets found and the ioctl returns with 0. If apqn_entries is > 0 * but the number of apqn targets does not fit into the list, the apqn_targets * field is updatedd with the number of reqired entries but there are no apqn * values stored in the list and the ioctl returns with ENOSPC. If no matching * APQN is found, the ioctl returns with 0 but the apqn_entries value is 0. */ struct pkey_apqns4keytype { enum pkey_key_type type; /* in: key type */ __u8 cur_mkvp[32]; /* in: current mkvp */ __u8 alt_mkvp[32]; /* in: alternate mkvp */ __u32 flags; /* in: match controlling flags */ struct pkey_apqn __user *apqns; /* in/out: ptr to list of apqn targets*/ __u32 apqn_entries; /* in: max # of apqn entries in the list */ /* out: # apqns stored into the list */ }; #define PKEY_APQNS4KT _IOWR(PKEY_IOCTL_MAGIC, 0x1C, struct pkey_apqns4keytype) /* * Transform a key blob into a protected key, version 3. * The difference to version 2 of this ioctl is that the protected key * buffer is now explicitly and not within a struct pkey_protkey any more. * So this ioctl is also able to handle EP11 and CCA ECC secure keys and * provide ECC protected keys. * There needs to be a list of apqns given with at least one entry in there. * All apqns in the list need to be exact apqns, 0xFFFF as ANY card or domain * is not supported. The implementation walks through the list of apqns and * tries to send the request to each apqn without any further checking (like * card type or online state). If the apqn fails, simple the next one in the * list is tried until success (return 0) or the end of the list is reached * (return -1 with errno ENODEV). You may use the PKEY_APQNS4K ioctl to * generate a list of apqns based on the key. */ struct pkey_kblob2pkey3 { __u8 __user *key; /* in: pointer to key blob */ __u32 keylen; /* in: key blob size */ struct pkey_apqn __user *apqns; /* in: ptr to list of apqn targets */ __u32 apqn_entries; /* in: # of apqn target list entries */ __u32 pkeytype; /* out: prot key type (enum pkey_key_type) */ __u32 pkeylen; /* in/out: size of pkey buffer/actual len of pkey */ __u8 __user *pkey; /* in: pkey blob buffer space ptr */ }; #define PKEY_KBLOB2PROTK3 _IOWR(PKEY_IOCTL_MAGIC, 0x1D, struct pkey_kblob2pkey3) #endif /* _UAPI_PKEY_H */ PK ! ���G� � sthyi.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _UAPI_ASM_STHYI_H #define _UAPI_ASM_STHYI_H #define STHYI_FC_CP_IFL_CAP 0 #endif /* _UAPI_ASM_STHYI_H */ PK ! |���% % clp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * ioctl interface for /dev/clp * * Copyright IBM Corp. 2016 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> */ #ifndef _ASM_CLP_H #define _ASM_CLP_H #include <linux/types.h> #include <linux/ioctl.h> struct clp_req { unsigned int c : 1; unsigned int r : 1; unsigned int lps : 6; unsigned int cmd : 8; unsigned int : 16; unsigned int reserved; __u64 data_p; }; #define CLP_IOCTL_MAGIC 'c' #define CLP_SYNC _IOWR(CLP_IOCTL_MAGIC, 0xC1, struct clp_req) #endif PK ! p��˼ � virtio-ccw.hnu �[��� /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ /* * Definitions for virtio-ccw devices. * * Copyright IBM Corp. 2013 * * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> */ #ifndef __KVM_VIRTIO_CCW_H #define __KVM_VIRTIO_CCW_H /* Alignment of vring buffers. */ #define KVM_VIRTIO_CCW_RING_ALIGN 4096 /* Subcode for diagnose 500 (virtio hypercall). */ #define KVM_S390_VIRTIO_CCW_NOTIFY 3 #endif PK ! ^��� � ipl.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_S390_UAPI_IPL_H #define _ASM_S390_UAPI_IPL_H #include <linux/types.h> /* IPL Parameter List header */ struct ipl_pl_hdr { __u32 len; __u8 flags; __u8 reserved1[2]; __u8 version; } __packed; #define IPL_PL_FLAG_IPLPS 0x80 #define IPL_PL_FLAG_SIPL 0x40 #define IPL_PL_FLAG_IPLSR 0x20 /* IPL Parameter Block header */ struct ipl_pb_hdr { __u32 len; __u8 pbt; } __packed; /* IPL Parameter Block types */ enum ipl_pbt { IPL_PBT_FCP = 0, IPL_PBT_SCP_DATA = 1, IPL_PBT_CCW = 2, IPL_PBT_NVME = 4, }; /* IPL Parameter Block 0 with common fields */ struct ipl_pb0_common { __u32 len; __u8 pbt; __u8 flags; __u8 reserved1[2]; __u8 loadparm[8]; __u8 reserved2[84]; } __packed; #define IPL_PB0_FLAG_LOADPARM 0x80 /* IPL Parameter Block 0 for FCP */ struct ipl_pb0_fcp { __u32 len; __u8 pbt; __u8 reserved1[3]; __u8 loadparm[8]; __u8 reserved2[304]; __u8 opt; __u8 reserved3[3]; __u8 cssid; __u8 reserved4[1]; __u16 devno; __u8 reserved5[4]; __u64 wwpn; __u64 lun; __u32 bootprog; __u8 reserved6[12]; __u64 br_lba; __u32 scp_data_len; __u8 reserved7[260]; __u8 scp_data[]; } __packed; #define IPL_PB0_FCP_OPT_IPL 0x10 #define IPL_PB0_FCP_OPT_DUMP 0x20 /* IPL Parameter Block 0 for NVMe */ struct ipl_pb0_nvme { __u32 len; __u8 pbt; __u8 reserved1[3]; __u8 loadparm[8]; __u8 reserved2[304]; __u8 opt; __u8 reserved3[3]; __u32 fid; __u8 reserved4[12]; __u32 nsid; __u8 reserved5[4]; __u32 bootprog; __u8 reserved6[12]; __u64 br_lba; __u32 scp_data_len; __u8 reserved7[260]; __u8 scp_data[]; } __packed; #define IPL_PB0_NVME_OPT_IPL 0x10 #define IPL_PB0_NVME_OPT_DUMP 0x20 /* IPL Parameter Block 0 for CCW */ struct ipl_pb0_ccw { __u32 len; __u8 pbt; __u8 flags; __u8 reserved1[2]; __u8 loadparm[8]; __u8 reserved2[84]; __u16 reserved3 : 13; __u8 ssid : 3; __u16 devno; __u8 vm_flags; __u8 reserved4[3]; __u32 vm_parm_len; __u8 nss_name[8]; __u8 vm_parm[64]; __u8 reserved5[8]; } __packed; #define IPL_PB0_CCW_VM_FLAG_NSS 0x80 #define IPL_PB0_CCW_VM_FLAG_VP 0x40 /* IPL Parameter Block 1 for additional SCP data */ struct ipl_pb1_scp_data { __u32 len; __u8 pbt; __u8 scp_data[]; } __packed; /* IPL Report List header */ struct ipl_rl_hdr { __u32 len; __u8 flags; __u8 reserved1[2]; __u8 version; __u8 reserved2[8]; } __packed; /* IPL Report Block header */ struct ipl_rb_hdr { __u32 len; __u8 rbt; __u8 reserved1[11]; } __packed; /* IPL Report Block types */ enum ipl_rbt { IPL_RBT_CERTIFICATES = 1, IPL_RBT_COMPONENTS = 2, }; /* IPL Report Block for the certificate list */ struct ipl_rb_certificate_entry { __u64 addr; __u64 len; } __packed; struct ipl_rb_certificates { __u32 len; __u8 rbt; __u8 reserved1[11]; struct ipl_rb_certificate_entry entries[]; } __packed; /* IPL Report Block for the component list */ struct ipl_rb_component_entry { __u64 addr; __u64 len; __u8 flags; __u8 reserved1[5]; __u16 certificate_index; __u8 reserved2[8]; }; #define IPL_RB_COMPONENT_FLAG_SIGNED 0x80 #define IPL_RB_COMPONENT_FLAG_VERIFIED 0x40 struct ipl_rb_components { __u32 len; __u8 rbt; __u8 reserved1[11]; struct ipl_rb_component_entry entries[]; } __packed; #endif PK ! ~�� � monwriter.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright IBM Corp. 2006 * Character device driver for writing z/VM APPLDATA monitor records * Version 1.0 * Author(s): Melissa Howland <melissah@us.ibm.com> * */ #ifndef _ASM_390_MONWRITER_H #define _ASM_390_MONWRITER_H /* mon_function values */ #define MONWRITE_START_INTERVAL 0x00 /* start interval recording */ #define MONWRITE_STOP_INTERVAL 0x01 /* stop interval or config recording */ #define MONWRITE_GEN_EVENT 0x02 /* generate event record */ #define MONWRITE_START_CONFIG 0x03 /* start configuration recording */ /* the header the app uses in its write() data */ struct monwrite_hdr { unsigned char mon_function; unsigned short applid; unsigned char record_num; unsigned short version; unsigned short release; unsigned short mod_level; unsigned short datalen; unsigned char hdrlen; } __attribute__((packed)); #endif /* _ASM_390_MONWRITER_H */ PK ! �9�� � kvm_perf.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Definitions for perf-kvm on s390 * * Copyright 2014 IBM Corp. * Author(s): Alexander Yarygin <yarygin@linux.vnet.ibm.com> */ #ifndef __LINUX_KVM_PERF_S390_H #define __LINUX_KVM_PERF_S390_H #include <asm/sie.h> #define DECODE_STR_LEN 40 #define VCPU_ID "id" #define KVM_ENTRY_TRACE "kvm:kvm_s390_sie_enter" #define KVM_EXIT_TRACE "kvm:kvm_s390_sie_exit" #define KVM_EXIT_REASON "icptcode" #endif PK ! ���dW W chsc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * ioctl interface for /dev/chsc * * Copyright IBM Corp. 2008, 2012 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> */ #ifndef _ASM_CHSC_H #define _ASM_CHSC_H #include <linux/types.h> #include <linux/ioctl.h> #include <asm/chpid.h> #include <asm/schid.h> #define CHSC_SIZE 0x1000 struct chsc_async_header { __u16 length; __u16 code; __u32 cmd_dependend; __u32 key : 4; __u32 : 28; struct subchannel_id sid; }; struct chsc_async_area { struct chsc_async_header header; __u8 data[CHSC_SIZE - sizeof(struct chsc_async_header)]; }; struct chsc_header { __u16 length; __u16 code; }; struct chsc_sync_area { struct chsc_header header; __u8 data[CHSC_SIZE - sizeof(struct chsc_header)]; }; struct chsc_response_struct { __u16 length; __u16 code; __u32 parms; __u8 data[CHSC_SIZE - 2 * sizeof(__u16) - sizeof(__u32)]; }; struct chsc_chp_cd { struct chp_id chpid; int m; int fmt; struct chsc_response_struct cpcb; }; struct chsc_cu_cd { __u16 cun; __u8 cssid; int m; int fmt; struct chsc_response_struct cucb; }; struct chsc_sch_cud { struct subchannel_id schid; int fmt; struct chsc_response_struct scub; }; struct conf_id { int m; __u8 cssid; __u8 ssid; }; struct chsc_conf_info { struct conf_id id; int fmt; struct chsc_response_struct scid; }; struct ccl_parm_chpid { int m; struct chp_id chp; }; struct ccl_parm_cssids { __u8 f_cssid; __u8 l_cssid; }; struct chsc_comp_list { struct { enum { CCL_CU_ON_CHP = 1, CCL_CHP_TYPE_CAP = 2, CCL_CSS_IMG = 4, CCL_CSS_IMG_CONF_CHAR = 5, CCL_IOP_CHP = 6, } ctype; int fmt; struct ccl_parm_chpid chpid; struct ccl_parm_cssids cssids; } req; struct chsc_response_struct sccl; }; struct chsc_dcal { struct { enum { DCAL_CSS_IID_PN = 4, } atype; __u32 list_parm[2]; int fmt; } req; struct chsc_response_struct sdcal; }; struct chsc_cpd_info { struct chp_id chpid; int m; int fmt; int rfmt; int c; struct chsc_response_struct chpdb; }; #define CHSC_IOCTL_MAGIC 'c' #define CHSC_START _IOWR(CHSC_IOCTL_MAGIC, 0x81, struct chsc_async_area) #define CHSC_INFO_CHANNEL_PATH _IOWR(CHSC_IOCTL_MAGIC, 0x82, \ struct chsc_chp_cd) #define CHSC_INFO_CU _IOWR(CHSC_IOCTL_MAGIC, 0x83, struct chsc_cu_cd) #define CHSC_INFO_SCH_CU _IOWR(CHSC_IOCTL_MAGIC, 0x84, struct chsc_sch_cud) #define CHSC_INFO_CI _IOWR(CHSC_IOCTL_MAGIC, 0x85, struct chsc_conf_info) #define CHSC_INFO_CCL _IOWR(CHSC_IOCTL_MAGIC, 0x86, struct chsc_comp_list) #define CHSC_INFO_CPD _IOWR(CHSC_IOCTL_MAGIC, 0x87, struct chsc_cpd_info) #define CHSC_INFO_DCAL _IOWR(CHSC_IOCTL_MAGIC, 0x88, struct chsc_dcal) #define CHSC_START_SYNC _IOWR(CHSC_IOCTL_MAGIC, 0x89, struct chsc_sync_area) #define CHSC_ON_CLOSE_SET _IOWR(CHSC_IOCTL_MAGIC, 0x8a, struct chsc_async_area) #define CHSC_ON_CLOSE_REMOVE _IO(CHSC_IOCTL_MAGIC, 0x8b) #endif PK ! ��٢, �, zcrypt.hnu �[��� /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ /* * include/asm-s390/zcrypt.h * * zcrypt 2.2.1 (user-visible header) * * Copyright IBM Corp. 2001, 2019 * Author(s): Robert Burroughs * Eric Rossman (edrossma@us.ibm.com) * * Hotplug & misc device support: Jochen Roehrig (roehrig@de.ibm.com) */ #ifndef __ASM_S390_ZCRYPT_H #define __ASM_S390_ZCRYPT_H #define ZCRYPT_VERSION 2 #define ZCRYPT_RELEASE 2 #define ZCRYPT_VARIANT 1 #include <linux/ioctl.h> #include <linux/compiler.h> #include <linux/types.h> /* Name of the zcrypt device driver. */ #define ZCRYPT_NAME "zcrypt" /** * struct ica_rsa_modexpo * * Requirements: * - outputdatalength is at least as large as inputdatalength. * - All key parts are right justified in their fields, padded on * the left with zeroes. * - length(b_key) = inputdatalength * - length(n_modulus) = inputdatalength */ struct ica_rsa_modexpo { __u8 __user *inputdata; __u32 inputdatalength; __u8 __user *outputdata; __u32 outputdatalength; __u8 __user *b_key; __u8 __user *n_modulus; }; /** * struct ica_rsa_modexpo_crt * * Requirements: * - inputdatalength is even. * - outputdatalength is at least as large as inputdatalength. * - All key parts are right justified in their fields, padded on * the left with zeroes. * - length(bp_key) = inputdatalength/2 + 8 * - length(bq_key) = inputdatalength/2 * - length(np_key) = inputdatalength/2 + 8 * - length(nq_key) = inputdatalength/2 * - length(u_mult_inv) = inputdatalength/2 + 8 */ struct ica_rsa_modexpo_crt { __u8 __user *inputdata; __u32 inputdatalength; __u8 __user *outputdata; __u32 outputdatalength; __u8 __user *bp_key; __u8 __user *bq_key; __u8 __user *np_prime; __u8 __user *nq_prime; __u8 __user *u_mult_inv; }; /** * CPRBX * Note that all shorts and ints are big-endian. * All pointer fields are 16 bytes long, and mean nothing. * * A request CPRB is followed by a request_parameter_block. * * The request (or reply) parameter block is organized thus: * function code * VUD block * key block */ struct CPRBX { __u16 cprb_len; /* CPRB length 220 */ __u8 cprb_ver_id; /* CPRB version id. 0x02 */ __u8 pad_000[3]; /* Alignment pad bytes */ __u8 func_id[2]; /* function id 0x5432 */ __u8 cprb_flags[4]; /* Flags */ __u32 req_parml; /* request parameter buffer len */ __u32 req_datal; /* request data buffer */ __u32 rpl_msgbl; /* reply message block length */ __u32 rpld_parml; /* replied parameter block len */ __u32 rpl_datal; /* reply data block len */ __u32 rpld_datal; /* replied data block len */ __u32 req_extbl; /* request extension block len */ __u8 pad_001[4]; /* reserved */ __u32 rpld_extbl; /* replied extension block len */ __u8 padx000[16 - sizeof(__u8 *)]; __u8 __user *req_parmb; /* request parm block 'address' */ __u8 padx001[16 - sizeof(__u8 *)]; __u8 __user *req_datab; /* request data block 'address' */ __u8 padx002[16 - sizeof(__u8 *)]; __u8 __user *rpl_parmb; /* reply parm block 'address' */ __u8 padx003[16 - sizeof(__u8 *)]; __u8 __user *rpl_datab; /* reply data block 'address' */ __u8 padx004[16 - sizeof(__u8 *)]; __u8 __user *req_extb; /* request extension block 'addr'*/ __u8 padx005[16 - sizeof(__u8 *)]; __u8 __user *rpl_extb; /* reply extension block 'address'*/ __u16 ccp_rtcode; /* server return code */ __u16 ccp_rscode; /* server reason code */ __u32 mac_data_len; /* Mac Data Length */ __u8 logon_id[8]; /* Logon Identifier */ __u8 mac_value[8]; /* Mac Value */ __u8 mac_content_flgs; /* Mac content flag byte */ __u8 pad_002; /* Alignment */ __u16 domain; /* Domain */ __u8 usage_domain[4]; /* Usage domain */ __u8 cntrl_domain[4]; /* Control domain */ __u8 S390enf_mask[4]; /* S/390 enforcement mask */ __u8 pad_004[36]; /* reserved */ } __attribute__((packed)); /** * xcRB */ struct ica_xcRB { __u16 agent_ID; __u32 user_defined; __u16 request_ID; __u32 request_control_blk_length; __u8 _padding1[16 - sizeof(__u8 *)]; __u8 __user *request_control_blk_addr; __u32 request_data_length; __u8 _padding2[16 - sizeof(__u8 *)]; __u8 __user *request_data_address; __u32 reply_control_blk_length; __u8 _padding3[16 - sizeof(__u8 *)]; __u8 __user *reply_control_blk_addr; __u32 reply_data_length; __u8 __padding4[16 - sizeof(__u8 *)]; __u8 __user *reply_data_addr; __u16 priority_window; __u32 status; } __attribute__((packed)); /** * struct ep11_cprb - EP11 connectivity programming request block * @cprb_len: CPRB header length [0x0020] * @cprb_ver_id: CPRB version id. [0x04] * @pad_000: Alignment pad bytes * @flags: Admin bit [0x80], Special bit [0x20] * @func_id: Function id / subtype [0x5434] "T4" * @source_id: Source id [originator id] * @target_id: Target id [usage/ctrl domain id] * @ret_code: Return code * @reserved1: Reserved * @reserved2: Reserved * @payload_len: Payload length */ struct ep11_cprb { __u16 cprb_len; __u8 cprb_ver_id; __u8 pad_000[2]; __u8 flags; __u8 func_id[2]; __u32 source_id; __u32 target_id; __u32 ret_code; __u32 reserved1; __u32 reserved2; __u32 payload_len; } __attribute__((packed)); /** * struct ep11_target_dev - EP11 target device list * @ap_id: AP device id * @dom_id: Usage domain id */ struct ep11_target_dev { __u16 ap_id; __u16 dom_id; }; /** * struct ep11_urb - EP11 user request block * @targets_num: Number of target adapters * @targets: Addr to target adapter list * @weight: Level of request priority * @req_no: Request id/number * @req_len: Request length * @req: Addr to request block * @resp_len: Response length * @resp: Addr to response block */ struct ep11_urb { __u16 targets_num; __u8 __user *targets; __u64 weight; __u64 req_no; __u64 req_len; __u8 __user *req; __u64 resp_len; __u8 __user *resp; } __attribute__((packed)); /** * struct zcrypt_device_status_ext * @hwtype: raw hardware type * @qid: 8 bit device index, 8 bit domain * @functions: AP device function bit field 'abcdef' * a, b, c = reserved * d = CCA coprocessor * e = Accelerator * f = EP11 coprocessor * @online online status * @reserved reserved */ struct zcrypt_device_status_ext { unsigned int hwtype:8; unsigned int qid:16; unsigned int online:1; unsigned int functions:6; unsigned int reserved:1; }; #define MAX_ZDEV_CARDIDS_EXT 256 #define MAX_ZDEV_DOMAINS_EXT 256 /* Maximum number of zcrypt devices */ #define MAX_ZDEV_ENTRIES_EXT (MAX_ZDEV_CARDIDS_EXT * MAX_ZDEV_DOMAINS_EXT) /* Device matrix of all zcrypt devices */ struct zcrypt_device_matrix_ext { struct zcrypt_device_status_ext device[MAX_ZDEV_ENTRIES_EXT]; }; #define AUTOSELECT 0xFFFFFFFF #define AUTOSEL_AP ((__u16) 0xFFFF) #define AUTOSEL_DOM ((__u16) 0xFFFF) #define ZCRYPT_IOCTL_MAGIC 'z' /** * Interface notes: * * The ioctl()s which are implemented (along with relevant details) * are: * * ICARSAMODEXPO * Perform an RSA operation using a Modulus-Exponent pair * This takes an ica_rsa_modexpo struct as its arg. * * NOTE: please refer to the comments preceding this structure * for the implementation details for the contents of the * block * * ICARSACRT * Perform an RSA operation using a Chinese-Remainder Theorem key * This takes an ica_rsa_modexpo_crt struct as its arg. * * NOTE: please refer to the comments preceding this structure * for the implementation details for the contents of the * block * * ZSECSENDCPRB * Send an arbitrary CPRB to a crypto card. * * ZSENDEP11CPRB * Send an arbitrary EP11 CPRB to an EP11 coprocessor crypto card. * * ZCRYPT_DEVICE_STATUS * The given struct zcrypt_device_matrix_ext is updated with * status information for each currently known apqn. * * ZCRYPT_STATUS_MASK * Return an MAX_ZDEV_CARDIDS_EXT element array of unsigned chars for the * status of all devices. * 0x01: PCICA * 0x02: PCICC * 0x03: PCIXCC_MCL2 * 0x04: PCIXCC_MCL3 * 0x05: CEX2C * 0x06: CEX2A * 0x07: CEX3C * 0x08: CEX3A * 0x0a: CEX4 * 0x0b: CEX5 * 0x0c: CEX6, CEX7 or CEX8 * 0x0d: device is disabled * * ZCRYPT_QDEPTH_MASK * Return an MAX_ZDEV_CARDIDS_EXT element array of unsigned chars for the * queue depth of all devices. * * ZCRYPT_PERDEV_REQCNT * Return an MAX_ZDEV_CARDIDS_EXT element array of unsigned integers for * the number of successfully completed requests per device since the * device was detected and made available. * */ /** * Supported ioctl calls */ #define ICARSAMODEXPO _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x05, 0) #define ICARSACRT _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x06, 0) #define ZSECSENDCPRB _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x81, 0) #define ZSENDEP11CPRB _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x04, 0) #define ZCRYPT_DEVICE_STATUS _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x5f, 0) #define ZCRYPT_STATUS_MASK _IOR(ZCRYPT_IOCTL_MAGIC, 0x58, char[MAX_ZDEV_CARDIDS_EXT]) #define ZCRYPT_QDEPTH_MASK _IOR(ZCRYPT_IOCTL_MAGIC, 0x59, char[MAX_ZDEV_CARDIDS_EXT]) #define ZCRYPT_PERDEV_REQCNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x5a, int[MAX_ZDEV_CARDIDS_EXT]) /* * Support for multiple zcrypt device nodes. */ /* Nr of minor device node numbers to allocate. */ #define ZCRYPT_MAX_MINOR_NODES 256 /* Max amount of possible ioctls */ #define MAX_ZDEV_IOCTLS (1 << _IOC_NRBITS) /* * Only deprecated defines, structs and ioctls below this line. */ /* Deprecated: use MAX_ZDEV_CARDIDS_EXT */ #define MAX_ZDEV_CARDIDS 64 /* Deprecated: use MAX_ZDEV_DOMAINS_EXT */ #define MAX_ZDEV_DOMAINS 256 /* Deprecated: use MAX_ZDEV_ENTRIES_EXT */ #define MAX_ZDEV_ENTRIES (MAX_ZDEV_CARDIDS * MAX_ZDEV_DOMAINS) /* Deprecated: use struct zcrypt_device_status_ext */ struct zcrypt_device_status { unsigned int hwtype:8; unsigned int qid:14; unsigned int online:1; unsigned int functions:6; unsigned int reserved:3; }; /* Deprecated: use struct zcrypt_device_matrix_ext */ struct zcrypt_device_matrix { struct zcrypt_device_status device[MAX_ZDEV_ENTRIES]; }; /* Deprecated: use ZCRYPT_DEVICE_STATUS */ #define ZDEVICESTATUS _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x4f, 0) /* Deprecated: use ZCRYPT_STATUS_MASK */ #define Z90STAT_STATUS_MASK _IOR(ZCRYPT_IOCTL_MAGIC, 0x48, char[64]) /* Deprecated: use ZCRYPT_QDEPTH_MASK */ #define Z90STAT_QDEPTH_MASK _IOR(ZCRYPT_IOCTL_MAGIC, 0x49, char[64]) /* Deprecated: use ZCRYPT_PERDEV_REQCNT */ #define Z90STAT_PERDEV_REQCNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4a, int[64]) /* Deprecated: use sysfs to query these values */ #define Z90STAT_REQUESTQ_COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x44, int) #define Z90STAT_PENDINGQ_COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x45, int) #define Z90STAT_TOTALOPEN_COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x46, int) #define Z90STAT_DOMAIN_INDEX _IOR(ZCRYPT_IOCTL_MAGIC, 0x47, int) /* * The ioctl number ranges 0x40 - 0x42 and 0x4b - 0x4e had been used in the * past, don't assign new ioctls for these. */ #endif /* __ASM_S390_ZCRYPT_H */ PK ! �~p�r1 r1 dasd.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com> * Bugreports.to..: <Linux390@de.ibm.com> * Copyright IBM Corp. 1999, 2000 * EMC Symmetrix ioctl Copyright EMC Corporation, 2008 * Author.........: Nigel Hislop <hislop_nigel@emc.com> * * This file is the interface of the DASD device driver, which is exported to user space * any future changes wrt the API will result in a change of the APIVERSION reported * to userspace by the DASDAPIVER-ioctl * */ #ifndef DASD_H #define DASD_H #include <linux/types.h> #include <linux/ioctl.h> #define DASD_IOCTL_LETTER 'D' #define DASD_API_VERSION 6 /* * struct dasd_information2_t * represents any data about the device, which is visible to userspace. * including foramt and featueres. */ typedef struct dasd_information2_t { unsigned int devno; /* S/390 devno */ unsigned int real_devno; /* for aliases */ unsigned int schid; /* S/390 subchannel identifier */ unsigned int cu_type : 16; /* from SenseID */ unsigned int cu_model : 8; /* from SenseID */ unsigned int dev_type : 16; /* from SenseID */ unsigned int dev_model : 8; /* from SenseID */ unsigned int open_count; unsigned int req_queue_len; unsigned int chanq_len; /* length of chanq */ char type[4]; /* from discipline.name, 'none' for unknown */ unsigned int status; /* current device level */ unsigned int label_block; /* where to find the VOLSER */ unsigned int FBA_layout; /* fixed block size (like AIXVOL) */ unsigned int characteristics_size; unsigned int confdata_size; char characteristics[64]; /* from read_device_characteristics */ char configuration_data[256]; /* from read_configuration_data */ unsigned int format; /* format info like formatted/cdl/ldl/... */ unsigned int features; /* dasd features like 'ro',... */ unsigned int reserved0; /* reserved for further use ,... */ unsigned int reserved1; /* reserved for further use ,... */ unsigned int reserved2; /* reserved for further use ,... */ unsigned int reserved3; /* reserved for further use ,... */ unsigned int reserved4; /* reserved for further use ,... */ unsigned int reserved5; /* reserved for further use ,... */ unsigned int reserved6; /* reserved for further use ,... */ unsigned int reserved7; /* reserved for further use ,... */ } dasd_information2_t; /* * values to be used for dasd_information_t.format * 0x00: NOT formatted * 0x01: Linux disc layout * 0x02: Common disc layout */ #define DASD_FORMAT_NONE 0 #define DASD_FORMAT_LDL 1 #define DASD_FORMAT_CDL 2 /* * values to be used for dasd_information_t.features * 0x100: default features * 0x001: readonly (ro) * 0x002: use diag discipline (diag) * 0x004: set the device initially online (internal use only) * 0x008: enable ERP related logging * 0x010: allow I/O to fail on lost paths * 0x020: allow I/O to fail when a lock was stolen * 0x040: give access to raw eckd data * 0x080: enable discard support * 0x100: enable autodisable for IFCC errors (default) * 0x200: enable requeue of all requests on autoquiesce */ #define DASD_FEATURE_READONLY 0x001 #define DASD_FEATURE_USEDIAG 0x002 #define DASD_FEATURE_INITIAL_ONLINE 0x004 #define DASD_FEATURE_ERPLOG 0x008 #define DASD_FEATURE_FAILFAST 0x010 #define DASD_FEATURE_FAILONSLCK 0x020 #define DASD_FEATURE_USERAW 0x040 #define DASD_FEATURE_DISCARD 0x080 #define DASD_FEATURE_PATH_AUTODISABLE 0x100 #define DASD_FEATURE_REQUEUEQUIESCE 0x200 #define DASD_FEATURE_DEFAULT DASD_FEATURE_PATH_AUTODISABLE #define DASD_PARTN_BITS 2 /* * struct dasd_information_t * represents any data about the data, which is visible to userspace */ typedef struct dasd_information_t { unsigned int devno; /* S/390 devno */ unsigned int real_devno; /* for aliases */ unsigned int schid; /* S/390 subchannel identifier */ unsigned int cu_type : 16; /* from SenseID */ unsigned int cu_model : 8; /* from SenseID */ unsigned int dev_type : 16; /* from SenseID */ unsigned int dev_model : 8; /* from SenseID */ unsigned int open_count; unsigned int req_queue_len; unsigned int chanq_len; /* length of chanq */ char type[4]; /* from discipline.name, 'none' for unknown */ unsigned int status; /* current device level */ unsigned int label_block; /* where to find the VOLSER */ unsigned int FBA_layout; /* fixed block size (like AIXVOL) */ unsigned int characteristics_size; unsigned int confdata_size; char characteristics[64]; /* from read_device_characteristics */ char configuration_data[256]; /* from read_configuration_data */ } dasd_information_t; /* * Read Subsystem Data - Performance Statistics */ typedef struct dasd_rssd_perf_stats_t { unsigned char invalid:1; unsigned char format:3; unsigned char data_format:4; unsigned char unit_address; unsigned short device_status; unsigned int nr_read_normal; unsigned int nr_read_normal_hits; unsigned int nr_write_normal; unsigned int nr_write_fast_normal_hits; unsigned int nr_read_seq; unsigned int nr_read_seq_hits; unsigned int nr_write_seq; unsigned int nr_write_fast_seq_hits; unsigned int nr_read_cache; unsigned int nr_read_cache_hits; unsigned int nr_write_cache; unsigned int nr_write_fast_cache_hits; unsigned int nr_inhibit_cache; unsigned int nr_bybass_cache; unsigned int nr_seq_dasd_to_cache; unsigned int nr_dasd_to_cache; unsigned int nr_cache_to_dasd; unsigned int nr_delayed_fast_write; unsigned int nr_normal_fast_write; unsigned int nr_seq_fast_write; unsigned int nr_cache_miss; unsigned char status2; unsigned int nr_quick_write_promotes; unsigned char reserved; unsigned short ssid; unsigned char reseved2[96]; } __attribute__((packed)) dasd_rssd_perf_stats_t; /* * struct profile_info_t * holds the profinling information */ typedef struct dasd_profile_info_t { unsigned int dasd_io_reqs; /* number of requests processed at all */ unsigned int dasd_io_sects; /* number of sectors processed at all */ unsigned int dasd_io_secs[32]; /* histogram of request's sizes */ unsigned int dasd_io_times[32]; /* histogram of requests's times */ unsigned int dasd_io_timps[32]; /* histogram of requests's times per sector */ unsigned int dasd_io_time1[32]; /* histogram of time from build to start */ unsigned int dasd_io_time2[32]; /* histogram of time from start to irq */ unsigned int dasd_io_time2ps[32]; /* histogram of time from start to irq */ unsigned int dasd_io_time3[32]; /* histogram of time from irq to end */ unsigned int dasd_io_nr_req[32]; /* histogram of # of requests in chanq */ } dasd_profile_info_t; /* * struct format_data_t * represents all data necessary to format a dasd */ typedef struct format_data_t { unsigned int start_unit; /* from track */ unsigned int stop_unit; /* to track */ unsigned int blksize; /* sectorsize */ unsigned int intensity; } format_data_t; /* * values to be used for format_data_t.intensity * 0/8: normal format * 1/9: also write record zero * 3/11: also write home address * 4/12: invalidate track */ #define DASD_FMT_INT_FMT_R0 1 /* write record zero */ #define DASD_FMT_INT_FMT_HA 2 /* write home address, also set FMT_R0 ! */ #define DASD_FMT_INT_INVAL 4 /* invalidate tracks */ #define DASD_FMT_INT_COMPAT 8 /* use OS/390 compatible disk layout */ #define DASD_FMT_INT_FMT_NOR0 16 /* remove permission to write record zero */ #define DASD_FMT_INT_ESE_FULL 32 /* release space for entire volume */ /* * struct format_check_t * represents all data necessary to evaluate the format of * different tracks of a dasd */ typedef struct format_check_t { /* Input */ struct format_data_t expect; /* Output */ unsigned int result; /* Error indication (DASD_FMT_ERR_*) */ unsigned int unit; /* Track that is in error */ unsigned int rec; /* Record that is in error */ unsigned int num_records; /* Records in the track in error */ unsigned int blksize; /* Blocksize of first record in error */ unsigned int key_length; /* Key length of first record in error */ } format_check_t; /* Values returned in format_check_t when a format error is detected: */ /* Too few records were found on a single track */ #define DASD_FMT_ERR_TOO_FEW_RECORDS 1 /* Too many records were found on a single track */ #define DASD_FMT_ERR_TOO_MANY_RECORDS 2 /* Blocksize/data-length of a record was wrong */ #define DASD_FMT_ERR_BLKSIZE 3 /* A record ID is defined by cylinder, head, and record number (CHR). */ /* On mismatch, this error is set */ #define DASD_FMT_ERR_RECORD_ID 4 /* If key-length was != 0 */ #define DASD_FMT_ERR_KEY_LENGTH 5 /* * struct attrib_data_t * represents the operation (cache) bits for the device. * Used in DE to influence caching of the DASD. */ typedef struct attrib_data_t { unsigned char operation:3; /* cache operation mode */ unsigned char reserved:5; /* cache operation mode */ __u16 nr_cyl; /* no of cyliners for read ahaed */ __u8 reserved2[29]; /* for future use */ } __attribute__ ((packed)) attrib_data_t; /* definition of operation (cache) bits within attributes of DE */ #define DASD_NORMAL_CACHE 0x0 #define DASD_BYPASS_CACHE 0x1 #define DASD_INHIBIT_LOAD 0x2 #define DASD_SEQ_ACCESS 0x3 #define DASD_SEQ_PRESTAGE 0x4 #define DASD_REC_ACCESS 0x5 /* * Perform EMC Symmetrix I/O */ typedef struct dasd_symmio_parms { unsigned char reserved[8]; /* compat with older releases */ unsigned long long psf_data; /* char * cast to u64 */ unsigned long long rssd_result; /* char * cast to u64 */ int psf_data_len; int rssd_result_len; } __attribute__ ((packed)) dasd_symmio_parms_t; /* * Data returned by Sense Path Group ID (SNID) */ struct dasd_snid_data { struct { __u8 group:2; __u8 reserve:2; __u8 mode:1; __u8 res:3; } __attribute__ ((packed)) path_state; __u8 pgid[11]; } __attribute__ ((packed)); struct dasd_snid_ioctl_data { struct dasd_snid_data data; __u8 path_mask; } __attribute__ ((packed)); /******************************************************************************** * SECTION: Definition of IOCTLs * * Here ist how the ioctl-nr should be used: * 0 - 31 DASD driver itself * 32 - 239 still open * 240 - 255 reserved for EMC *******************************************************************************/ /* Disable the volume (for Linux) */ #define BIODASDDISABLE _IO(DASD_IOCTL_LETTER,0) /* Enable the volume (for Linux) */ #define BIODASDENABLE _IO(DASD_IOCTL_LETTER,1) /* Issue a reserve/release command, rsp. */ #define BIODASDRSRV _IO(DASD_IOCTL_LETTER,2) /* reserve */ #define BIODASDRLSE _IO(DASD_IOCTL_LETTER,3) /* release */ #define BIODASDSLCK _IO(DASD_IOCTL_LETTER,4) /* steal lock */ /* reset profiling information of a device */ #define BIODASDPRRST _IO(DASD_IOCTL_LETTER,5) /* Quiesce IO on device */ #define BIODASDQUIESCE _IO(DASD_IOCTL_LETTER,6) /* Resume IO on device */ #define BIODASDRESUME _IO(DASD_IOCTL_LETTER,7) /* Abort all I/O on a device */ #define BIODASDABORTIO _IO(DASD_IOCTL_LETTER, 240) /* Allow I/O on a device */ #define BIODASDALLOWIO _IO(DASD_IOCTL_LETTER, 241) /* retrieve API version number */ #define DASDAPIVER _IOR(DASD_IOCTL_LETTER,0,int) /* Get information on a dasd device */ #define BIODASDINFO _IOR(DASD_IOCTL_LETTER,1,dasd_information_t) /* retrieve profiling information of a device */ #define BIODASDPRRD _IOR(DASD_IOCTL_LETTER,2,dasd_profile_info_t) /* Get information on a dasd device (enhanced) */ #define BIODASDINFO2 _IOR(DASD_IOCTL_LETTER,3,dasd_information2_t) /* Performance Statistics Read */ #define BIODASDPSRD _IOR(DASD_IOCTL_LETTER,4,dasd_rssd_perf_stats_t) /* Get Attributes (cache operations) */ #define BIODASDGATTR _IOR(DASD_IOCTL_LETTER,5,attrib_data_t) /* #define BIODASDFORMAT _IOW(IOCTL_LETTER,0,format_data_t) , deprecated */ #define BIODASDFMT _IOW(DASD_IOCTL_LETTER,1,format_data_t) /* Set Attributes (cache operations) */ #define BIODASDSATTR _IOW(DASD_IOCTL_LETTER,2,attrib_data_t) /* Release Allocated Space */ #define BIODASDRAS _IOW(DASD_IOCTL_LETTER, 3, format_data_t) /* Get Sense Path Group ID (SNID) data */ #define BIODASDSNID _IOWR(DASD_IOCTL_LETTER, 1, struct dasd_snid_ioctl_data) /* Check device format according to format_check_t */ #define BIODASDCHECKFMT _IOWR(DASD_IOCTL_LETTER, 2, format_check_t) #define BIODASDSYMMIO _IOWR(DASD_IOCTL_LETTER, 240, dasd_symmio_parms_t) #endif /* DASD_H */ PK ! ��w�s s vtoc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * This file contains volume label definitions for DASD devices. * * Copyright IBM Corp. 2005 * * Author(s): Volker Sameske <sameske@de.ibm.com> * */ #ifndef _ASM_S390_VTOC_H #define _ASM_S390_VTOC_H #include <linux/types.h> struct vtoc_ttr { __u16 tt; __u8 r; } __attribute__ ((packed)); struct vtoc_cchhb { __u16 cc; __u16 hh; __u8 b; } __attribute__ ((packed)); struct vtoc_cchh { __u16 cc; __u16 hh; } __attribute__ ((packed)); struct vtoc_labeldate { __u8 year; __u16 day; } __attribute__ ((packed)); struct vtoc_volume_label_cdl { char volkey[4]; /* volume key = volume label */ char vollbl[4]; /* volume label */ char volid[6]; /* volume identifier */ __u8 security; /* security byte */ struct vtoc_cchhb vtoc; /* VTOC address */ char res1[5]; /* reserved */ char cisize[4]; /* CI-size for FBA,... */ /* ...blanks for CKD */ char blkperci[4]; /* no of blocks per CI (FBA), blanks for CKD */ char labperci[4]; /* no of labels per CI (FBA), blanks for CKD */ char res2[4]; /* reserved */ char lvtoc[14]; /* owner code for LVTOC */ char res3[29]; /* reserved */ } __attribute__ ((packed)); struct vtoc_volume_label_ldl { char vollbl[4]; /* volume label */ char volid[6]; /* volume identifier */ char res3[69]; /* reserved */ char ldl_version; /* version number, valid for ldl format */ __u64 formatted_blocks; /* valid when ldl_version >= f2 */ } __attribute__ ((packed)); struct vtoc_extent { __u8 typeind; /* extent type indicator */ __u8 seqno; /* extent sequence number */ struct vtoc_cchh llimit; /* starting point of this extent */ struct vtoc_cchh ulimit; /* ending point of this extent */ } __attribute__ ((packed)); struct vtoc_dev_const { __u16 DS4DSCYL; /* number of logical cyls */ __u16 DS4DSTRK; /* number of tracks in a logical cylinder */ __u16 DS4DEVTK; /* device track length */ __u8 DS4DEVI; /* non-last keyed record overhead */ __u8 DS4DEVL; /* last keyed record overhead */ __u8 DS4DEVK; /* non-keyed record overhead differential */ __u8 DS4DEVFG; /* flag byte */ __u16 DS4DEVTL; /* device tolerance */ __u8 DS4DEVDT; /* number of DSCB's per track */ __u8 DS4DEVDB; /* number of directory blocks per track */ } __attribute__ ((packed)); struct vtoc_format1_label { char DS1DSNAM[44]; /* data set name */ __u8 DS1FMTID; /* format identifier */ char DS1DSSN[6]; /* data set serial number */ __u16 DS1VOLSQ; /* volume sequence number */ struct vtoc_labeldate DS1CREDT; /* creation date: ydd */ struct vtoc_labeldate DS1EXPDT; /* expiration date */ __u8 DS1NOEPV; /* number of extents on volume */ __u8 DS1NOBDB; /* no. of bytes used in last direction blk */ __u8 DS1FLAG1; /* flag 1 */ char DS1SYSCD[13]; /* system code */ struct vtoc_labeldate DS1REFD; /* date last referenced */ __u8 DS1SMSFG; /* system managed storage indicators */ __u8 DS1SCXTF; /* sec. space extension flag byte */ __u16 DS1SCXTV; /* secondary space extension value */ __u8 DS1DSRG1; /* data set organisation byte 1 */ __u8 DS1DSRG2; /* data set organisation byte 2 */ __u8 DS1RECFM; /* record format */ __u8 DS1OPTCD; /* option code */ __u16 DS1BLKL; /* block length */ __u16 DS1LRECL; /* record length */ __u8 DS1KEYL; /* key length */ __u16 DS1RKP; /* relative key position */ __u8 DS1DSIND; /* data set indicators */ __u8 DS1SCAL1; /* secondary allocation flag byte */ char DS1SCAL3[3]; /* secondary allocation quantity */ struct vtoc_ttr DS1LSTAR; /* last used track and block on track */ __u16 DS1TRBAL; /* space remaining on last used track */ __u16 res1; /* reserved */ struct vtoc_extent DS1EXT1; /* first extent description */ struct vtoc_extent DS1EXT2; /* second extent description */ struct vtoc_extent DS1EXT3; /* third extent description */ struct vtoc_cchhb DS1PTRDS; /* possible pointer to f2 or f3 DSCB */ } __attribute__ ((packed)); struct vtoc_format4_label { char DS4KEYCD[44]; /* key code for VTOC labels: 44 times 0x04 */ __u8 DS4IDFMT; /* format identifier */ struct vtoc_cchhb DS4HPCHR; /* highest address of a format 1 DSCB */ __u16 DS4DSREC; /* number of available DSCB's */ struct vtoc_cchh DS4HCCHH; /* CCHH of next available alternate track */ __u16 DS4NOATK; /* number of remaining alternate tracks */ __u8 DS4VTOCI; /* VTOC indicators */ __u8 DS4NOEXT; /* number of extents in VTOC */ __u8 DS4SMSFG; /* system managed storage indicators */ __u8 DS4DEVAC; /* number of alternate cylinders. * Subtract from first two bytes of * DS4DEVSZ to get number of usable * cylinders. can be zero. valid * only if DS4DEVAV on. */ struct vtoc_dev_const DS4DEVCT; /* device constants */ char DS4AMTIM[8]; /* VSAM time stamp */ char DS4AMCAT[3]; /* VSAM catalog indicator */ char DS4R2TIM[8]; /* VSAM volume/catalog match time stamp */ char res1[5]; /* reserved */ char DS4F6PTR[5]; /* pointer to first format 6 DSCB */ struct vtoc_extent DS4VTOCE; /* VTOC extent description */ char res2[10]; /* reserved */ __u8 DS4EFLVL; /* extended free-space management level */ struct vtoc_cchhb DS4EFPTR; /* pointer to extended free-space info */ char res3; /* reserved */ __u32 DS4DCYL; /* number of logical cyls */ char res4[2]; /* reserved */ __u8 DS4DEVF2; /* device flags */ char res5; /* reserved */ } __attribute__ ((packed)); struct vtoc_ds5ext { __u16 t; /* RTA of the first track of free extent */ __u16 fc; /* number of whole cylinders in free ext. */ __u8 ft; /* number of remaining free tracks */ } __attribute__ ((packed)); struct vtoc_format5_label { char DS5KEYID[4]; /* key identifier */ struct vtoc_ds5ext DS5AVEXT; /* first available (free-space) extent. */ struct vtoc_ds5ext DS5EXTAV[7]; /* seven available extents */ __u8 DS5FMTID; /* format identifier */ struct vtoc_ds5ext DS5MAVET[18]; /* eighteen available extents */ struct vtoc_cchhb DS5PTRDS; /* pointer to next format5 DSCB */ } __attribute__ ((packed)); struct vtoc_ds7ext { __u32 a; /* starting RTA value */ __u32 b; /* ending RTA value + 1 */ } __attribute__ ((packed)); struct vtoc_format7_label { char DS7KEYID[4]; /* key identifier */ struct vtoc_ds7ext DS7EXTNT[5]; /* space for 5 extent descriptions */ __u8 DS7FMTID; /* format identifier */ struct vtoc_ds7ext DS7ADEXT[11]; /* space for 11 extent descriptions */ char res1[2]; /* reserved */ struct vtoc_cchhb DS7PTRDS; /* pointer to next FMT7 DSCB */ } __attribute__ ((packed)); struct vtoc_cms_label { __u8 label_id[4]; /* Label identifier */ __u8 vol_id[6]; /* Volid */ __u16 version_id; /* Version identifier */ __u32 block_size; /* Disk block size */ __u32 origin_ptr; /* Disk origin pointer */ __u32 usable_count; /* Number of usable cylinders/blocks */ __u32 formatted_count; /* Maximum number of formatted cylinders/ * blocks */ __u32 block_count; /* Disk size in CMS blocks */ __u32 used_count; /* Number of CMS blocks in use */ __u32 fst_size; /* File Status Table (FST) size */ __u32 fst_count; /* Number of FSTs per CMS block */ __u8 format_date[6]; /* Disk FORMAT date */ __u8 reserved1[2]; __u32 disk_offset; /* Disk offset when reserved*/ __u32 map_block; /* Allocation Map Block with next hole */ __u32 hblk_disp; /* Displacement into HBLK data of next hole */ __u32 user_disp; /* Displacement into user part of Allocation * map */ __u8 reserved2[4]; __u8 segment_name[8]; /* Name of shared segment */ } __attribute__ ((packed)); #endif /* _ASM_S390_VTOC_H */ PK ! �q�� � hwcap.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Copied from arch/arm64/include/asm/hwcap.h * * Copyright (C) 2012 ARM Ltd. * Copyright (C) 2017 SiFive */ #ifndef _UAPI_ASM_RISCV_HWCAP_H #define _UAPI_ASM_RISCV_HWCAP_H /* * Linux saves the floating-point registers according to the ISA Linux is * executing on, as opposed to the ISA the user program is compiled for. This * is necessary for a handful of esoteric use cases: for example, userspace * threading libraries must be able to examine the actual machine state in * order to fully reconstruct the state of a thread. */ #define COMPAT_HWCAP_ISA_I (1 << ('I' - 'A')) #define COMPAT_HWCAP_ISA_M (1 << ('M' - 'A')) #define COMPAT_HWCAP_ISA_A (1 << ('A' - 'A')) #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) #endif /* _UAPI_ASM_RISCV_HWCAP_H */ PK ! d���2 2 reg.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Various register offset definitions for debuggers, core file * examiners and whatnot. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995, 1999 Ralf Baechle * Copyright (C) 1995, 1999 Silicon Graphics */ #ifndef __UAPI_ASM_MIPS_REG_H #define __UAPI_ASM_MIPS_REG_H #define MIPS32_EF_R0 6 #define MIPS32_EF_R1 7 #define MIPS32_EF_R2 8 #define MIPS32_EF_R3 9 #define MIPS32_EF_R4 10 #define MIPS32_EF_R5 11 #define MIPS32_EF_R6 12 #define MIPS32_EF_R7 13 #define MIPS32_EF_R8 14 #define MIPS32_EF_R9 15 #define MIPS32_EF_R10 16 #define MIPS32_EF_R11 17 #define MIPS32_EF_R12 18 #define MIPS32_EF_R13 19 #define MIPS32_EF_R14 20 #define MIPS32_EF_R15 21 #define MIPS32_EF_R16 22 #define MIPS32_EF_R17 23 #define MIPS32_EF_R18 24 #define MIPS32_EF_R19 25 #define MIPS32_EF_R20 26 #define MIPS32_EF_R21 27 #define MIPS32_EF_R22 28 #define MIPS32_EF_R23 29 #define MIPS32_EF_R24 30 #define MIPS32_EF_R25 31 /* * k0/k1 unsaved */ #define MIPS32_EF_R26 32 #define MIPS32_EF_R27 33 #define MIPS32_EF_R28 34 #define MIPS32_EF_R29 35 #define MIPS32_EF_R30 36 #define MIPS32_EF_R31 37 /* * Saved special registers */ #define MIPS32_EF_LO 38 #define MIPS32_EF_HI 39 #define MIPS32_EF_CP0_EPC 40 #define MIPS32_EF_CP0_BADVADDR 41 #define MIPS32_EF_CP0_STATUS 42 #define MIPS32_EF_CP0_CAUSE 43 #define MIPS32_EF_UNUSED0 44 #define MIPS32_EF_SIZE 180 #define MIPS64_EF_R0 0 #define MIPS64_EF_R1 1 #define MIPS64_EF_R2 2 #define MIPS64_EF_R3 3 #define MIPS64_EF_R4 4 #define MIPS64_EF_R5 5 #define MIPS64_EF_R6 6 #define MIPS64_EF_R7 7 #define MIPS64_EF_R8 8 #define MIPS64_EF_R9 9 #define MIPS64_EF_R10 10 #define MIPS64_EF_R11 11 #define MIPS64_EF_R12 12 #define MIPS64_EF_R13 13 #define MIPS64_EF_R14 14 #define MIPS64_EF_R15 15 #define MIPS64_EF_R16 16 #define MIPS64_EF_R17 17 #define MIPS64_EF_R18 18 #define MIPS64_EF_R19 19 #define MIPS64_EF_R20 20 #define MIPS64_EF_R21 21 #define MIPS64_EF_R22 22 #define MIPS64_EF_R23 23 #define MIPS64_EF_R24 24 #define MIPS64_EF_R25 25 /* * k0/k1 unsaved */ #define MIPS64_EF_R26 26 #define MIPS64_EF_R27 27 #define MIPS64_EF_R28 28 #define MIPS64_EF_R29 29 #define MIPS64_EF_R30 30 #define MIPS64_EF_R31 31 /* * Saved special registers */ #define MIPS64_EF_LO 32 #define MIPS64_EF_HI 33 #define MIPS64_EF_CP0_EPC 34 #define MIPS64_EF_CP0_BADVADDR 35 #define MIPS64_EF_CP0_STATUS 36 #define MIPS64_EF_CP0_CAUSE 37 #define MIPS64_EF_SIZE 304 /* size in bytes */ #if _MIPS_SIM == _MIPS_SIM_ABI32 #define EF_R0 MIPS32_EF_R0 #define EF_R1 MIPS32_EF_R1 #define EF_R2 MIPS32_EF_R2 #define EF_R3 MIPS32_EF_R3 #define EF_R4 MIPS32_EF_R4 #define EF_R5 MIPS32_EF_R5 #define EF_R6 MIPS32_EF_R6 #define EF_R7 MIPS32_EF_R7 #define EF_R8 MIPS32_EF_R8 #define EF_R9 MIPS32_EF_R9 #define EF_R10 MIPS32_EF_R10 #define EF_R11 MIPS32_EF_R11 #define EF_R12 MIPS32_EF_R12 #define EF_R13 MIPS32_EF_R13 #define EF_R14 MIPS32_EF_R14 #define EF_R15 MIPS32_EF_R15 #define EF_R16 MIPS32_EF_R16 #define EF_R17 MIPS32_EF_R17 #define EF_R18 MIPS32_EF_R18 #define EF_R19 MIPS32_EF_R19 #define EF_R20 MIPS32_EF_R20 #define EF_R21 MIPS32_EF_R21 #define EF_R22 MIPS32_EF_R22 #define EF_R23 MIPS32_EF_R23 #define EF_R24 MIPS32_EF_R24 #define EF_R25 MIPS32_EF_R25 #define EF_R26 MIPS32_EF_R26 #define EF_R27 MIPS32_EF_R27 #define EF_R28 MIPS32_EF_R28 #define EF_R29 MIPS32_EF_R29 #define EF_R30 MIPS32_EF_R30 #define EF_R31 MIPS32_EF_R31 #define EF_LO MIPS32_EF_LO #define EF_HI MIPS32_EF_HI #define EF_CP0_EPC MIPS32_EF_CP0_EPC #define EF_CP0_BADVADDR MIPS32_EF_CP0_BADVADDR #define EF_CP0_STATUS MIPS32_EF_CP0_STATUS #define EF_CP0_CAUSE MIPS32_EF_CP0_CAUSE #define EF_UNUSED0 MIPS32_EF_UNUSED0 #define EF_SIZE MIPS32_EF_SIZE #elif _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 #define EF_R0 MIPS64_EF_R0 #define EF_R1 MIPS64_EF_R1 #define EF_R2 MIPS64_EF_R2 #define EF_R3 MIPS64_EF_R3 #define EF_R4 MIPS64_EF_R4 #define EF_R5 MIPS64_EF_R5 #define EF_R6 MIPS64_EF_R6 #define EF_R7 MIPS64_EF_R7 #define EF_R8 MIPS64_EF_R8 #define EF_R9 MIPS64_EF_R9 #define EF_R10 MIPS64_EF_R10 #define EF_R11 MIPS64_EF_R11 #define EF_R12 MIPS64_EF_R12 #define EF_R13 MIPS64_EF_R13 #define EF_R14 MIPS64_EF_R14 #define EF_R15 MIPS64_EF_R15 #define EF_R16 MIPS64_EF_R16 #define EF_R17 MIPS64_EF_R17 #define EF_R18 MIPS64_EF_R18 #define EF_R19 MIPS64_EF_R19 #define EF_R20 MIPS64_EF_R20 #define EF_R21 MIPS64_EF_R21 #define EF_R22 MIPS64_EF_R22 #define EF_R23 MIPS64_EF_R23 #define EF_R24 MIPS64_EF_R24 #define EF_R25 MIPS64_EF_R25 #define EF_R26 MIPS64_EF_R26 #define EF_R27 MIPS64_EF_R27 #define EF_R28 MIPS64_EF_R28 #define EF_R29 MIPS64_EF_R29 #define EF_R30 MIPS64_EF_R30 #define EF_R31 MIPS64_EF_R31 #define EF_LO MIPS64_EF_LO #define EF_HI MIPS64_EF_HI #define EF_CP0_EPC MIPS64_EF_CP0_EPC #define EF_CP0_BADVADDR MIPS64_EF_CP0_BADVADDR #define EF_CP0_STATUS MIPS64_EF_CP0_STATUS #define EF_CP0_CAUSE MIPS64_EF_CP0_CAUSE #define EF_SIZE MIPS64_EF_SIZE #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ #endif /* __UAPI_ASM_MIPS_REG_H */ PK ! ���r r inst.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Format of an instruction in memory. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996, 2000 by Ralf Baechle * Copyright (C) 2006 by Thiemo Seufer * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2014 Imagination Technologies Ltd. */ #ifndef _UAPI_ASM_INST_H #define _UAPI_ASM_INST_H #include <asm/bitfield.h> /* * Major opcodes; before MIPS IV cop1x was called cop3. */ enum major_op { spec_op, bcond_op, j_op, jal_op, beq_op, bne_op, blez_op, bgtz_op, addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op, andi_op, ori_op, xori_op, lui_op, cop0_op, cop1_op, cop2_op, cop1x_op, beql_op, bnel_op, blezl_op, bgtzl_op, daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op, spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op, lb_op, lh_op, lwl_op, lw_op, lbu_op, lhu_op, lwr_op, lwu_op, sb_op, sh_op, swl_op, sw_op, sdl_op, sdr_op, swr_op, cache_op, ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op, lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op, sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op, scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op }; /* * func field of spec opcode. */ enum spec_op { sll_op, movc_op, srl_op, sra_op, sllv_op, pmon_op, srlv_op, srav_op, jr_op, jalr_op, movz_op, movn_op, syscall_op, break_op, spim_op, sync_op, mfhi_op, mthi_op, mflo_op, mtlo_op, dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, mult_op, multu_op, div_op, divu_op, dmult_op, dmultu_op, ddiv_op, ddivu_op, add_op, addu_op, sub_op, subu_op, and_op, or_op, xor_op, nor_op, spec3_unused_op, spec4_unused_op, slt_op, sltu_op, dadd_op, daddu_op, dsub_op, dsubu_op, tge_op, tgeu_op, tlt_op, tltu_op, teq_op, seleqz_op, tne_op, selnez_op, dsll_op, spec5_unused_op, dsrl_op, dsra_op, dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op }; /* * func field of spec2 opcode. */ enum spec2_op { madd_op, maddu_op, mul_op, spec2_3_unused_op, msub_op, msubu_op, /* more unused ops */ clz_op = 0x20, clo_op, dclz_op = 0x24, dclo_op, sdbpp_op = 0x3f }; /* * func field of spec3 opcode. */ enum spec3_op { ext_op, dextm_op, dextu_op, dext_op, ins_op, dinsm_op, dinsu_op, dins_op, yield_op = 0x09, lx_op = 0x0a, lwle_op = 0x19, lwre_op = 0x1a, cachee_op = 0x1b, sbe_op = 0x1c, she_op = 0x1d, sce_op = 0x1e, swe_op = 0x1f, bshfl_op = 0x20, swle_op = 0x21, swre_op = 0x22, prefe_op = 0x23, dbshfl_op = 0x24, cache6_op = 0x25, sc6_op = 0x26, scd6_op = 0x27, lbue_op = 0x28, lhue_op = 0x29, lbe_op = 0x2c, lhe_op = 0x2d, lle_op = 0x2e, lwe_op = 0x2f, pref6_op = 0x35, ll6_op = 0x36, lld6_op = 0x37, rdhwr_op = 0x3b }; /* * Bits 10-6 minor opcode for r6 spec mult/div encodings */ enum mult_op { mult_mult_op = 0x0, mult_mul_op = 0x2, mult_muh_op = 0x3, }; enum multu_op { multu_multu_op = 0x0, multu_mulu_op = 0x2, multu_muhu_op = 0x3, }; enum div_op { div_div_op = 0x0, div_div6_op = 0x2, div_mod_op = 0x3, }; enum divu_op { divu_divu_op = 0x0, divu_divu6_op = 0x2, divu_modu_op = 0x3, }; enum dmult_op { dmult_dmult_op = 0x0, dmult_dmul_op = 0x2, dmult_dmuh_op = 0x3, }; enum dmultu_op { dmultu_dmultu_op = 0x0, dmultu_dmulu_op = 0x2, dmultu_dmuhu_op = 0x3, }; enum ddiv_op { ddiv_ddiv_op = 0x0, ddiv_ddiv6_op = 0x2, ddiv_dmod_op = 0x3, }; enum ddivu_op { ddivu_ddivu_op = 0x0, ddivu_ddivu6_op = 0x2, ddivu_dmodu_op = 0x3, }; /* * rt field of bcond opcodes. */ enum rt_op { bltz_op, bgez_op, bltzl_op, bgezl_op, spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, tgei_op, tgeiu_op, tlti_op, tltiu_op, teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, bltzal_op, bgezal_op, bltzall_op, bgezall_op, rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op }; /* * rs field of cop opcodes. */ enum cop_op { mfc_op = 0x00, dmfc_op = 0x01, cfc_op = 0x02, mfhc0_op = 0x02, mfhc_op = 0x03, mtc_op = 0x04, dmtc_op = 0x05, ctc_op = 0x06, mthc0_op = 0x06, mthc_op = 0x07, bc_op = 0x08, bc1eqz_op = 0x09, mfmc0_op = 0x0b, bc1nez_op = 0x0d, wrpgpr_op = 0x0e, cop_op = 0x10, copm_op = 0x18 }; /* * rt field of cop.bc_op opcodes */ enum bcop_op { bcf_op, bct_op, bcfl_op, bctl_op }; /* * func field of cop0 coi opcodes. */ enum cop0_coi_func { tlbr_op = 0x01, tlbwi_op = 0x02, tlbwr_op = 0x06, tlbp_op = 0x08, rfe_op = 0x10, eret_op = 0x18, wait_op = 0x20, hypcall_op = 0x28 }; /* * func field of cop0 com opcodes. */ enum cop0_com_func { tlbr1_op = 0x01, tlbw_op = 0x02, tlbp1_op = 0x08, dctr_op = 0x09, dctw_op = 0x0a }; /* * fmt field of cop1 opcodes. */ enum cop1_fmt { s_fmt, d_fmt, e_fmt, q_fmt, w_fmt, l_fmt }; /* * func field of cop1 instructions using d, s or w format. */ enum cop1_sdw_func { fadd_op = 0x00, fsub_op = 0x01, fmul_op = 0x02, fdiv_op = 0x03, fsqrt_op = 0x04, fabs_op = 0x05, fmov_op = 0x06, fneg_op = 0x07, froundl_op = 0x08, ftruncl_op = 0x09, fceill_op = 0x0a, ffloorl_op = 0x0b, fround_op = 0x0c, ftrunc_op = 0x0d, fceil_op = 0x0e, ffloor_op = 0x0f, fsel_op = 0x10, fmovc_op = 0x11, fmovz_op = 0x12, fmovn_op = 0x13, fseleqz_op = 0x14, frecip_op = 0x15, frsqrt_op = 0x16, fselnez_op = 0x17, fmaddf_op = 0x18, fmsubf_op = 0x19, frint_op = 0x1a, fclass_op = 0x1b, fmin_op = 0x1c, fmina_op = 0x1d, fmax_op = 0x1e, fmaxa_op = 0x1f, fcvts_op = 0x20, fcvtd_op = 0x21, fcvte_op = 0x22, fcvtw_op = 0x24, fcvtl_op = 0x25, fcmp_op = 0x30 }; /* * func field of cop1x opcodes (MIPS IV). */ enum cop1x_func { lwxc1_op = 0x00, ldxc1_op = 0x01, swxc1_op = 0x08, sdxc1_op = 0x09, pfetch_op = 0x0f, madd_s_op = 0x20, madd_d_op = 0x21, madd_e_op = 0x22, msub_s_op = 0x28, msub_d_op = 0x29, msub_e_op = 0x2a, nmadd_s_op = 0x30, nmadd_d_op = 0x31, nmadd_e_op = 0x32, nmsub_s_op = 0x38, nmsub_d_op = 0x39, nmsub_e_op = 0x3a }; /* * func field for mad opcodes (MIPS IV). */ enum mad_func { madd_fp_op = 0x08, msub_fp_op = 0x0a, nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e }; /* * func field for page table walker (Loongson-3). */ enum ptw_func { lwdir_op = 0x00, lwpte_op = 0x01, lddir_op = 0x02, ldpte_op = 0x03, }; /* * func field for special3 lx opcodes (Cavium Octeon). */ enum lx_func { lwx_op = 0x00, lhx_op = 0x04, lbux_op = 0x06, ldx_op = 0x08, lwux_op = 0x10, lhux_op = 0x14, lbx_op = 0x16, }; /* * BSHFL opcodes */ enum bshfl_func { wsbh_op = 0x2, seb_op = 0x10, seh_op = 0x18, }; /* * DBSHFL opcodes */ enum dbshfl_func { dsbh_op = 0x2, dshd_op = 0x5, }; /* * MSA minor opcodes. */ enum msa_func { msa_elm_op = 0x19, }; /* * MSA ELM opcodes. */ enum msa_elm { msa_ctc_op = 0x3e, msa_cfc_op = 0x7e, }; /* * func field for MSA MI10 format. */ enum msa_mi10_func { msa_ld_op = 8, msa_st_op = 9, }; /* * MSA 2 bit format fields. */ enum msa_2b_fmt { msa_fmt_b = 0, msa_fmt_h = 1, msa_fmt_w = 2, msa_fmt_d = 3, }; /* * (microMIPS) Major opcodes. */ enum mm_major_op { mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op, mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, }; /* * (microMIPS) POOL32I minor opcodes. */ enum mm_32i_minor_op { mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, }; /* * (microMIPS) POOL32A minor opcodes. */ enum mm_32a_minor_op { mm_sll32_op = 0x000, mm_ins_op = 0x00c, mm_sllv32_op = 0x010, mm_ext_op = 0x02c, mm_pool32axf_op = 0x03c, mm_srl32_op = 0x040, mm_srlv32_op = 0x050, mm_sra_op = 0x080, mm_srav_op = 0x090, mm_rotr_op = 0x0c0, mm_lwxs_op = 0x118, mm_addu32_op = 0x150, mm_subu32_op = 0x1d0, mm_wsbh_op = 0x1ec, mm_mul_op = 0x210, mm_and_op = 0x250, mm_or32_op = 0x290, mm_xor32_op = 0x310, mm_slt_op = 0x350, mm_sltu_op = 0x390, }; /* * (microMIPS) POOL32B functions. */ enum mm_32b_func { mm_lwc2_func = 0x0, mm_lwp_func = 0x1, mm_ldc2_func = 0x2, mm_ldp_func = 0x4, mm_lwm32_func = 0x5, mm_cache_func = 0x6, mm_ldm_func = 0x7, mm_swc2_func = 0x8, mm_swp_func = 0x9, mm_sdc2_func = 0xa, mm_sdp_func = 0xc, mm_swm32_func = 0xd, mm_sdm_func = 0xf, }; /* * (microMIPS) POOL32C functions. */ enum mm_32c_func { mm_pref_func = 0x2, mm_ll_func = 0x3, mm_swr_func = 0x9, mm_sc_func = 0xb, mm_lwu_func = 0xe, }; /* * (microMIPS) POOL32AXF minor opcodes. */ enum mm_32axf_minor_op { mm_mfc0_op = 0x003, mm_mtc0_op = 0x00b, mm_tlbp_op = 0x00d, mm_mfhi32_op = 0x035, mm_jalr_op = 0x03c, mm_tlbr_op = 0x04d, mm_mflo32_op = 0x075, mm_jalrhb_op = 0x07c, mm_tlbwi_op = 0x08d, mm_mthi32_op = 0x0b5, mm_tlbwr_op = 0x0cd, mm_mtlo32_op = 0x0f5, mm_di_op = 0x11d, mm_jalrs_op = 0x13c, mm_jalrshb_op = 0x17c, mm_sync_op = 0x1ad, mm_syscall_op = 0x22d, mm_wait_op = 0x24d, mm_eret_op = 0x3cd, mm_divu_op = 0x5dc, }; /* * (microMIPS) POOL32F minor opcodes. */ enum mm_32f_minor_op { mm_32f_00_op = 0x00, mm_32f_01_op = 0x01, mm_32f_02_op = 0x02, mm_32f_10_op = 0x08, mm_32f_11_op = 0x09, mm_32f_12_op = 0x0a, mm_32f_20_op = 0x10, mm_32f_30_op = 0x18, mm_32f_40_op = 0x20, mm_32f_41_op = 0x21, mm_32f_42_op = 0x22, mm_32f_50_op = 0x28, mm_32f_51_op = 0x29, mm_32f_52_op = 0x2a, mm_32f_60_op = 0x30, mm_32f_70_op = 0x38, mm_32f_73_op = 0x3b, mm_32f_74_op = 0x3c, }; /* * (microMIPS) POOL32F secondary minor opcodes. */ enum mm_32f_10_minor_op { mm_lwxc1_op = 0x1, mm_swxc1_op, mm_ldxc1_op, mm_sdxc1_op, mm_luxc1_op, mm_suxc1_op, }; enum mm_32f_func { mm_lwxc1_func = 0x048, mm_swxc1_func = 0x088, mm_ldxc1_func = 0x0c8, mm_sdxc1_func = 0x108, }; /* * (microMIPS) POOL32F secondary minor opcodes. */ enum mm_32f_40_minor_op { mm_fmovf_op, mm_fmovt_op, }; /* * (microMIPS) POOL32F secondary minor opcodes. */ enum mm_32f_60_minor_op { mm_fadd_op, mm_fsub_op, mm_fmul_op, mm_fdiv_op, }; /* * (microMIPS) POOL32F secondary minor opcodes. */ enum mm_32f_70_minor_op { mm_fmovn_op, mm_fmovz_op, }; /* * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. */ enum mm_32f_73_minor_op { mm_fmov0_op = 0x01, mm_fcvtl_op = 0x04, mm_movf0_op = 0x05, mm_frsqrt_op = 0x08, mm_ffloorl_op = 0x0c, mm_fabs0_op = 0x0d, mm_fcvtw_op = 0x24, mm_movt0_op = 0x25, mm_fsqrt_op = 0x28, mm_ffloorw_op = 0x2c, mm_fneg0_op = 0x2d, mm_cfc1_op = 0x40, mm_frecip_op = 0x48, mm_fceill_op = 0x4c, mm_fcvtd0_op = 0x4d, mm_ctc1_op = 0x60, mm_fceilw_op = 0x6c, mm_fcvts0_op = 0x6d, mm_mfc1_op = 0x80, mm_fmov1_op = 0x81, mm_movf1_op = 0x85, mm_ftruncl_op = 0x8c, mm_fabs1_op = 0x8d, mm_mtc1_op = 0xa0, mm_movt1_op = 0xa5, mm_ftruncw_op = 0xac, mm_fneg1_op = 0xad, mm_mfhc1_op = 0xc0, mm_froundl_op = 0xcc, mm_fcvtd1_op = 0xcd, mm_mthc1_op = 0xe0, mm_froundw_op = 0xec, mm_fcvts1_op = 0xed, }; /* * (microMIPS) POOL32S minor opcodes. */ enum mm_32s_minor_op { mm_32s_elm_op = 0x16, }; /* * (microMIPS) POOL16C minor opcodes. */ enum mm_16c_minor_op { mm_lwm16_op = 0x04, mm_swm16_op = 0x05, mm_jr16_op = 0x0c, mm_jrc_op = 0x0d, mm_jalr16_op = 0x0e, mm_jalrs16_op = 0x0f, mm_jraddiusp_op = 0x18, }; /* * (microMIPS) POOL16D minor opcodes. */ enum mm_16d_minor_op { mm_addius5_func, mm_addiusp_func, }; /* * (MIPS16e) opcodes. */ enum MIPS16e_ops { MIPS16e_jal_op = 003, MIPS16e_ld_op = 007, MIPS16e_i8_op = 014, MIPS16e_sd_op = 017, MIPS16e_lb_op = 020, MIPS16e_lh_op = 021, MIPS16e_lwsp_op = 022, MIPS16e_lw_op = 023, MIPS16e_lbu_op = 024, MIPS16e_lhu_op = 025, MIPS16e_lwpc_op = 026, MIPS16e_lwu_op = 027, MIPS16e_sb_op = 030, MIPS16e_sh_op = 031, MIPS16e_swsp_op = 032, MIPS16e_sw_op = 033, MIPS16e_rr_op = 035, MIPS16e_extend_op = 036, MIPS16e_i64_op = 037, }; enum MIPS16e_i64_func { MIPS16e_ldsp_func, MIPS16e_sdsp_func, MIPS16e_sdrasp_func, MIPS16e_dadjsp_func, MIPS16e_ldpc_func, }; enum MIPS16e_rr_func { MIPS16e_jr_func, }; enum MIPS6e_i8_func { MIPS16e_swrasp_func = 02, }; /* * (microMIPS) NOP instruction. */ #define MM_NOP16 0x0c00 struct j_format { __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ __BITFIELD_FIELD(unsigned int target : 26, ;)) }; struct i_format { /* signed immediate format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(signed int simmediate : 16, ;)))) }; struct u_format { /* unsigned immediate format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int uimmediate : 16, ;)))) }; struct c_format { /* Cache (>= R6000) format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int c_op : 3, __BITFIELD_FIELD(unsigned int cache : 2, __BITFIELD_FIELD(unsigned int simmediate : 16, ;))))) }; struct r_format { /* Register format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int re : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct c0r_format { /* C0 register format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int z: 8, __BITFIELD_FIELD(unsigned int sel : 3, ;)))))) }; struct mfmc0_format { /* MFMC0 register format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int re : 5, __BITFIELD_FIELD(unsigned int sc : 1, __BITFIELD_FIELD(unsigned int : 2, __BITFIELD_FIELD(unsigned int sel : 3, ;)))))))) }; struct co_format { /* C0 CO format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int co : 1, __BITFIELD_FIELD(unsigned int code : 19, __BITFIELD_FIELD(unsigned int func : 6, ;)))) }; struct p_format { /* Performance counter format (R10000) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int re : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct f_format { /* FPU register format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int : 1, __BITFIELD_FIELD(unsigned int fmt : 4, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int re : 5, __BITFIELD_FIELD(unsigned int func : 6, ;))))))) }; struct ma_format { /* FPU multiply and add format (MIPS IV) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int fr : 5, __BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int func : 4, __BITFIELD_FIELD(unsigned int fmt : 2, ;))))))) }; struct b_format { /* BREAK and SYSCALL */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int code : 20, __BITFIELD_FIELD(unsigned int func : 6, ;))) }; struct ps_format { /* MIPS-3D / paired single format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct v_format { /* MDMX vector format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int sel : 4, __BITFIELD_FIELD(unsigned int fmt : 1, __BITFIELD_FIELD(unsigned int vt : 5, __BITFIELD_FIELD(unsigned int vs : 5, __BITFIELD_FIELD(unsigned int vd : 5, __BITFIELD_FIELD(unsigned int func : 6, ;))))))) }; struct msa_mi10_format { /* MSA MI10 */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(signed int s10 : 10, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int wd : 5, __BITFIELD_FIELD(unsigned int func : 4, __BITFIELD_FIELD(unsigned int df : 2, ;)))))) }; struct dsp_format { /* SPEC3 DSP format instructions */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int index : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int op : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct spec3_format { /* SPEC3 */ __BITFIELD_FIELD(unsigned int opcode:6, __BITFIELD_FIELD(unsigned int rs:5, __BITFIELD_FIELD(unsigned int rt:5, __BITFIELD_FIELD(signed int simmediate:9, __BITFIELD_FIELD(unsigned int func:7, ;))))) }; /* * microMIPS instruction formats (32-bit length) * * NOTE: * Parenthesis denote whether the format is a microMIPS instruction or * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. */ struct fb_format { /* FPU branch format (MIPS32) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int bc : 5, __BITFIELD_FIELD(unsigned int cc : 3, __BITFIELD_FIELD(unsigned int flag : 2, __BITFIELD_FIELD(signed int simmediate : 16, ;))))) }; struct fp0_format { /* FPU multiply and add format (MIPS32) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int fmt : 5, __BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct mm_fp0_format { /* FPU multiply and add format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fmt : 3, __BITFIELD_FIELD(unsigned int op : 2, __BITFIELD_FIELD(unsigned int func : 6, ;))))))) }; struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int op : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fmt : 2, __BITFIELD_FIELD(unsigned int op : 8, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int cc : 3, __BITFIELD_FIELD(unsigned int zero : 2, __BITFIELD_FIELD(unsigned int fmt : 2, __BITFIELD_FIELD(unsigned int op : 3, __BITFIELD_FIELD(unsigned int func : 6, ;)))))))) }; struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fmt : 3, __BITFIELD_FIELD(unsigned int op : 7, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int cc : 3, __BITFIELD_FIELD(unsigned int fmt : 3, __BITFIELD_FIELD(unsigned int cond : 4, __BITFIELD_FIELD(unsigned int func : 6, ;))))))) }; struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int index : 5, __BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int op : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct fp6_format { /* FPU madd and msub format (MIPS IV) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int fr : 5, __BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int ft : 5, __BITFIELD_FIELD(unsigned int fs : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int fr : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; struct mm_i_format { /* Immediate format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(signed int simmediate : 16, ;)))) }; struct mm_m_format { /* Multi-word load/store format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int func : 4, __BITFIELD_FIELD(signed int simmediate : 12, ;))))) }; struct mm_x_format { /* Scaled indexed load format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int index : 5, __BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int func : 11, ;))))) }; struct mm_a_format { /* ADDIUPC format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 3, __BITFIELD_FIELD(signed int simmediate : 23, ;))) }; /* * microMIPS instruction formats (16-bit length) */ struct mm_b0_format { /* Unconditional branch format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(signed int simmediate : 10, __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ ;))) }; struct mm_b1_format { /* Conditional branch format (microMIPS) */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 3, __BITFIELD_FIELD(signed int simmediate : 7, __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ ;)))) }; struct mm16_m_format { /* Multi-word load/store format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int func : 4, __BITFIELD_FIELD(unsigned int rlist : 2, __BITFIELD_FIELD(unsigned int imm : 4, __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ ;))))) }; struct mm16_rb_format { /* Signed immediate format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rt : 3, __BITFIELD_FIELD(unsigned int base : 3, __BITFIELD_FIELD(signed int simmediate : 4, __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ ;))))) }; struct mm16_r3_format { /* Load from global pointer format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rt : 3, __BITFIELD_FIELD(signed int simmediate : 7, __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ ;)))) }; struct mm16_r5_format { /* Load/store from stack pointer format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int imm : 5, __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ ;)))) }; /* * Loongson-3 overridden COP2 instruction formats (32-bit length) */ struct loongson3_lswc2_format { /* Loongson-3 overridden lwc2/swc2 Load/Store format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int fr : 1, __BITFIELD_FIELD(unsigned int offset : 9, __BITFIELD_FIELD(unsigned int ls : 1, __BITFIELD_FIELD(unsigned int rq : 5, ;))))))) }; struct loongson3_lsdc2_format { /* Loongson-3 overridden ldc2/sdc2 Load/Store format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int base : 5, __BITFIELD_FIELD(unsigned int rt : 5, __BITFIELD_FIELD(unsigned int index : 5, __BITFIELD_FIELD(unsigned int offset : 8, __BITFIELD_FIELD(unsigned int opcode1 : 3, ;)))))) }; struct loongson3_lscsr_format { /* Loongson-3 CPUCFG&CSR read/write format */ __BITFIELD_FIELD(unsigned int opcode : 6, __BITFIELD_FIELD(unsigned int rs : 5, __BITFIELD_FIELD(unsigned int fr : 5, __BITFIELD_FIELD(unsigned int rd : 5, __BITFIELD_FIELD(unsigned int fd : 5, __BITFIELD_FIELD(unsigned int func : 6, ;)))))) }; /* * MIPS16e instruction formats (16-bit length) */ struct m16e_rr { __BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int rx : 3, __BITFIELD_FIELD(unsigned int nd : 1, __BITFIELD_FIELD(unsigned int l : 1, __BITFIELD_FIELD(unsigned int ra : 1, __BITFIELD_FIELD(unsigned int func : 5, ;)))))) }; struct m16e_jal { __BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int x : 1, __BITFIELD_FIELD(unsigned int imm20_16 : 5, __BITFIELD_FIELD(signed int imm25_21 : 5, ;)))) }; struct m16e_i64 { __BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int func : 3, __BITFIELD_FIELD(unsigned int imm : 8, ;))) }; struct m16e_ri64 { __BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int func : 3, __BITFIELD_FIELD(unsigned int ry : 3, __BITFIELD_FIELD(unsigned int imm : 5, ;)))) }; struct m16e_ri { __BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int rx : 3, __BITFIELD_FIELD(unsigned int imm : 8, ;))) }; struct m16e_rri { __BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int rx : 3, __BITFIELD_FIELD(unsigned int ry : 3, __BITFIELD_FIELD(unsigned int imm : 5, ;)))) }; struct m16e_i8 { __BITFIELD_FIELD(unsigned int opcode : 5, __BITFIELD_FIELD(unsigned int func : 3, __BITFIELD_FIELD(unsigned int imm : 8, ;))) }; union mips_instruction { unsigned int word; unsigned short halfword[2]; unsigned char byte[4]; struct j_format j_format; struct i_format i_format; struct u_format u_format; struct c_format c_format; struct r_format r_format; struct c0r_format c0r_format; struct mfmc0_format mfmc0_format; struct co_format co_format; struct p_format p_format; struct f_format f_format; struct ma_format ma_format; struct msa_mi10_format msa_mi10_format; struct b_format b_format; struct ps_format ps_format; struct v_format v_format; struct dsp_format dsp_format; struct spec3_format spec3_format; struct fb_format fb_format; struct fp0_format fp0_format; struct mm_fp0_format mm_fp0_format; struct fp1_format fp1_format; struct mm_fp1_format mm_fp1_format; struct mm_fp2_format mm_fp2_format; struct mm_fp3_format mm_fp3_format; struct mm_fp4_format mm_fp4_format; struct mm_fp5_format mm_fp5_format; struct fp6_format fp6_format; struct mm_fp6_format mm_fp6_format; struct mm_i_format mm_i_format; struct mm_m_format mm_m_format; struct mm_x_format mm_x_format; struct mm_a_format mm_a_format; struct mm_b0_format mm_b0_format; struct mm_b1_format mm_b1_format; struct mm16_m_format mm16_m_format ; struct mm16_rb_format mm16_rb_format; struct mm16_r3_format mm16_r3_format; struct mm16_r5_format mm16_r5_format; struct loongson3_lswc2_format loongson3_lswc2_format; struct loongson3_lsdc2_format loongson3_lsdc2_format; struct loongson3_lscsr_format loongson3_lscsr_format; }; union mips16e_instruction { unsigned int full : 16; struct m16e_rr rr; struct m16e_jal jal; struct m16e_i64 i64; struct m16e_ri64 ri64; struct m16e_ri ri; struct m16e_rri rri; struct m16e_i8 i8; }; #endif /* _UAPI_ASM_INST_H */ PK ! ��5+� � bitfield.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2014 by Ralf Baechle <ralf@linux-mips.org> */ #ifndef __UAPI_ASM_BITFIELD_H #define __UAPI_ASM_BITFIELD_H /* * * Damn ... bitfields depend from byteorder :-( * */ #ifdef __MIPSEB__ #define __BITFIELD_FIELD(field, more) \ field; \ more #elif defined(__MIPSEL__) #define __BITFIELD_FIELD(field, more) \ more \ field; #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" #endif #endif /* __UAPI_ASM_BITFIELD_H */ PK ! �t�� � errno.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle */ #ifndef _UAPI_ASM_ERRNO_H #define _UAPI_ASM_ERRNO_H /* * These error numbers are intended to be MIPS ABI compatible */ #include <asm-generic/errno-base.h> #define ENOMSG 35 /* No message of desired type */ #define EIDRM 36 /* Identifier removed */ #define ECHRNG 37 /* Channel number out of range */ #define EL2NSYNC 38 /* Level 2 not synchronized */ #define EL3HLT 39 /* Level 3 halted */ #define EL3RST 40 /* Level 3 reset */ #define ELNRNG 41 /* Link number out of range */ #define EUNATCH 42 /* Protocol driver not attached */ #define ENOCSI 43 /* No CSI structure available */ #define EL2HLT 44 /* Level 2 halted */ #define EDEADLK 45 /* Resource deadlock would occur */ #define ENOLCK 46 /* No record locks available */ #define EBADE 50 /* Invalid exchange */ #define EBADR 51 /* Invalid request descriptor */ #define EXFULL 52 /* Exchange full */ #define ENOANO 53 /* No anode */ #define EBADRQC 54 /* Invalid request code */ #define EBADSLT 55 /* Invalid slot */ #define EDEADLOCK 56 /* File locking deadlock error */ #define EBFONT 59 /* Bad font file format */ #define ENOSTR 60 /* Device not a stream */ #define ENODATA 61 /* No data available */ #define ETIME 62 /* Timer expired */ #define ENOSR 63 /* Out of streams resources */ #define ENONET 64 /* Machine is not on the network */ #define ENOPKG 65 /* Package not installed */ #define EREMOTE 66 /* Object is remote */ #define ENOLINK 67 /* Link has been severed */ #define EADV 68 /* Advertise error */ #define ESRMNT 69 /* Srmount error */ #define ECOMM 70 /* Communication error on send */ #define EPROTO 71 /* Protocol error */ #define EDOTDOT 73 /* RFS specific error */ #define EMULTIHOP 74 /* Multihop attempted */ #define EBADMSG 77 /* Not a data message */ #define ENAMETOOLONG 78 /* File name too long */ #define EOVERFLOW 79 /* Value too large for defined data type */ #define ENOTUNIQ 80 /* Name not unique on network */ #define EBADFD 81 /* File descriptor in bad state */ #define EREMCHG 82 /* Remote address changed */ #define ELIBACC 83 /* Can not access a needed shared library */ #define ELIBBAD 84 /* Accessing a corrupted shared library */ #define ELIBSCN 85 /* .lib section in a.out corrupted */ #define ELIBMAX 86 /* Attempting to link in too many shared libraries */ #define ELIBEXEC 87 /* Cannot exec a shared library directly */ #define EILSEQ 88 /* Illegal byte sequence */ #define ENOSYS 89 /* Function not implemented */ #define ELOOP 90 /* Too many symbolic links encountered */ #define ERESTART 91 /* Interrupted system call should be restarted */ #define ESTRPIPE 92 /* Streams pipe error */ #define ENOTEMPTY 93 /* Directory not empty */ #define EUSERS 94 /* Too many users */ #define ENOTSOCK 95 /* Socket operation on non-socket */ #define EDESTADDRREQ 96 /* Destination address required */ #define EMSGSIZE 97 /* Message too long */ #define EPROTOTYPE 98 /* Protocol wrong type for socket */ #define ENOPROTOOPT 99 /* Protocol not available */ #define EPROTONOSUPPORT 120 /* Protocol not supported */ #define ESOCKTNOSUPPORT 121 /* Socket type not supported */ #define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ #define EPFNOSUPPORT 123 /* Protocol family not supported */ #define EAFNOSUPPORT 124 /* Address family not supported by protocol */ #define EADDRINUSE 125 /* Address already in use */ #define EADDRNOTAVAIL 126 /* Cannot assign requested address */ #define ENETDOWN 127 /* Network is down */ #define ENETUNREACH 128 /* Network is unreachable */ #define ENETRESET 129 /* Network dropped connection because of reset */ #define ECONNABORTED 130 /* Software caused connection abort */ #define ECONNRESET 131 /* Connection reset by peer */ #define ENOBUFS 132 /* No buffer space available */ #define EISCONN 133 /* Transport endpoint is already connected */ #define ENOTCONN 134 /* Transport endpoint is not connected */ #define EUCLEAN 135 /* Structure needs cleaning */ #define ENOTNAM 137 /* Not a XENIX named type file */ #define ENAVAIL 138 /* No XENIX semaphores available */ #define EISNAM 139 /* Is a named type file */ #define EREMOTEIO 140 /* Remote I/O error */ #define EINIT 141 /* Reserved */ #define EREMDEV 142 /* Error 142 */ #define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ #define ETOOMANYREFS 144 /* Too many references: cannot splice */ #define ETIMEDOUT 145 /* Connection timed out */ #define ECONNREFUSED 146 /* Connection refused */ #define EHOSTDOWN 147 /* Host is down */ #define EHOSTUNREACH 148 /* No route to host */ #define EWOULDBLOCK EAGAIN /* Operation would block */ #define EALREADY 149 /* Operation already in progress */ #define EINPROGRESS 150 /* Operation now in progress */ #define ESTALE 151 /* Stale file handle */ #define ECANCELED 158 /* AIO operation canceled */ /* * These error are Linux extensions. */ #define ENOMEDIUM 159 /* No medium found */ #define EMEDIUMTYPE 160 /* Wrong medium type */ #define ENOKEY 161 /* Required key not available */ #define EKEYEXPIRED 162 /* Key has expired */ #define EKEYREVOKED 163 /* Key has been revoked */ #define EKEYREJECTED 164 /* Key was rejected by service */ /* for robust mutexes */ #define EOWNERDEAD 165 /* Owner died */ #define ENOTRECOVERABLE 166 /* State not recoverable */ #define ERFKILL 167 /* Operation not possible due to RF-kill */ #define EHWPOISON 168 /* Memory page has hardware error */ #define EDQUOT 1133 /* Quota exceeded */ #endif /* _UAPI_ASM_ERRNO_H */ PK ! �@c6 6 socket.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_SOCKET_H #define _ASM_SOCKET_H #include <uapi/asm/socket.h> /* O_NONBLOCK clashes with the bits used for socket types. Therefore we * have to define SOCK_NONBLOCK to a different value here. */ #define SOCK_NONBLOCK 0x40000000 #endif /* _ASM_SOCKET_H */ PK ! ���[I I sysmips.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Definitions for the MIPS sysmips(2) call * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995 by Ralf Baechle */ #ifndef _ASM_SYSMIPS_H #define _ASM_SYSMIPS_H /* * Commands for the sysmips(2) call * * sysmips(2) is deprecated - though some existing software uses it. * We only support the following commands. */ #define SETNAME 1 /* set hostname */ #define FLUSH_CACHE 3 /* writeback and invalidate caches */ #define MIPS_FIXADE 7 /* control address error fixing */ #define MIPS_RDNVRAM 10 /* read NVRAM */ #define MIPS_ATOMIC_SET 2001 /* atomically set variable */ #endif /* _ASM_SYSMIPS_H */ PK ! ���- sgidefs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996, 1999, 2001 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. */ #ifndef __ASM_SGIDEFS_H #define __ASM_SGIDEFS_H /* * Definitions for the ISA levels * * With the introduction of MIPS32 / MIPS64 instruction sets definitions * MIPS ISAs are no longer subsets of each other. Therefore comparisons * on these symbols except with == may result in unexpected results and * are forbidden! */ #define _MIPS_ISA_MIPS1 1 #define _MIPS_ISA_MIPS2 2 #define _MIPS_ISA_MIPS3 3 #define _MIPS_ISA_MIPS4 4 #define _MIPS_ISA_MIPS5 5 #define _MIPS_ISA_MIPS32 6 #define _MIPS_ISA_MIPS64 7 /* * Subprogram calling convention */ #define _MIPS_SIM_ABI32 1 #define _MIPS_SIM_NABI32 2 #define _MIPS_SIM_ABI64 3 #endif /* __ASM_SGIDEFS_H */ PK ! Ʈ]� ioctl.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org> * Copyright (C) 2009 Wind River Systems * Written by Ralf Baechle <ralf@linux-mips.org> */ #ifndef __ASM_IOCTL_H #define __ASM_IOCTL_H #define _IOC_SIZEBITS 13 #define _IOC_DIRBITS 3 /* * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. * And this turns out useful to catch old ioctl numbers in header * files for us. */ #define _IOC_NONE 1U #define _IOC_READ 2U #define _IOC_WRITE 4U #include <asm-generic/ioctl.h> #endif /* __ASM_IOCTL_H */ PK ! ���� � .syscalls_32.h.cmdnu �[��� cmd_arch/x86/include/generated/asm/syscalls_32.h := sh /build/linux-6CgZId/linux-5.15.0/scripts/syscalltbl.sh --abis i386 /build/linux-6CgZId/linux-5.15.0/arch/x86/entry/syscalls/syscall_32.tbl arch/x86/include/generated/asm/syscalls_32.h PK ! vS� unistd_64_x32.hnu �[��� #ifndef _UAPI_ASM_UNISTD_64_X32_H #define _UAPI_ASM_UNISTD_64_X32_H #define __NR_x32_rt_sigaction 512 #define __NR_x32_rt_sigreturn 513 #define __NR_x32_ioctl 514 #define __NR_x32_readv 515 #define __NR_x32_writev 516 #define __NR_x32_recvfrom 517 #define __NR_x32_sendmsg 518 #define __NR_x32_recvmsg 519 #define __NR_x32_execve 520 #define __NR_x32_ptrace 521 #define __NR_x32_rt_sigpending 522 #define __NR_x32_rt_sigtimedwait 523 #define __NR_x32_rt_sigqueueinfo 524 #define __NR_x32_sigaltstack 525 #define __NR_x32_timer_create 526 #define __NR_x32_mq_notify 527 #define __NR_x32_kexec_load 528 #define __NR_x32_waitid 529 #define __NR_x32_set_robust_list 530 #define __NR_x32_get_robust_list 531 #define __NR_x32_vmsplice 532 #define __NR_x32_move_pages 533 #define __NR_x32_preadv 534 #define __NR_x32_pwritev 535 #define __NR_x32_rt_tgsigqueueinfo 536 #define __NR_x32_recvmmsg 537 #define __NR_x32_sendmmsg 538 #define __NR_x32_process_vm_readv 539 #define __NR_x32_process_vm_writev 540 #define __NR_x32_setsockopt 541 #define __NR_x32_getsockopt 542 #define __NR_x32_io_setup 543 #define __NR_x32_io_submit 544 #define __NR_x32_execveat 545 #define __NR_x32_preadv2 546 #define __NR_x32_pwritev2 547 #ifdef __KERNEL__ #define __NR_x32_syscalls 548 #endif #endif /* _UAPI_ASM_UNISTD_64_X32_H */ PK ! �[, , rwonce.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019 Google LLC. */ #ifndef __ASM_RWONCE_H #define __ASM_RWONCE_H #ifdef CONFIG_SMP #include <asm/barrier.h> /* * Alpha is apparently daft enough to reorder address-dependent loads * on some CPU implementations. Knock some common sense into it with * a memory barrier in READ_ONCE(). * * For the curious, more information about this unusual reordering is * available in chapter 15 of the "perfbook": * * https://kernel.org/pub/linux/kernel/people/paulmck/perfbook/perfbook.html * */ #define __READ_ONCE(x) \ ({ \ __unqual_scalar_typeof(x) __x = \ (*(volatile typeof(__x) *)(&(x))); \ mb(); \ (typeof(x))__x; \ }) #endif /* CONFIG_SMP */ #include <asm-generic/rwonce.h> #endif /* __ASM_RWONCE_H */ PK ! 1���4 �4 syscalls_64.hnu �[��� __SYSCALL(0, sys_read) __SYSCALL(1, sys_write) __SYSCALL(2, sys_open) __SYSCALL(3, sys_close) __SYSCALL(4, sys_newstat) __SYSCALL(5, sys_newfstat) __SYSCALL(6, sys_newlstat) __SYSCALL(7, sys_poll) __SYSCALL(8, sys_lseek) __SYSCALL(9, sys_mmap) __SYSCALL(10, sys_mprotect) __SYSCALL(11, sys_munmap) __SYSCALL(12, sys_brk) __SYSCALL(13, sys_rt_sigaction) __SYSCALL(14, sys_rt_sigprocmask) __SYSCALL(15, sys_rt_sigreturn) __SYSCALL(16, sys_ioctl) __SYSCALL(17, sys_pread64) __SYSCALL(18, sys_pwrite64) __SYSCALL(19, sys_readv) __SYSCALL(20, sys_writev) __SYSCALL(21, sys_access) __SYSCALL(22, sys_pipe) __SYSCALL(23, sys_select) __SYSCALL(24, sys_sched_yield) __SYSCALL(25, sys_mremap) __SYSCALL(26, sys_msync) __SYSCALL(27, sys_mincore) __SYSCALL(28, sys_madvise) __SYSCALL(29, sys_shmget) __SYSCALL(30, sys_shmat) __SYSCALL(31, sys_shmctl) __SYSCALL(32, sys_dup) __SYSCALL(33, sys_dup2) __SYSCALL(34, sys_pause) __SYSCALL(35, sys_nanosleep) __SYSCALL(36, sys_getitimer) __SYSCALL(37, sys_alarm) __SYSCALL(38, sys_setitimer) __SYSCALL(39, sys_getpid) __SYSCALL(40, sys_sendfile64) __SYSCALL(41, sys_socket) __SYSCALL(42, sys_connect) __SYSCALL(43, sys_accept) __SYSCALL(44, sys_sendto) __SYSCALL(45, sys_recvfrom) __SYSCALL(46, sys_sendmsg) __SYSCALL(47, sys_recvmsg) __SYSCALL(48, sys_shutdown) __SYSCALL(49, sys_bind) __SYSCALL(50, sys_listen) __SYSCALL(51, sys_getsockname) __SYSCALL(52, sys_getpeername) __SYSCALL(53, sys_socketpair) __SYSCALL(54, sys_setsockopt) __SYSCALL(55, sys_getsockopt) __SYSCALL(56, sys_clone) __SYSCALL(57, sys_fork) __SYSCALL(58, sys_vfork) __SYSCALL(59, sys_execve) __SYSCALL(60, sys_exit) __SYSCALL(61, sys_wait4) __SYSCALL(62, sys_kill) __SYSCALL(63, sys_newuname) __SYSCALL(64, sys_semget) __SYSCALL(65, sys_semop) __SYSCALL(66, sys_semctl) __SYSCALL(67, sys_shmdt) __SYSCALL(68, sys_msgget) __SYSCALL(69, sys_msgsnd) __SYSCALL(70, sys_msgrcv) __SYSCALL(71, sys_msgctl) __SYSCALL(72, sys_fcntl) __SYSCALL(73, sys_flock) __SYSCALL(74, sys_fsync) __SYSCALL(75, sys_fdatasync) __SYSCALL(76, sys_truncate) __SYSCALL(77, sys_ftruncate) __SYSCALL(78, sys_getdents) __SYSCALL(79, sys_getcwd) __SYSCALL(80, sys_chdir) __SYSCALL(81, sys_fchdir) __SYSCALL(82, sys_rename) __SYSCALL(83, sys_mkdir) __SYSCALL(84, sys_rmdir) __SYSCALL(85, sys_creat) __SYSCALL(86, sys_link) __SYSCALL(87, sys_unlink) __SYSCALL(88, sys_symlink) __SYSCALL(89, sys_readlink) __SYSCALL(90, sys_chmod) __SYSCALL(91, sys_fchmod) __SYSCALL(92, sys_chown) __SYSCALL(93, sys_fchown) __SYSCALL(94, sys_lchown) __SYSCALL(95, sys_umask) __SYSCALL(96, sys_gettimeofday) __SYSCALL(97, sys_getrlimit) __SYSCALL(98, sys_getrusage) __SYSCALL(99, sys_sysinfo) __SYSCALL(100, sys_times) __SYSCALL(101, sys_ptrace) __SYSCALL(102, sys_getuid) __SYSCALL(103, sys_syslog) __SYSCALL(104, sys_getgid) __SYSCALL(105, sys_setuid) __SYSCALL(106, sys_setgid) __SYSCALL(107, sys_geteuid) __SYSCALL(108, sys_getegid) __SYSCALL(109, sys_setpgid) __SYSCALL(110, sys_getppid) __SYSCALL(111, sys_getpgrp) __SYSCALL(112, sys_setsid) __SYSCALL(113, sys_setreuid) __SYSCALL(114, sys_setregid) __SYSCALL(115, sys_getgroups) __SYSCALL(116, sys_setgroups) __SYSCALL(117, sys_setresuid) __SYSCALL(118, sys_getresuid) __SYSCALL(119, sys_setresgid) __SYSCALL(120, sys_getresgid) __SYSCALL(121, sys_getpgid) __SYSCALL(122, sys_setfsuid) __SYSCALL(123, sys_setfsgid) __SYSCALL(124, sys_getsid) __SYSCALL(125, sys_capget) __SYSCALL(126, sys_capset) __SYSCALL(127, sys_rt_sigpending) __SYSCALL(128, sys_rt_sigtimedwait) __SYSCALL(129, sys_rt_sigqueueinfo) __SYSCALL(130, sys_rt_sigsuspend) __SYSCALL(131, sys_sigaltstack) __SYSCALL(132, sys_utime) __SYSCALL(133, sys_mknod) __SYSCALL(134, sys_ni_syscall) __SYSCALL(135, sys_personality) __SYSCALL(136, sys_ustat) __SYSCALL(137, sys_statfs) __SYSCALL(138, sys_fstatfs) __SYSCALL(139, sys_sysfs) __SYSCALL(140, sys_getpriority) __SYSCALL(141, sys_setpriority) __SYSCALL(142, sys_sched_setparam) __SYSCALL(143, sys_sched_getparam) __SYSCALL(144, sys_sched_setscheduler) __SYSCALL(145, sys_sched_getscheduler) __SYSCALL(146, sys_sched_get_priority_max) __SYSCALL(147, sys_sched_get_priority_min) __SYSCALL(148, sys_sched_rr_get_interval) __SYSCALL(149, sys_mlock) __SYSCALL(150, sys_munlock) __SYSCALL(151, sys_mlockall) __SYSCALL(152, sys_munlockall) __SYSCALL(153, sys_vhangup) __SYSCALL(154, sys_modify_ldt) __SYSCALL(155, sys_pivot_root) __SYSCALL(156, sys_ni_syscall) __SYSCALL(157, sys_prctl) __SYSCALL(158, sys_arch_prctl) __SYSCALL(159, sys_adjtimex) __SYSCALL(160, sys_setrlimit) __SYSCALL(161, sys_chroot) __SYSCALL(162, sys_sync) __SYSCALL(163, sys_acct) __SYSCALL(164, sys_settimeofday) __SYSCALL(165, sys_mount) __SYSCALL(166, sys_umount) __SYSCALL(167, sys_swapon) __SYSCALL(168, sys_swapoff) __SYSCALL(169, sys_reboot) __SYSCALL(170, sys_sethostname) __SYSCALL(171, sys_setdomainname) __SYSCALL(172, sys_iopl) __SYSCALL(173, sys_ioperm) __SYSCALL(174, sys_ni_syscall) __SYSCALL(175, sys_init_module) __SYSCALL(176, sys_delete_module) __SYSCALL(177, sys_ni_syscall) __SYSCALL(178, sys_ni_syscall) __SYSCALL(179, sys_quotactl) __SYSCALL(180, sys_ni_syscall) __SYSCALL(181, sys_ni_syscall) __SYSCALL(182, sys_ni_syscall) __SYSCALL(183, sys_ni_syscall) __SYSCALL(184, sys_ni_syscall) __SYSCALL(185, sys_ni_syscall) __SYSCALL(186, sys_gettid) __SYSCALL(187, sys_readahead) __SYSCALL(188, sys_setxattr) __SYSCALL(189, sys_lsetxattr) __SYSCALL(190, sys_fsetxattr) __SYSCALL(191, sys_getxattr) __SYSCALL(192, sys_lgetxattr) __SYSCALL(193, sys_fgetxattr) __SYSCALL(194, sys_listxattr) __SYSCALL(195, sys_llistxattr) __SYSCALL(196, sys_flistxattr) __SYSCALL(197, sys_removexattr) __SYSCALL(198, sys_lremovexattr) __SYSCALL(199, sys_fremovexattr) __SYSCALL(200, sys_tkill) __SYSCALL(201, sys_time) __SYSCALL(202, sys_futex) __SYSCALL(203, sys_sched_setaffinity) __SYSCALL(204, sys_sched_getaffinity) __SYSCALL(205, sys_ni_syscall) __SYSCALL(206, sys_io_setup) __SYSCALL(207, sys_io_destroy) __SYSCALL(208, sys_io_getevents) __SYSCALL(209, sys_io_submit) __SYSCALL(210, sys_io_cancel) __SYSCALL(211, sys_ni_syscall) __SYSCALL(212, sys_lookup_dcookie) __SYSCALL(213, sys_epoll_create) __SYSCALL(214, sys_ni_syscall) __SYSCALL(215, sys_ni_syscall) __SYSCALL(216, sys_remap_file_pages) __SYSCALL(217, sys_getdents64) __SYSCALL(218, sys_set_tid_address) __SYSCALL(219, sys_restart_syscall) __SYSCALL(220, sys_semtimedop) __SYSCALL(221, sys_fadvise64) __SYSCALL(222, sys_timer_create) __SYSCALL(223, sys_timer_settime) __SYSCALL(224, sys_timer_gettime) __SYSCALL(225, sys_timer_getoverrun) __SYSCALL(226, sys_timer_delete) __SYSCALL(227, sys_clock_settime) __SYSCALL(228, sys_clock_gettime) __SYSCALL(229, sys_clock_getres) __SYSCALL(230, sys_clock_nanosleep) __SYSCALL(231, sys_exit_group) __SYSCALL(232, sys_epoll_wait) __SYSCALL(233, sys_epoll_ctl) __SYSCALL(234, sys_tgkill) __SYSCALL(235, sys_utimes) __SYSCALL(236, sys_ni_syscall) __SYSCALL(237, sys_mbind) __SYSCALL(238, sys_set_mempolicy) __SYSCALL(239, sys_get_mempolicy) __SYSCALL(240, sys_mq_open) __SYSCALL(241, sys_mq_unlink) __SYSCALL(242, sys_mq_timedsend) __SYSCALL(243, sys_mq_timedreceive) __SYSCALL(244, sys_mq_notify) __SYSCALL(245, sys_mq_getsetattr) __SYSCALL(246, sys_kexec_load) __SYSCALL(247, sys_waitid) __SYSCALL(248, sys_add_key) __SYSCALL(249, sys_request_key) __SYSCALL(250, sys_keyctl) __SYSCALL(251, sys_ioprio_set) __SYSCALL(252, sys_ioprio_get) __SYSCALL(253, sys_inotify_init) __SYSCALL(254, sys_inotify_add_watch) __SYSCALL(255, sys_inotify_rm_watch) __SYSCALL(256, sys_migrate_pages) __SYSCALL(257, sys_openat) __SYSCALL(258, sys_mkdirat) __SYSCALL(259, sys_mknodat) __SYSCALL(260, sys_fchownat) __SYSCALL(261, sys_futimesat) __SYSCALL(262, sys_newfstatat) __SYSCALL(263, sys_unlinkat) __SYSCALL(264, sys_renameat) __SYSCALL(265, sys_linkat) __SYSCALL(266, sys_symlinkat) __SYSCALL(267, sys_readlinkat) __SYSCALL(268, sys_fchmodat) __SYSCALL(269, sys_faccessat) __SYSCALL(270, sys_pselect6) __SYSCALL(271, sys_ppoll) __SYSCALL(272, sys_unshare) __SYSCALL(273, sys_set_robust_list) __SYSCALL(274, sys_get_robust_list) __SYSCALL(275, sys_splice) __SYSCALL(276, sys_tee) __SYSCALL(277, sys_sync_file_range) __SYSCALL(278, sys_vmsplice) __SYSCALL(279, sys_move_pages) __SYSCALL(280, sys_utimensat) __SYSCALL(281, sys_epoll_pwait) __SYSCALL(282, sys_signalfd) __SYSCALL(283, sys_timerfd_create) __SYSCALL(284, sys_eventfd) __SYSCALL(285, sys_fallocate) __SYSCALL(286, sys_timerfd_settime) __SYSCALL(287, sys_timerfd_gettime) __SYSCALL(288, sys_accept4) __SYSCALL(289, sys_signalfd4) __SYSCALL(290, sys_eventfd2) __SYSCALL(291, sys_epoll_create1) __SYSCALL(292, sys_dup3) __SYSCALL(293, sys_pipe2) __SYSCALL(294, sys_inotify_init1) __SYSCALL(295, sys_preadv) __SYSCALL(296, sys_pwritev) __SYSCALL(297, sys_rt_tgsigqueueinfo) __SYSCALL(298, sys_perf_event_open) __SYSCALL(299, sys_recvmmsg) __SYSCALL(300, sys_fanotify_init) __SYSCALL(301, sys_fanotify_mark) __SYSCALL(302, sys_prlimit64) __SYSCALL(303, sys_name_to_handle_at) __SYSCALL(304, sys_open_by_handle_at) __SYSCALL(305, sys_clock_adjtime) __SYSCALL(306, sys_syncfs) __SYSCALL(307, sys_sendmmsg) __SYSCALL(308, sys_setns) __SYSCALL(309, sys_getcpu) __SYSCALL(310, sys_process_vm_readv) __SYSCALL(311, sys_process_vm_writev) __SYSCALL(312, sys_kcmp) __SYSCALL(313, sys_finit_module) __SYSCALL(314, sys_sched_setattr) __SYSCALL(315, sys_sched_getattr) __SYSCALL(316, sys_renameat2) __SYSCALL(317, sys_seccomp) __SYSCALL(318, sys_getrandom) __SYSCALL(319, sys_memfd_create) __SYSCALL(320, sys_kexec_file_load) __SYSCALL(321, sys_bpf) __SYSCALL(322, sys_execveat) __SYSCALL(323, sys_userfaultfd) __SYSCALL(324, sys_membarrier) __SYSCALL(325, sys_mlock2) __SYSCALL(326, sys_copy_file_range) __SYSCALL(327, sys_preadv2) __SYSCALL(328, sys_pwritev2) __SYSCALL(329, sys_pkey_mprotect) __SYSCALL(330, sys_pkey_alloc) __SYSCALL(331, sys_pkey_free) __SYSCALL(332, sys_statx) __SYSCALL(333, sys_io_pgetevents) __SYSCALL(334, sys_rseq) __SYSCALL(335, sys_ni_syscall) __SYSCALL(336, sys_ni_syscall) __SYSCALL(337, sys_ni_syscall) __SYSCALL(338, sys_ni_syscall) __SYSCALL(339, sys_ni_syscall) __SYSCALL(340, sys_ni_syscall) __SYSCALL(341, sys_ni_syscall) __SYSCALL(342, sys_ni_syscall) __SYSCALL(343, sys_ni_syscall) __SYSCALL(344, sys_ni_syscall) __SYSCALL(345, sys_ni_syscall) __SYSCALL(346, sys_ni_syscall) __SYSCALL(347, sys_ni_syscall) __SYSCALL(348, sys_ni_syscall) __SYSCALL(349, sys_ni_syscall) __SYSCALL(350, sys_ni_syscall) __SYSCALL(351, sys_ni_syscall) __SYSCALL(352, sys_ni_syscall) __SYSCALL(353, sys_ni_syscall) __SYSCALL(354, sys_ni_syscall) __SYSCALL(355, sys_ni_syscall) __SYSCALL(356, sys_ni_syscall) __SYSCALL(357, sys_ni_syscall) __SYSCALL(358, sys_ni_syscall) __SYSCALL(359, sys_ni_syscall) __SYSCALL(360, sys_ni_syscall) __SYSCALL(361, sys_ni_syscall) __SYSCALL(362, sys_ni_syscall) __SYSCALL(363, sys_ni_syscall) __SYSCALL(364, sys_ni_syscall) __SYSCALL(365, sys_ni_syscall) __SYSCALL(366, sys_ni_syscall) __SYSCALL(367, sys_ni_syscall) __SYSCALL(368, sys_ni_syscall) __SYSCALL(369, sys_ni_syscall) __SYSCALL(370, sys_ni_syscall) __SYSCALL(371, sys_ni_syscall) __SYSCALL(372, sys_ni_syscall) __SYSCALL(373, sys_ni_syscall) __SYSCALL(374, sys_ni_syscall) __SYSCALL(375, sys_ni_syscall) __SYSCALL(376, sys_ni_syscall) __SYSCALL(377, sys_ni_syscall) __SYSCALL(378, sys_ni_syscall) __SYSCALL(379, sys_ni_syscall) __SYSCALL(380, sys_ni_syscall) __SYSCALL(381, sys_ni_syscall) __SYSCALL(382, sys_ni_syscall) __SYSCALL(383, sys_ni_syscall) __SYSCALL(384, sys_ni_syscall) __SYSCALL(385, sys_ni_syscall) __SYSCALL(386, sys_ni_syscall) __SYSCALL(387, sys_ni_syscall) __SYSCALL(388, sys_ni_syscall) __SYSCALL(389, sys_ni_syscall) __SYSCALL(390, sys_ni_syscall) __SYSCALL(391, sys_ni_syscall) __SYSCALL(392, sys_ni_syscall) __SYSCALL(393, sys_ni_syscall) __SYSCALL(394, sys_ni_syscall) __SYSCALL(395, sys_ni_syscall) __SYSCALL(396, sys_ni_syscall) __SYSCALL(397, sys_ni_syscall) __SYSCALL(398, sys_ni_syscall) __SYSCALL(399, sys_ni_syscall) __SYSCALL(400, sys_ni_syscall) __SYSCALL(401, sys_ni_syscall) __SYSCALL(402, sys_ni_syscall) __SYSCALL(403, sys_ni_syscall) __SYSCALL(404, sys_ni_syscall) __SYSCALL(405, sys_ni_syscall) __SYSCALL(406, sys_ni_syscall) __SYSCALL(407, sys_ni_syscall) __SYSCALL(408, sys_ni_syscall) __SYSCALL(409, sys_ni_syscall) __SYSCALL(410, sys_ni_syscall) __SYSCALL(411, sys_ni_syscall) __SYSCALL(412, sys_ni_syscall) __SYSCALL(413, sys_ni_syscall) __SYSCALL(414, sys_ni_syscall) __SYSCALL(415, sys_ni_syscall) __SYSCALL(416, sys_ni_syscall) __SYSCALL(417, sys_ni_syscall) __SYSCALL(418, sys_ni_syscall) __SYSCALL(419, sys_ni_syscall) __SYSCALL(420, sys_ni_syscall) __SYSCALL(421, sys_ni_syscall) __SYSCALL(422, sys_ni_syscall) __SYSCALL(423, sys_ni_syscall) __SYSCALL(424, sys_pidfd_send_signal) __SYSCALL(425, sys_io_uring_setup) __SYSCALL(426, sys_io_uring_enter) __SYSCALL(427, sys_io_uring_register) __SYSCALL(428, sys_open_tree) __SYSCALL(429, sys_move_mount) __SYSCALL(430, sys_fsopen) __SYSCALL(431, sys_fsconfig) __SYSCALL(432, sys_fsmount) __SYSCALL(433, sys_fspick) __SYSCALL(434, sys_pidfd_open) __SYSCALL(435, sys_clone3) __SYSCALL(436, sys_close_range) __SYSCALL(437, sys_openat2) __SYSCALL(438, sys_pidfd_getfd) __SYSCALL(439, sys_faccessat2) __SYSCALL(440, sys_process_madvise) __SYSCALL(441, sys_epoll_pwait2) __SYSCALL(442, sys_mount_setattr) __SYSCALL(443, sys_quotactl_fd) __SYSCALL(444, sys_landlock_create_ruleset) __SYSCALL(445, sys_landlock_add_rule) __SYSCALL(446, sys_landlock_restrict_self) __SYSCALL(447, sys_memfd_secret) __SYSCALL(448, sys_process_mrelease) PK ! 9��t" " irq_regs.hnu �[��� #include <asm-generic/irq_regs.h> PK ! �wD_C C syscalls_32.hnu �[��� __SYSCALL(0, sys_restart_syscall) __SYSCALL(1, sys_exit) __SYSCALL(2, sys_fork) __SYSCALL(3, sys_read) __SYSCALL(4, sys_write) __SYSCALL_WITH_COMPAT(5, sys_open, compat_sys_open) __SYSCALL(6, sys_close) __SYSCALL(7, sys_waitpid) __SYSCALL(8, sys_creat) __SYSCALL(9, sys_link) __SYSCALL(10, sys_unlink) __SYSCALL_WITH_COMPAT(11, sys_execve, compat_sys_execve) __SYSCALL(12, sys_chdir) __SYSCALL(13, sys_time32) __SYSCALL(14, sys_mknod) __SYSCALL(15, sys_chmod) __SYSCALL(16, sys_lchown16) __SYSCALL(17, sys_ni_syscall) __SYSCALL(18, sys_stat) __SYSCALL_WITH_COMPAT(19, sys_lseek, compat_sys_lseek) __SYSCALL(20, sys_getpid) __SYSCALL(21, sys_mount) __SYSCALL(22, sys_oldumount) __SYSCALL(23, sys_setuid16) __SYSCALL(24, sys_getuid16) __SYSCALL(25, sys_stime32) __SYSCALL_WITH_COMPAT(26, sys_ptrace, compat_sys_ptrace) __SYSCALL(27, sys_alarm) __SYSCALL(28, sys_fstat) __SYSCALL(29, sys_pause) __SYSCALL(30, sys_utime32) __SYSCALL(31, sys_ni_syscall) __SYSCALL(32, sys_ni_syscall) __SYSCALL(33, sys_access) __SYSCALL(34, sys_nice) __SYSCALL(35, sys_ni_syscall) __SYSCALL(36, sys_sync) __SYSCALL(37, sys_kill) __SYSCALL(38, sys_rename) __SYSCALL(39, sys_mkdir) __SYSCALL(40, sys_rmdir) __SYSCALL(41, sys_dup) __SYSCALL(42, sys_pipe) __SYSCALL_WITH_COMPAT(43, sys_times, compat_sys_times) __SYSCALL(44, sys_ni_syscall) __SYSCALL(45, sys_brk) __SYSCALL(46, sys_setgid16) __SYSCALL(47, sys_getgid16) __SYSCALL(48, sys_signal) __SYSCALL(49, sys_geteuid16) __SYSCALL(50, sys_getegid16) __SYSCALL(51, sys_acct) __SYSCALL(52, sys_umount) __SYSCALL(53, sys_ni_syscall) __SYSCALL_WITH_COMPAT(54, sys_ioctl, compat_sys_ioctl) __SYSCALL_WITH_COMPAT(55, sys_fcntl, compat_sys_fcntl64) __SYSCALL(56, sys_ni_syscall) __SYSCALL(57, sys_setpgid) __SYSCALL(58, sys_ni_syscall) __SYSCALL(59, sys_olduname) __SYSCALL(60, sys_umask) __SYSCALL(61, sys_chroot) __SYSCALL_WITH_COMPAT(62, sys_ustat, compat_sys_ustat) __SYSCALL(63, sys_dup2) __SYSCALL(64, sys_getppid) __SYSCALL(65, sys_getpgrp) __SYSCALL(66, sys_setsid) __SYSCALL_WITH_COMPAT(67, sys_sigaction, compat_sys_sigaction) __SYSCALL(68, sys_sgetmask) __SYSCALL(69, sys_ssetmask) __SYSCALL(70, sys_setreuid16) __SYSCALL(71, sys_setregid16) __SYSCALL(72, sys_sigsuspend) __SYSCALL_WITH_COMPAT(73, sys_sigpending, compat_sys_sigpending) __SYSCALL(74, sys_sethostname) __SYSCALL_WITH_COMPAT(75, sys_setrlimit, compat_sys_setrlimit) __SYSCALL_WITH_COMPAT(76, sys_old_getrlimit, compat_sys_old_getrlimit) __SYSCALL_WITH_COMPAT(77, sys_getrusage, compat_sys_getrusage) __SYSCALL_WITH_COMPAT(78, sys_gettimeofday, compat_sys_gettimeofday) __SYSCALL_WITH_COMPAT(79, sys_settimeofday, compat_sys_settimeofday) __SYSCALL(80, sys_getgroups16) __SYSCALL(81, sys_setgroups16) __SYSCALL_WITH_COMPAT(82, sys_old_select, compat_sys_old_select) __SYSCALL(83, sys_symlink) __SYSCALL(84, sys_lstat) __SYSCALL(85, sys_readlink) __SYSCALL(86, sys_uselib) __SYSCALL(87, sys_swapon) __SYSCALL(88, sys_reboot) __SYSCALL_WITH_COMPAT(89, sys_old_readdir, compat_sys_old_readdir) __SYSCALL_WITH_COMPAT(90, sys_old_mmap, compat_sys_ia32_mmap) __SYSCALL(91, sys_munmap) __SYSCALL_WITH_COMPAT(92, sys_truncate, compat_sys_truncate) __SYSCALL_WITH_COMPAT(93, sys_ftruncate, compat_sys_ftruncate) __SYSCALL(94, sys_fchmod) __SYSCALL(95, sys_fchown16) __SYSCALL(96, sys_getpriority) __SYSCALL(97, sys_setpriority) __SYSCALL(98, sys_ni_syscall) __SYSCALL_WITH_COMPAT(99, sys_statfs, compat_sys_statfs) __SYSCALL_WITH_COMPAT(100, sys_fstatfs, compat_sys_fstatfs) __SYSCALL(101, sys_ioperm) __SYSCALL_WITH_COMPAT(102, sys_socketcall, compat_sys_socketcall) __SYSCALL(103, sys_syslog) __SYSCALL_WITH_COMPAT(104, sys_setitimer, compat_sys_setitimer) __SYSCALL_WITH_COMPAT(105, sys_getitimer, compat_sys_getitimer) __SYSCALL_WITH_COMPAT(106, sys_newstat, compat_sys_newstat) __SYSCALL_WITH_COMPAT(107, sys_newlstat, compat_sys_newlstat) __SYSCALL_WITH_COMPAT(108, sys_newfstat, compat_sys_newfstat) __SYSCALL(109, sys_uname) __SYSCALL(110, sys_iopl) __SYSCALL(111, sys_vhangup) __SYSCALL(112, sys_ni_syscall) __SYSCALL_WITH_COMPAT(113, sys_vm86old, sys_ni_syscall) __SYSCALL_WITH_COMPAT(114, sys_wait4, compat_sys_wait4) __SYSCALL(115, sys_swapoff) __SYSCALL_WITH_COMPAT(116, sys_sysinfo, compat_sys_sysinfo) __SYSCALL_WITH_COMPAT(117, sys_ipc, compat_sys_ipc) __SYSCALL(118, sys_fsync) __SYSCALL_WITH_COMPAT(119, sys_sigreturn, compat_sys_sigreturn) __SYSCALL_WITH_COMPAT(120, sys_clone, compat_sys_ia32_clone) __SYSCALL(121, sys_setdomainname) __SYSCALL(122, sys_newuname) __SYSCALL(123, sys_modify_ldt) __SYSCALL(124, sys_adjtimex_time32) __SYSCALL(125, sys_mprotect) __SYSCALL_WITH_COMPAT(126, sys_sigprocmask, compat_sys_sigprocmask) __SYSCALL(127, sys_ni_syscall) __SYSCALL(128, sys_init_module) __SYSCALL(129, sys_delete_module) __SYSCALL(130, sys_ni_syscall) __SYSCALL(131, sys_quotactl) __SYSCALL(132, sys_getpgid) __SYSCALL(133, sys_fchdir) __SYSCALL(134, sys_ni_syscall) __SYSCALL(135, sys_sysfs) __SYSCALL(136, sys_personality) __SYSCALL(137, sys_ni_syscall) __SYSCALL(138, sys_setfsuid16) __SYSCALL(139, sys_setfsgid16) __SYSCALL(140, sys_llseek) __SYSCALL_WITH_COMPAT(141, sys_getdents, compat_sys_getdents) __SYSCALL_WITH_COMPAT(142, sys_select, compat_sys_select) __SYSCALL(143, sys_flock) __SYSCALL(144, sys_msync) __SYSCALL(145, sys_readv) __SYSCALL(146, sys_writev) __SYSCALL(147, sys_getsid) __SYSCALL(148, sys_fdatasync) __SYSCALL(149, sys_ni_syscall) __SYSCALL(150, sys_mlock) __SYSCALL(151, sys_munlock) __SYSCALL(152, sys_mlockall) __SYSCALL(153, sys_munlockall) __SYSCALL(154, sys_sched_setparam) __SYSCALL(155, sys_sched_getparam) __SYSCALL(156, sys_sched_setscheduler) __SYSCALL(157, sys_sched_getscheduler) __SYSCALL(158, sys_sched_yield) __SYSCALL(159, sys_sched_get_priority_max) __SYSCALL(160, sys_sched_get_priority_min) __SYSCALL(161, sys_sched_rr_get_interval_time32) __SYSCALL(162, sys_nanosleep_time32) __SYSCALL(163, sys_mremap) __SYSCALL(164, sys_setresuid16) __SYSCALL(165, sys_getresuid16) __SYSCALL_WITH_COMPAT(166, sys_vm86, sys_ni_syscall) __SYSCALL(167, sys_ni_syscall) __SYSCALL(168, sys_poll) __SYSCALL(169, sys_ni_syscall) __SYSCALL(170, sys_setresgid16) __SYSCALL(171, sys_getresgid16) __SYSCALL(172, sys_prctl) __SYSCALL_WITH_COMPAT(173, sys_rt_sigreturn, compat_sys_rt_sigreturn) __SYSCALL_WITH_COMPAT(174, sys_rt_sigaction, compat_sys_rt_sigaction) __SYSCALL_WITH_COMPAT(175, sys_rt_sigprocmask, compat_sys_rt_sigprocmask) __SYSCALL_WITH_COMPAT(176, sys_rt_sigpending, compat_sys_rt_sigpending) __SYSCALL_WITH_COMPAT(177, sys_rt_sigtimedwait_time32, compat_sys_rt_sigtimedwait_time32) __SYSCALL_WITH_COMPAT(178, sys_rt_sigqueueinfo, compat_sys_rt_sigqueueinfo) __SYSCALL_WITH_COMPAT(179, sys_rt_sigsuspend, compat_sys_rt_sigsuspend) __SYSCALL(180, sys_ia32_pread64) __SYSCALL(181, sys_ia32_pwrite64) __SYSCALL(182, sys_chown16) __SYSCALL(183, sys_getcwd) __SYSCALL(184, sys_capget) __SYSCALL(185, sys_capset) __SYSCALL_WITH_COMPAT(186, sys_sigaltstack, compat_sys_sigaltstack) __SYSCALL_WITH_COMPAT(187, sys_sendfile, compat_sys_sendfile) __SYSCALL(188, sys_ni_syscall) __SYSCALL(189, sys_ni_syscall) __SYSCALL(190, sys_vfork) __SYSCALL_WITH_COMPAT(191, sys_getrlimit, compat_sys_getrlimit) __SYSCALL(192, sys_mmap_pgoff) __SYSCALL(193, sys_ia32_truncate64) __SYSCALL(194, sys_ia32_ftruncate64) __SYSCALL_WITH_COMPAT(195, sys_stat64, compat_sys_ia32_stat64) __SYSCALL_WITH_COMPAT(196, sys_lstat64, compat_sys_ia32_lstat64) __SYSCALL_WITH_COMPAT(197, sys_fstat64, compat_sys_ia32_fstat64) __SYSCALL(198, sys_lchown) __SYSCALL(199, sys_getuid) __SYSCALL(200, sys_getgid) __SYSCALL(201, sys_geteuid) __SYSCALL(202, sys_getegid) __SYSCALL(203, sys_setreuid) __SYSCALL(204, sys_setregid) __SYSCALL(205, sys_getgroups) __SYSCALL(206, sys_setgroups) __SYSCALL(207, sys_fchown) __SYSCALL(208, sys_setresuid) __SYSCALL(209, sys_getresuid) __SYSCALL(210, sys_setresgid) __SYSCALL(211, sys_getresgid) __SYSCALL(212, sys_chown) __SYSCALL(213, sys_setuid) __SYSCALL(214, sys_setgid) __SYSCALL(215, sys_setfsuid) __SYSCALL(216, sys_setfsgid) __SYSCALL(217, sys_pivot_root) __SYSCALL(218, sys_mincore) __SYSCALL(219, sys_madvise) __SYSCALL(220, sys_getdents64) __SYSCALL_WITH_COMPAT(221, sys_fcntl64, compat_sys_fcntl64) __SYSCALL(222, sys_ni_syscall) __SYSCALL(223, sys_ni_syscall) __SYSCALL(224, sys_gettid) __SYSCALL(225, sys_ia32_readahead) __SYSCALL(226, sys_setxattr) __SYSCALL(227, sys_lsetxattr) __SYSCALL(228, sys_fsetxattr) __SYSCALL(229, sys_getxattr) __SYSCALL(230, sys_lgetxattr) __SYSCALL(231, sys_fgetxattr) __SYSCALL(232, sys_listxattr) __SYSCALL(233, sys_llistxattr) __SYSCALL(234, sys_flistxattr) __SYSCALL(235, sys_removexattr) __SYSCALL(236, sys_lremovexattr) __SYSCALL(237, sys_fremovexattr) __SYSCALL(238, sys_tkill) __SYSCALL(239, sys_sendfile64) __SYSCALL(240, sys_futex_time32) __SYSCALL_WITH_COMPAT(241, sys_sched_setaffinity, compat_sys_sched_setaffinity) __SYSCALL_WITH_COMPAT(242, sys_sched_getaffinity, compat_sys_sched_getaffinity) __SYSCALL(243, sys_set_thread_area) __SYSCALL(244, sys_get_thread_area) __SYSCALL_WITH_COMPAT(245, sys_io_setup, compat_sys_io_setup) __SYSCALL(246, sys_io_destroy) __SYSCALL(247, sys_io_getevents_time32) __SYSCALL_WITH_COMPAT(248, sys_io_submit, compat_sys_io_submit) __SYSCALL(249, sys_io_cancel) __SYSCALL(250, sys_ia32_fadvise64) __SYSCALL(251, sys_ni_syscall) __SYSCALL(252, sys_exit_group) __SYSCALL_WITH_COMPAT(253, sys_lookup_dcookie, compat_sys_lookup_dcookie) __SYSCALL(254, sys_epoll_create) __SYSCALL(255, sys_epoll_ctl) __SYSCALL(256, sys_epoll_wait) __SYSCALL(257, sys_remap_file_pages) __SYSCALL(258, sys_set_tid_address) __SYSCALL_WITH_COMPAT(259, sys_timer_create, compat_sys_timer_create) __SYSCALL(260, sys_timer_settime32) __SYSCALL(261, sys_timer_gettime32) __SYSCALL(262, sys_timer_getoverrun) __SYSCALL(263, sys_timer_delete) __SYSCALL(264, sys_clock_settime32) __SYSCALL(265, sys_clock_gettime32) __SYSCALL(266, sys_clock_getres_time32) __SYSCALL(267, sys_clock_nanosleep_time32) __SYSCALL_WITH_COMPAT(268, sys_statfs64, compat_sys_statfs64) __SYSCALL_WITH_COMPAT(269, sys_fstatfs64, compat_sys_fstatfs64) __SYSCALL(270, sys_tgkill) __SYSCALL(271, sys_utimes_time32) __SYSCALL(272, sys_ia32_fadvise64_64) __SYSCALL(273, sys_ni_syscall) __SYSCALL(274, sys_mbind) __SYSCALL(275, sys_get_mempolicy) __SYSCALL(276, sys_set_mempolicy) __SYSCALL_WITH_COMPAT(277, sys_mq_open, compat_sys_mq_open) __SYSCALL(278, sys_mq_unlink) __SYSCALL(279, sys_mq_timedsend_time32) __SYSCALL(280, sys_mq_timedreceive_time32) __SYSCALL_WITH_COMPAT(281, sys_mq_notify, compat_sys_mq_notify) __SYSCALL_WITH_COMPAT(282, sys_mq_getsetattr, compat_sys_mq_getsetattr) __SYSCALL_WITH_COMPAT(283, sys_kexec_load, compat_sys_kexec_load) __SYSCALL_WITH_COMPAT(284, sys_waitid, compat_sys_waitid) __SYSCALL(285, sys_ni_syscall) __SYSCALL(286, sys_add_key) __SYSCALL(287, sys_request_key) __SYSCALL_WITH_COMPAT(288, sys_keyctl, compat_sys_keyctl) __SYSCALL(289, sys_ioprio_set) __SYSCALL(290, sys_ioprio_get) __SYSCALL(291, sys_inotify_init) __SYSCALL(292, sys_inotify_add_watch) __SYSCALL(293, sys_inotify_rm_watch) __SYSCALL(294, sys_migrate_pages) __SYSCALL_WITH_COMPAT(295, sys_openat, compat_sys_openat) __SYSCALL(296, sys_mkdirat) __SYSCALL(297, sys_mknodat) __SYSCALL(298, sys_fchownat) __SYSCALL(299, sys_futimesat_time32) __SYSCALL_WITH_COMPAT(300, sys_fstatat64, compat_sys_ia32_fstatat64) __SYSCALL(301, sys_unlinkat) __SYSCALL(302, sys_renameat) __SYSCALL(303, sys_linkat) __SYSCALL(304, sys_symlinkat) __SYSCALL(305, sys_readlinkat) __SYSCALL(306, sys_fchmodat) __SYSCALL(307, sys_faccessat) __SYSCALL_WITH_COMPAT(308, sys_pselect6_time32, compat_sys_pselect6_time32) __SYSCALL_WITH_COMPAT(309, sys_ppoll_time32, compat_sys_ppoll_time32) __SYSCALL(310, sys_unshare) __SYSCALL_WITH_COMPAT(311, sys_set_robust_list, compat_sys_set_robust_list) __SYSCALL_WITH_COMPAT(312, sys_get_robust_list, compat_sys_get_robust_list) __SYSCALL(313, sys_splice) __SYSCALL(314, sys_ia32_sync_file_range) __SYSCALL(315, sys_tee) __SYSCALL(316, sys_vmsplice) __SYSCALL(317, sys_move_pages) __SYSCALL(318, sys_getcpu) __SYSCALL(319, sys_epoll_pwait) __SYSCALL(320, sys_utimensat_time32) __SYSCALL_WITH_COMPAT(321, sys_signalfd, compat_sys_signalfd) __SYSCALL(322, sys_timerfd_create) __SYSCALL(323, sys_eventfd) __SYSCALL(324, sys_ia32_fallocate) __SYSCALL(325, sys_timerfd_settime32) __SYSCALL(326, sys_timerfd_gettime32) __SYSCALL_WITH_COMPAT(327, sys_signalfd4, compat_sys_signalfd4) __SYSCALL(328, sys_eventfd2) __SYSCALL(329, sys_epoll_create1) __SYSCALL(330, sys_dup3) __SYSCALL(331, sys_pipe2) __SYSCALL(332, sys_inotify_init1) __SYSCALL_WITH_COMPAT(333, sys_preadv, compat_sys_preadv) __SYSCALL_WITH_COMPAT(334, sys_pwritev, compat_sys_pwritev) __SYSCALL_WITH_COMPAT(335, sys_rt_tgsigqueueinfo, compat_sys_rt_tgsigqueueinfo) __SYSCALL(336, sys_perf_event_open) __SYSCALL_WITH_COMPAT(337, sys_recvmmsg_time32, compat_sys_recvmmsg_time32) __SYSCALL(338, sys_fanotify_init) __SYSCALL_WITH_COMPAT(339, sys_fanotify_mark, compat_sys_fanotify_mark) __SYSCALL(340, sys_prlimit64) __SYSCALL(341, sys_name_to_handle_at) __SYSCALL_WITH_COMPAT(342, sys_open_by_handle_at, compat_sys_open_by_handle_at) __SYSCALL(343, sys_clock_adjtime32) __SYSCALL(344, sys_syncfs) __SYSCALL_WITH_COMPAT(345, sys_sendmmsg, compat_sys_sendmmsg) __SYSCALL(346, sys_setns) __SYSCALL(347, sys_process_vm_readv) __SYSCALL(348, sys_process_vm_writev) __SYSCALL(349, sys_kcmp) __SYSCALL(350, sys_finit_module) __SYSCALL(351, sys_sched_setattr) __SYSCALL(352, sys_sched_getattr) __SYSCALL(353, sys_renameat2) __SYSCALL(354, sys_seccomp) __SYSCALL(355, sys_getrandom) __SYSCALL(356, sys_memfd_create) __SYSCALL(357, sys_bpf) __SYSCALL_WITH_COMPAT(358, sys_execveat, compat_sys_execveat) __SYSCALL(359, sys_socket) __SYSCALL(360, sys_socketpair) __SYSCALL(361, sys_bind) __SYSCALL(362, sys_connect) __SYSCALL(363, sys_listen) __SYSCALL(364, sys_accept4) __SYSCALL_WITH_COMPAT(365, sys_getsockopt, sys_getsockopt) __SYSCALL_WITH_COMPAT(366, sys_setsockopt, sys_setsockopt) __SYSCALL(367, sys_getsockname) __SYSCALL(368, sys_getpeername) __SYSCALL(369, sys_sendto) __SYSCALL_WITH_COMPAT(370, sys_sendmsg, compat_sys_sendmsg) __SYSCALL_WITH_COMPAT(371, sys_recvfrom, compat_sys_recvfrom) __SYSCALL_WITH_COMPAT(372, sys_recvmsg, compat_sys_recvmsg) __SYSCALL(373, sys_shutdown) __SYSCALL(374, sys_userfaultfd) __SYSCALL(375, sys_membarrier) __SYSCALL(376, sys_mlock2) __SYSCALL(377, sys_copy_file_range) __SYSCALL_WITH_COMPAT(378, sys_preadv2, compat_sys_preadv2) __SYSCALL_WITH_COMPAT(379, sys_pwritev2, compat_sys_pwritev2) __SYSCALL(380, sys_pkey_mprotect) __SYSCALL(381, sys_pkey_alloc) __SYSCALL(382, sys_pkey_free) __SYSCALL(383, sys_statx) __SYSCALL_WITH_COMPAT(384, sys_arch_prctl, compat_sys_arch_prctl) __SYSCALL_WITH_COMPAT(385, sys_io_pgetevents_time32, compat_sys_io_pgetevents) __SYSCALL(386, sys_rseq) __SYSCALL(387, sys_ni_syscall) __SYSCALL(388, sys_ni_syscall) __SYSCALL(389, sys_ni_syscall) __SYSCALL(390, sys_ni_syscall) __SYSCALL(391, sys_ni_syscall) __SYSCALL(392, sys_ni_syscall) __SYSCALL(393, sys_semget) __SYSCALL_WITH_COMPAT(394, sys_semctl, compat_sys_semctl) __SYSCALL(395, sys_shmget) __SYSCALL_WITH_COMPAT(396, sys_shmctl, compat_sys_shmctl) __SYSCALL_WITH_COMPAT(397, sys_shmat, compat_sys_shmat) __SYSCALL(398, sys_shmdt) __SYSCALL(399, sys_msgget) __SYSCALL_WITH_COMPAT(400, sys_msgsnd, compat_sys_msgsnd) __SYSCALL_WITH_COMPAT(401, sys_msgrcv, compat_sys_msgrcv) __SYSCALL_WITH_COMPAT(402, sys_msgctl, compat_sys_msgctl) __SYSCALL(403, sys_clock_gettime) __SYSCALL(404, sys_clock_settime) __SYSCALL(405, sys_clock_adjtime) __SYSCALL(406, sys_clock_getres) __SYSCALL(407, sys_clock_nanosleep) __SYSCALL(408, sys_timer_gettime) __SYSCALL(409, sys_timer_settime) __SYSCALL(410, sys_timerfd_gettime) __SYSCALL(411, sys_timerfd_settime) __SYSCALL(412, sys_utimensat) __SYSCALL_WITH_COMPAT(413, sys_pselect6, compat_sys_pselect6_time64) __SYSCALL_WITH_COMPAT(414, sys_ppoll, compat_sys_ppoll_time64) __SYSCALL(415, sys_ni_syscall) __SYSCALL_WITH_COMPAT(416, sys_io_pgetevents, compat_sys_io_pgetevents_time64) __SYSCALL_WITH_COMPAT(417, sys_recvmmsg, compat_sys_recvmmsg_time64) __SYSCALL(418, sys_mq_timedsend) __SYSCALL(419, sys_mq_timedreceive) __SYSCALL(420, sys_semtimedop) __SYSCALL_WITH_COMPAT(421, sys_rt_sigtimedwait, compat_sys_rt_sigtimedwait_time64) __SYSCALL(422, sys_futex) __SYSCALL(423, sys_sched_rr_get_interval) __SYSCALL(424, sys_pidfd_send_signal) __SYSCALL(425, sys_io_uring_setup) __SYSCALL(426, sys_io_uring_enter) __SYSCALL(427, sys_io_uring_register) __SYSCALL(428, sys_open_tree) __SYSCALL(429, sys_move_mount) __SYSCALL(430, sys_fsopen) __SYSCALL(431, sys_fsconfig) __SYSCALL(432, sys_fsmount) __SYSCALL(433, sys_fspick) __SYSCALL(434, sys_pidfd_open) __SYSCALL(435, sys_clone3) __SYSCALL(436, sys_close_range) __SYSCALL(437, sys_openat2) __SYSCALL(438, sys_pidfd_getfd) __SYSCALL(439, sys_faccessat2) __SYSCALL(440, sys_process_madvise) __SYSCALL_WITH_COMPAT(441, sys_epoll_pwait2, compat_sys_epoll_pwait2) __SYSCALL(442, sys_mount_setattr) __SYSCALL(443, sys_quotactl_fd) __SYSCALL(444, sys_landlock_create_ruleset) __SYSCALL(445, sys_landlock_add_rule) __SYSCALL(446, sys_landlock_restrict_self) __SYSCALL(447, sys_memfd_secret) __SYSCALL(448, sys_process_mrelease) PK ! ��w� .unistd_64_x32.h.cmdnu �[��� cmd_arch/x86/include/generated/asm/unistd_64_x32.h := sh /build/linux-6CgZId/linux-5.15.0/scripts/syscallhdr.sh --abis x32 --emit-nr --prefix x32_ /build/linux-6CgZId/linux-5.15.0/arch/x86/entry/syscalls/syscall_64.tbl arch/x86/include/generated/asm/unistd_64_x32.h PK ! �k .unistd_32_ia32.h.cmdnu �[��� cmd_arch/x86/include/generated/asm/unistd_32_ia32.h := sh /build/linux-6CgZId/linux-5.15.0/scripts/syscallhdr.sh --abis i386 --emit-nr --prefix ia32_ /build/linux-6CgZId/linux-5.15.0/arch/x86/entry/syscalls/syscall_32.tbl arch/x86/include/generated/asm/unistd_32_ia32.h PK ! �`�� export.hnu �[��� #include <asm-generic/export.h> PK ! ���� mmiowb.hnu �[��� #include <asm-generic/mmiowb.h> PK ! �˟# # kmap_size.hnu �[��� #include <asm-generic/kmap_size.h> PK ! q�8�& & mcs_spinlock.hnu �[��� #include <asm-generic/mcs_spinlock.h> PK ! ��K' ' early_ioremap.hnu �[��� #include <asm-generic/early_ioremap.h> PK ! �6J>� � .syscalls_64.h.cmdnu �[��� cmd_arch/x86/include/generated/asm/syscalls_64.h := sh /build/linux-6CgZId/linux-5.15.0/scripts/syscalltbl.sh --abis common,64 /build/linux-6CgZId/linux-5.15.0/arch/x86/entry/syscalls/syscall_64.tbl arch/x86/include/generated/asm/syscalls_64.h PK ! _k�,e e .xen-hypercalls.h.cmdnu �[��� cmd_arch/x86/include/generated/asm/xen-hypercalls.h := sh '/build/linux-6CgZId/linux-5.15.0/scripts/xen-hypercalls.sh' arch/x86/include/generated/asm/xen-hypercalls.h /build/linux-6CgZId/linux-5.15.0/include/xen/interface/xen-mca.h /build/linux-6CgZId/linux-5.15.0/include/xen/interface/xen.h /build/linux-6CgZId/linux-5.15.0/include/xen/interface/xenpmu.h PK ! ���*� � .syscalls_x32.h.cmdnu �[��� cmd_arch/x86/include/generated/asm/syscalls_x32.h := sh /build/linux-6CgZId/linux-5.15.0/scripts/syscalltbl.sh --abis common,x32 /build/linux-6CgZId/linux-5.15.0/arch/x86/entry/syscalls/syscall_64.tbl arch/x86/include/generated/asm/syscalls_x32.h PK ! ��H7 H7 unistd_32_ia32.hnu �[��� #ifndef _UAPI_ASM_UNISTD_32_IA32_H #define _UAPI_ASM_UNISTD_32_IA32_H #define __NR_ia32_restart_syscall 0 #define __NR_ia32_exit 1 #define __NR_ia32_fork 2 #define __NR_ia32_read 3 #define __NR_ia32_write 4 #define __NR_ia32_open 5 #define __NR_ia32_close 6 #define __NR_ia32_waitpid 7 #define __NR_ia32_creat 8 #define __NR_ia32_link 9 #define __NR_ia32_unlink 10 #define __NR_ia32_execve 11 #define __NR_ia32_chdir 12 #define __NR_ia32_time 13 #define __NR_ia32_mknod 14 #define __NR_ia32_chmod 15 #define __NR_ia32_lchown 16 #define __NR_ia32_break 17 #define __NR_ia32_oldstat 18 #define __NR_ia32_lseek 19 #define __NR_ia32_getpid 20 #define __NR_ia32_mount 21 #define __NR_ia32_umount 22 #define __NR_ia32_setuid 23 #define __NR_ia32_getuid 24 #define __NR_ia32_stime 25 #define __NR_ia32_ptrace 26 #define __NR_ia32_alarm 27 #define __NR_ia32_oldfstat 28 #define __NR_ia32_pause 29 #define __NR_ia32_utime 30 #define __NR_ia32_stty 31 #define __NR_ia32_gtty 32 #define __NR_ia32_access 33 #define __NR_ia32_nice 34 #define __NR_ia32_ftime 35 #define __NR_ia32_sync 36 #define __NR_ia32_kill 37 #define __NR_ia32_rename 38 #define __NR_ia32_mkdir 39 #define __NR_ia32_rmdir 40 #define __NR_ia32_dup 41 #define __NR_ia32_pipe 42 #define __NR_ia32_times 43 #define __NR_ia32_prof 44 #define __NR_ia32_brk 45 #define __NR_ia32_setgid 46 #define __NR_ia32_getgid 47 #define __NR_ia32_signal 48 #define __NR_ia32_geteuid 49 #define __NR_ia32_getegid 50 #define __NR_ia32_acct 51 #define __NR_ia32_umount2 52 #define __NR_ia32_lock 53 #define __NR_ia32_ioctl 54 #define __NR_ia32_fcntl 55 #define __NR_ia32_mpx 56 #define __NR_ia32_setpgid 57 #define __NR_ia32_ulimit 58 #define __NR_ia32_oldolduname 59 #define __NR_ia32_umask 60 #define __NR_ia32_chroot 61 #define __NR_ia32_ustat 62 #define __NR_ia32_dup2 63 #define __NR_ia32_getppid 64 #define __NR_ia32_getpgrp 65 #define __NR_ia32_setsid 66 #define __NR_ia32_sigaction 67 #define __NR_ia32_sgetmask 68 #define __NR_ia32_ssetmask 69 #define __NR_ia32_setreuid 70 #define __NR_ia32_setregid 71 #define __NR_ia32_sigsuspend 72 #define __NR_ia32_sigpending 73 #define __NR_ia32_sethostname 74 #define __NR_ia32_setrlimit 75 #define __NR_ia32_getrlimit 76 #define __NR_ia32_getrusage 77 #define __NR_ia32_gettimeofday 78 #define __NR_ia32_settimeofday 79 #define __NR_ia32_getgroups 80 #define __NR_ia32_setgroups 81 #define __NR_ia32_select 82 #define __NR_ia32_symlink 83 #define __NR_ia32_oldlstat 84 #define __NR_ia32_readlink 85 #define __NR_ia32_uselib 86 #define __NR_ia32_swapon 87 #define __NR_ia32_reboot 88 #define __NR_ia32_readdir 89 #define __NR_ia32_mmap 90 #define __NR_ia32_munmap 91 #define __NR_ia32_truncate 92 #define __NR_ia32_ftruncate 93 #define __NR_ia32_fchmod 94 #define __NR_ia32_fchown 95 #define __NR_ia32_getpriority 96 #define __NR_ia32_setpriority 97 #define __NR_ia32_profil 98 #define __NR_ia32_statfs 99 #define __NR_ia32_fstatfs 100 #define __NR_ia32_ioperm 101 #define __NR_ia32_socketcall 102 #define __NR_ia32_syslog 103 #define __NR_ia32_setitimer 104 #define __NR_ia32_getitimer 105 #define __NR_ia32_stat 106 #define __NR_ia32_lstat 107 #define __NR_ia32_fstat 108 #define __NR_ia32_olduname 109 #define __NR_ia32_iopl 110 #define __NR_ia32_vhangup 111 #define __NR_ia32_idle 112 #define __NR_ia32_vm86old 113 #define __NR_ia32_wait4 114 #define __NR_ia32_swapoff 115 #define __NR_ia32_sysinfo 116 #define __NR_ia32_ipc 117 #define __NR_ia32_fsync 118 #define __NR_ia32_sigreturn 119 #define __NR_ia32_clone 120 #define __NR_ia32_setdomainname 121 #define __NR_ia32_uname 122 #define __NR_ia32_modify_ldt 123 #define __NR_ia32_adjtimex 124 #define __NR_ia32_mprotect 125 #define __NR_ia32_sigprocmask 126 #define __NR_ia32_create_module 127 #define __NR_ia32_init_module 128 #define __NR_ia32_delete_module 129 #define __NR_ia32_get_kernel_syms 130 #define __NR_ia32_quotactl 131 #define __NR_ia32_getpgid 132 #define __NR_ia32_fchdir 133 #define __NR_ia32_bdflush 134 #define __NR_ia32_sysfs 135 #define __NR_ia32_personality 136 #define __NR_ia32_afs_syscall 137 #define __NR_ia32_setfsuid 138 #define __NR_ia32_setfsgid 139 #define __NR_ia32__llseek 140 #define __NR_ia32_getdents 141 #define __NR_ia32__newselect 142 #define __NR_ia32_flock 143 #define __NR_ia32_msync 144 #define __NR_ia32_readv 145 #define __NR_ia32_writev 146 #define __NR_ia32_getsid 147 #define __NR_ia32_fdatasync 148 #define __NR_ia32__sysctl 149 #define __NR_ia32_mlock 150 #define __NR_ia32_munlock 151 #define __NR_ia32_mlockall 152 #define __NR_ia32_munlockall 153 #define __NR_ia32_sched_setparam 154 #define __NR_ia32_sched_getparam 155 #define __NR_ia32_sched_setscheduler 156 #define __NR_ia32_sched_getscheduler 157 #define __NR_ia32_sched_yield 158 #define __NR_ia32_sched_get_priority_max 159 #define __NR_ia32_sched_get_priority_min 160 #define __NR_ia32_sched_rr_get_interval 161 #define __NR_ia32_nanosleep 162 #define __NR_ia32_mremap 163 #define __NR_ia32_setresuid 164 #define __NR_ia32_getresuid 165 #define __NR_ia32_vm86 166 #define __NR_ia32_query_module 167 #define __NR_ia32_poll 168 #define __NR_ia32_nfsservctl 169 #define __NR_ia32_setresgid 170 #define __NR_ia32_getresgid 171 #define __NR_ia32_prctl 172 #define __NR_ia32_rt_sigreturn 173 #define __NR_ia32_rt_sigaction 174 #define __NR_ia32_rt_sigprocmask 175 #define __NR_ia32_rt_sigpending 176 #define __NR_ia32_rt_sigtimedwait 177 #define __NR_ia32_rt_sigqueueinfo 178 #define __NR_ia32_rt_sigsuspend 179 #define __NR_ia32_pread64 180 #define __NR_ia32_pwrite64 181 #define __NR_ia32_chown 182 #define __NR_ia32_getcwd 183 #define __NR_ia32_capget 184 #define __NR_ia32_capset 185 #define __NR_ia32_sigaltstack 186 #define __NR_ia32_sendfile 187 #define __NR_ia32_getpmsg 188 #define __NR_ia32_putpmsg 189 #define __NR_ia32_vfork 190 #define __NR_ia32_ugetrlimit 191 #define __NR_ia32_mmap2 192 #define __NR_ia32_truncate64 193 #define __NR_ia32_ftruncate64 194 #define __NR_ia32_stat64 195 #define __NR_ia32_lstat64 196 #define __NR_ia32_fstat64 197 #define __NR_ia32_lchown32 198 #define __NR_ia32_getuid32 199 #define __NR_ia32_getgid32 200 #define __NR_ia32_geteuid32 201 #define __NR_ia32_getegid32 202 #define __NR_ia32_setreuid32 203 #define __NR_ia32_setregid32 204 #define __NR_ia32_getgroups32 205 #define __NR_ia32_setgroups32 206 #define __NR_ia32_fchown32 207 #define __NR_ia32_setresuid32 208 #define __NR_ia32_getresuid32 209 #define __NR_ia32_setresgid32 210 #define __NR_ia32_getresgid32 211 #define __NR_ia32_chown32 212 #define __NR_ia32_setuid32 213 #define __NR_ia32_setgid32 214 #define __NR_ia32_setfsuid32 215 #define __NR_ia32_setfsgid32 216 #define __NR_ia32_pivot_root 217 #define __NR_ia32_mincore 218 #define __NR_ia32_madvise 219 #define __NR_ia32_getdents64 220 #define __NR_ia32_fcntl64 221 #define __NR_ia32_gettid 224 #define __NR_ia32_readahead 225 #define __NR_ia32_setxattr 226 #define __NR_ia32_lsetxattr 227 #define __NR_ia32_fsetxattr 228 #define __NR_ia32_getxattr 229 #define __NR_ia32_lgetxattr 230 #define __NR_ia32_fgetxattr 231 #define __NR_ia32_listxattr 232 #define __NR_ia32_llistxattr 233 #define __NR_ia32_flistxattr 234 #define __NR_ia32_removexattr 235 #define __NR_ia32_lremovexattr 236 #define __NR_ia32_fremovexattr 237 #define __NR_ia32_tkill 238 #define __NR_ia32_sendfile64 239 #define __NR_ia32_futex 240 #define __NR_ia32_sched_setaffinity 241 #define __NR_ia32_sched_getaffinity 242 #define __NR_ia32_set_thread_area 243 #define __NR_ia32_get_thread_area 244 #define __NR_ia32_io_setup 245 #define __NR_ia32_io_destroy 246 #define __NR_ia32_io_getevents 247 #define __NR_ia32_io_submit 248 #define __NR_ia32_io_cancel 249 #define __NR_ia32_fadvise64 250 #define __NR_ia32_exit_group 252 #define __NR_ia32_lookup_dcookie 253 #define __NR_ia32_epoll_create 254 #define __NR_ia32_epoll_ctl 255 #define __NR_ia32_epoll_wait 256 #define __NR_ia32_remap_file_pages 257 #define __NR_ia32_set_tid_address 258 #define __NR_ia32_timer_create 259 #define __NR_ia32_timer_settime 260 #define __NR_ia32_timer_gettime 261 #define __NR_ia32_timer_getoverrun 262 #define __NR_ia32_timer_delete 263 #define __NR_ia32_clock_settime 264 #define __NR_ia32_clock_gettime 265 #define __NR_ia32_clock_getres 266 #define __NR_ia32_clock_nanosleep 267 #define __NR_ia32_statfs64 268 #define __NR_ia32_fstatfs64 269 #define __NR_ia32_tgkill 270 #define __NR_ia32_utimes 271 #define __NR_ia32_fadvise64_64 272 #define __NR_ia32_vserver 273 #define __NR_ia32_mbind 274 #define __NR_ia32_get_mempolicy 275 #define __NR_ia32_set_mempolicy 276 #define __NR_ia32_mq_open 277 #define __NR_ia32_mq_unlink 278 #define __NR_ia32_mq_timedsend 279 #define __NR_ia32_mq_timedreceive 280 #define __NR_ia32_mq_notify 281 #define __NR_ia32_mq_getsetattr 282 #define __NR_ia32_kexec_load 283 #define __NR_ia32_waitid 284 #define __NR_ia32_add_key 286 #define __NR_ia32_request_key 287 #define __NR_ia32_keyctl 288 #define __NR_ia32_ioprio_set 289 #define __NR_ia32_ioprio_get 290 #define __NR_ia32_inotify_init 291 #define __NR_ia32_inotify_add_watch 292 #define __NR_ia32_inotify_rm_watch 293 #define __NR_ia32_migrate_pages 294 #define __NR_ia32_openat 295 #define __NR_ia32_mkdirat 296 #define __NR_ia32_mknodat 297 #define __NR_ia32_fchownat 298 #define __NR_ia32_futimesat 299 #define __NR_ia32_fstatat64 300 #define __NR_ia32_unlinkat 301 #define __NR_ia32_renameat 302 #define __NR_ia32_linkat 303 #define __NR_ia32_symlinkat 304 #define __NR_ia32_readlinkat 305 #define __NR_ia32_fchmodat 306 #define __NR_ia32_faccessat 307 #define __NR_ia32_pselect6 308 #define __NR_ia32_ppoll 309 #define __NR_ia32_unshare 310 #define __NR_ia32_set_robust_list 311 #define __NR_ia32_get_robust_list 312 #define __NR_ia32_splice 313 #define __NR_ia32_sync_file_range 314 #define __NR_ia32_tee 315 #define __NR_ia32_vmsplice 316 #define __NR_ia32_move_pages 317 #define __NR_ia32_getcpu 318 #define __NR_ia32_epoll_pwait 319 #define __NR_ia32_utimensat 320 #define __NR_ia32_signalfd 321 #define __NR_ia32_timerfd_create 322 #define __NR_ia32_eventfd 323 #define __NR_ia32_fallocate 324 #define __NR_ia32_timerfd_settime 325 #define __NR_ia32_timerfd_gettime 326 #define __NR_ia32_signalfd4 327 #define __NR_ia32_eventfd2 328 #define __NR_ia32_epoll_create1 329 #define __NR_ia32_dup3 330 #define __NR_ia32_pipe2 331 #define __NR_ia32_inotify_init1 332 #define __NR_ia32_preadv 333 #define __NR_ia32_pwritev 334 #define __NR_ia32_rt_tgsigqueueinfo 335 #define __NR_ia32_perf_event_open 336 #define __NR_ia32_recvmmsg 337 #define __NR_ia32_fanotify_init 338 #define __NR_ia32_fanotify_mark 339 #define __NR_ia32_prlimit64 340 #define __NR_ia32_name_to_handle_at 341 #define __NR_ia32_open_by_handle_at 342 #define __NR_ia32_clock_adjtime 343 #define __NR_ia32_syncfs 344 #define __NR_ia32_sendmmsg 345 #define __NR_ia32_setns 346 #define __NR_ia32_process_vm_readv 347 #define __NR_ia32_process_vm_writev 348 #define __NR_ia32_kcmp 349 #define __NR_ia32_finit_module 350 #define __NR_ia32_sched_setattr 351 #define __NR_ia32_sched_getattr 352 #define __NR_ia32_renameat2 353 #define __NR_ia32_seccomp 354 #define __NR_ia32_getrandom 355 #define __NR_ia32_memfd_create 356 #define __NR_ia32_bpf 357 #define __NR_ia32_execveat 358 #define __NR_ia32_socket 359 #define __NR_ia32_socketpair 360 #define __NR_ia32_bind 361 #define __NR_ia32_connect 362 #define __NR_ia32_listen 363 #define __NR_ia32_accept4 364 #define __NR_ia32_getsockopt 365 #define __NR_ia32_setsockopt 366 #define __NR_ia32_getsockname 367 #define __NR_ia32_getpeername 368 #define __NR_ia32_sendto 369 #define __NR_ia32_sendmsg 370 #define __NR_ia32_recvfrom 371 #define __NR_ia32_recvmsg 372 #define __NR_ia32_shutdown 373 #define __NR_ia32_userfaultfd 374 #define __NR_ia32_membarrier 375 #define __NR_ia32_mlock2 376 #define __NR_ia32_copy_file_range 377 #define __NR_ia32_preadv2 378 #define __NR_ia32_pwritev2 379 #define __NR_ia32_pkey_mprotect 380 #define __NR_ia32_pkey_alloc 381 #define __NR_ia32_pkey_free 382 #define __NR_ia32_statx 383 #define __NR_ia32_arch_prctl 384 #define __NR_ia32_io_pgetevents 385 #define __NR_ia32_rseq 386 #define __NR_ia32_semget 393 #define __NR_ia32_semctl 394 #define __NR_ia32_shmget 395 #define __NR_ia32_shmctl 396 #define __NR_ia32_shmat 397 #define __NR_ia32_shmdt 398 #define __NR_ia32_msgget 399 #define __NR_ia32_msgsnd 400 #define __NR_ia32_msgrcv 401 #define __NR_ia32_msgctl 402 #define __NR_ia32_clock_gettime64 403 #define __NR_ia32_clock_settime64 404 #define __NR_ia32_clock_adjtime64 405 #define __NR_ia32_clock_getres_time64 406 #define __NR_ia32_clock_nanosleep_time64 407 #define __NR_ia32_timer_gettime64 408 #define __NR_ia32_timer_settime64 409 #define __NR_ia32_timerfd_gettime64 410 #define __NR_ia32_timerfd_settime64 411 #define __NR_ia32_utimensat_time64 412 #define __NR_ia32_pselect6_time64 413 #define __NR_ia32_ppoll_time64 414 #define __NR_ia32_io_pgetevents_time64 416 #define __NR_ia32_recvmmsg_time64 417 #define __NR_ia32_mq_timedsend_time64 418 #define __NR_ia32_mq_timedreceive_time64 419 #define __NR_ia32_semtimedop_time64 420 #define __NR_ia32_rt_sigtimedwait_time64 421 #define __NR_ia32_futex_time64 422 #define __NR_ia32_sched_rr_get_interval_time64 423 #define __NR_ia32_pidfd_send_signal 424 #define __NR_ia32_io_uring_setup 425 #define __NR_ia32_io_uring_enter 426 #define __NR_ia32_io_uring_register 427 #define __NR_ia32_open_tree 428 #define __NR_ia32_move_mount 429 #define __NR_ia32_fsopen 430 #define __NR_ia32_fsconfig 431 #define __NR_ia32_fsmount 432 #define __NR_ia32_fspick 433 #define __NR_ia32_pidfd_open 434 #define __NR_ia32_clone3 435 #define __NR_ia32_close_range 436 #define __NR_ia32_openat2 437 #define __NR_ia32_pidfd_getfd 438 #define __NR_ia32_faccessat2 439 #define __NR_ia32_process_madvise 440 #define __NR_ia32_epoll_pwait2 441 #define __NR_ia32_mount_setattr 442 #define __NR_ia32_quotactl_fd 443 #define __NR_ia32_landlock_create_ruleset 444 #define __NR_ia32_landlock_add_rule 445 #define __NR_ia32_landlock_restrict_self 446 #define __NR_ia32_memfd_secret 447 #define __NR_ia32_process_mrelease 448 #ifdef __KERNEL__ #define __NR_ia32_syscalls 449 #endif #endif /* _UAPI_ASM_UNISTD_32_IA32_H */ PK ! �Ļ4# # unaligned.hnu �[��� #include <asm-generic/unaligned.h> PK ! �^=�! ! local64.hnu �[��� #include <asm-generic/local64.h> PK ! \P�fA fA syscalls_x32.hnu �[��� __SYSCALL(0, sys_read) __SYSCALL(1, sys_write) __SYSCALL(2, sys_open) __SYSCALL(3, sys_close) __SYSCALL(4, sys_newstat) __SYSCALL(5, sys_newfstat) __SYSCALL(6, sys_newlstat) __SYSCALL(7, sys_poll) __SYSCALL(8, sys_lseek) __SYSCALL(9, sys_mmap) __SYSCALL(10, sys_mprotect) __SYSCALL(11, sys_munmap) __SYSCALL(12, sys_brk) __SYSCALL(13, sys_ni_syscall) __SYSCALL(14, sys_rt_sigprocmask) __SYSCALL(15, sys_ni_syscall) __SYSCALL(16, sys_ni_syscall) __SYSCALL(17, sys_pread64) __SYSCALL(18, sys_pwrite64) __SYSCALL(19, sys_ni_syscall) __SYSCALL(20, sys_ni_syscall) __SYSCALL(21, sys_access) __SYSCALL(22, sys_pipe) __SYSCALL(23, sys_select) __SYSCALL(24, sys_sched_yield) __SYSCALL(25, sys_mremap) __SYSCALL(26, sys_msync) __SYSCALL(27, sys_mincore) __SYSCALL(28, sys_madvise) __SYSCALL(29, sys_shmget) __SYSCALL(30, sys_shmat) __SYSCALL(31, sys_shmctl) __SYSCALL(32, sys_dup) __SYSCALL(33, sys_dup2) __SYSCALL(34, sys_pause) __SYSCALL(35, sys_nanosleep) __SYSCALL(36, sys_getitimer) __SYSCALL(37, sys_alarm) __SYSCALL(38, sys_setitimer) __SYSCALL(39, sys_getpid) __SYSCALL(40, sys_sendfile64) __SYSCALL(41, sys_socket) __SYSCALL(42, sys_connect) __SYSCALL(43, sys_accept) __SYSCALL(44, sys_sendto) __SYSCALL(45, sys_ni_syscall) __SYSCALL(46, sys_ni_syscall) __SYSCALL(47, sys_ni_syscall) __SYSCALL(48, sys_shutdown) __SYSCALL(49, sys_bind) __SYSCALL(50, sys_listen) __SYSCALL(51, sys_getsockname) __SYSCALL(52, sys_getpeername) __SYSCALL(53, sys_socketpair) __SYSCALL(54, sys_ni_syscall) __SYSCALL(55, sys_ni_syscall) __SYSCALL(56, sys_clone) __SYSCALL(57, sys_fork) __SYSCALL(58, sys_vfork) __SYSCALL(59, sys_ni_syscall) __SYSCALL(60, sys_exit) __SYSCALL(61, sys_wait4) __SYSCALL(62, sys_kill) __SYSCALL(63, sys_newuname) __SYSCALL(64, sys_semget) __SYSCALL(65, sys_semop) __SYSCALL(66, sys_semctl) __SYSCALL(67, sys_shmdt) __SYSCALL(68, sys_msgget) __SYSCALL(69, sys_msgsnd) __SYSCALL(70, sys_msgrcv) __SYSCALL(71, sys_msgctl) __SYSCALL(72, sys_fcntl) __SYSCALL(73, sys_flock) __SYSCALL(74, sys_fsync) __SYSCALL(75, sys_fdatasync) __SYSCALL(76, sys_truncate) __SYSCALL(77, sys_ftruncate) __SYSCALL(78, sys_getdents) __SYSCALL(79, sys_getcwd) __SYSCALL(80, sys_chdir) __SYSCALL(81, sys_fchdir) __SYSCALL(82, sys_rename) __SYSCALL(83, sys_mkdir) __SYSCALL(84, sys_rmdir) __SYSCALL(85, sys_creat) __SYSCALL(86, sys_link) __SYSCALL(87, sys_unlink) __SYSCALL(88, sys_symlink) __SYSCALL(89, sys_readlink) __SYSCALL(90, sys_chmod) __SYSCALL(91, sys_fchmod) __SYSCALL(92, sys_chown) __SYSCALL(93, sys_fchown) __SYSCALL(94, sys_lchown) __SYSCALL(95, sys_umask) __SYSCALL(96, sys_gettimeofday) __SYSCALL(97, sys_getrlimit) __SYSCALL(98, sys_getrusage) __SYSCALL(99, sys_sysinfo) __SYSCALL(100, sys_times) __SYSCALL(101, sys_ni_syscall) __SYSCALL(102, sys_getuid) __SYSCALL(103, sys_syslog) __SYSCALL(104, sys_getgid) __SYSCALL(105, sys_setuid) __SYSCALL(106, sys_setgid) __SYSCALL(107, sys_geteuid) __SYSCALL(108, sys_getegid) __SYSCALL(109, sys_setpgid) __SYSCALL(110, sys_getppid) __SYSCALL(111, sys_getpgrp) __SYSCALL(112, sys_setsid) __SYSCALL(113, sys_setreuid) __SYSCALL(114, sys_setregid) __SYSCALL(115, sys_getgroups) __SYSCALL(116, sys_setgroups) __SYSCALL(117, sys_setresuid) __SYSCALL(118, sys_getresuid) __SYSCALL(119, sys_setresgid) __SYSCALL(120, sys_getresgid) __SYSCALL(121, sys_getpgid) __SYSCALL(122, sys_setfsuid) __SYSCALL(123, sys_setfsgid) __SYSCALL(124, sys_getsid) __SYSCALL(125, sys_capget) __SYSCALL(126, sys_capset) __SYSCALL(127, sys_ni_syscall) __SYSCALL(128, sys_ni_syscall) __SYSCALL(129, sys_ni_syscall) __SYSCALL(130, sys_rt_sigsuspend) __SYSCALL(131, sys_ni_syscall) __SYSCALL(132, sys_utime) __SYSCALL(133, sys_mknod) __SYSCALL(134, sys_ni_syscall) __SYSCALL(135, sys_personality) __SYSCALL(136, sys_ustat) __SYSCALL(137, sys_statfs) __SYSCALL(138, sys_fstatfs) __SYSCALL(139, sys_sysfs) __SYSCALL(140, sys_getpriority) __SYSCALL(141, sys_setpriority) __SYSCALL(142, sys_sched_setparam) __SYSCALL(143, sys_sched_getparam) __SYSCALL(144, sys_sched_setscheduler) __SYSCALL(145, sys_sched_getscheduler) __SYSCALL(146, sys_sched_get_priority_max) __SYSCALL(147, sys_sched_get_priority_min) __SYSCALL(148, sys_sched_rr_get_interval) __SYSCALL(149, sys_mlock) __SYSCALL(150, sys_munlock) __SYSCALL(151, sys_mlockall) __SYSCALL(152, sys_munlockall) __SYSCALL(153, sys_vhangup) __SYSCALL(154, sys_modify_ldt) __SYSCALL(155, sys_pivot_root) __SYSCALL(156, sys_ni_syscall) __SYSCALL(157, sys_prctl) __SYSCALL(158, sys_arch_prctl) __SYSCALL(159, sys_adjtimex) __SYSCALL(160, sys_setrlimit) __SYSCALL(161, sys_chroot) __SYSCALL(162, sys_sync) __SYSCALL(163, sys_acct) __SYSCALL(164, sys_settimeofday) __SYSCALL(165, sys_mount) __SYSCALL(166, sys_umount) __SYSCALL(167, sys_swapon) __SYSCALL(168, sys_swapoff) __SYSCALL(169, sys_reboot) __SYSCALL(170, sys_sethostname) __SYSCALL(171, sys_setdomainname) __SYSCALL(172, sys_iopl) __SYSCALL(173, sys_ioperm) __SYSCALL(174, sys_ni_syscall) __SYSCALL(175, sys_init_module) __SYSCALL(176, sys_delete_module) __SYSCALL(177, sys_ni_syscall) __SYSCALL(178, sys_ni_syscall) __SYSCALL(179, sys_quotactl) __SYSCALL(180, sys_ni_syscall) __SYSCALL(181, sys_ni_syscall) __SYSCALL(182, sys_ni_syscall) __SYSCALL(183, sys_ni_syscall) __SYSCALL(184, sys_ni_syscall) __SYSCALL(185, sys_ni_syscall) __SYSCALL(186, sys_gettid) __SYSCALL(187, sys_readahead) __SYSCALL(188, sys_setxattr) __SYSCALL(189, sys_lsetxattr) __SYSCALL(190, sys_fsetxattr) __SYSCALL(191, sys_getxattr) __SYSCALL(192, sys_lgetxattr) __SYSCALL(193, sys_fgetxattr) __SYSCALL(194, sys_listxattr) __SYSCALL(195, sys_llistxattr) __SYSCALL(196, sys_flistxattr) __SYSCALL(197, sys_removexattr) __SYSCALL(198, sys_lremovexattr) __SYSCALL(199, sys_fremovexattr) __SYSCALL(200, sys_tkill) __SYSCALL(201, sys_time) __SYSCALL(202, sys_futex) __SYSCALL(203, sys_sched_setaffinity) __SYSCALL(204, sys_sched_getaffinity) __SYSCALL(205, sys_ni_syscall) __SYSCALL(206, sys_ni_syscall) __SYSCALL(207, sys_io_destroy) __SYSCALL(208, sys_io_getevents) __SYSCALL(209, sys_ni_syscall) __SYSCALL(210, sys_io_cancel) __SYSCALL(211, sys_ni_syscall) __SYSCALL(212, sys_lookup_dcookie) __SYSCALL(213, sys_epoll_create) __SYSCALL(214, sys_ni_syscall) __SYSCALL(215, sys_ni_syscall) __SYSCALL(216, sys_remap_file_pages) __SYSCALL(217, sys_getdents64) __SYSCALL(218, sys_set_tid_address) __SYSCALL(219, sys_restart_syscall) __SYSCALL(220, sys_semtimedop) __SYSCALL(221, sys_fadvise64) __SYSCALL(222, sys_ni_syscall) __SYSCALL(223, sys_timer_settime) __SYSCALL(224, sys_timer_gettime) __SYSCALL(225, sys_timer_getoverrun) __SYSCALL(226, sys_timer_delete) __SYSCALL(227, sys_clock_settime) __SYSCALL(228, sys_clock_gettime) __SYSCALL(229, sys_clock_getres) __SYSCALL(230, sys_clock_nanosleep) __SYSCALL(231, sys_exit_group) __SYSCALL(232, sys_epoll_wait) __SYSCALL(233, sys_epoll_ctl) __SYSCALL(234, sys_tgkill) __SYSCALL(235, sys_utimes) __SYSCALL(236, sys_ni_syscall) __SYSCALL(237, sys_mbind) __SYSCALL(238, sys_set_mempolicy) __SYSCALL(239, sys_get_mempolicy) __SYSCALL(240, sys_mq_open) __SYSCALL(241, sys_mq_unlink) __SYSCALL(242, sys_mq_timedsend) __SYSCALL(243, sys_mq_timedreceive) __SYSCALL(244, sys_ni_syscall) __SYSCALL(245, sys_mq_getsetattr) __SYSCALL(246, sys_ni_syscall) __SYSCALL(247, sys_ni_syscall) __SYSCALL(248, sys_add_key) __SYSCALL(249, sys_request_key) __SYSCALL(250, sys_keyctl) __SYSCALL(251, sys_ioprio_set) __SYSCALL(252, sys_ioprio_get) __SYSCALL(253, sys_inotify_init) __SYSCALL(254, sys_inotify_add_watch) __SYSCALL(255, sys_inotify_rm_watch) __SYSCALL(256, sys_migrate_pages) __SYSCALL(257, sys_openat) __SYSCALL(258, sys_mkdirat) __SYSCALL(259, sys_mknodat) __SYSCALL(260, sys_fchownat) __SYSCALL(261, sys_futimesat) __SYSCALL(262, sys_newfstatat) __SYSCALL(263, sys_unlinkat) __SYSCALL(264, sys_renameat) __SYSCALL(265, sys_linkat) __SYSCALL(266, sys_symlinkat) __SYSCALL(267, sys_readlinkat) __SYSCALL(268, sys_fchmodat) __SYSCALL(269, sys_faccessat) __SYSCALL(270, sys_pselect6) __SYSCALL(271, sys_ppoll) __SYSCALL(272, sys_unshare) __SYSCALL(273, sys_ni_syscall) __SYSCALL(274, sys_ni_syscall) __SYSCALL(275, sys_splice) __SYSCALL(276, sys_tee) __SYSCALL(277, sys_sync_file_range) __SYSCALL(278, sys_ni_syscall) __SYSCALL(279, sys_ni_syscall) __SYSCALL(280, sys_utimensat) __SYSCALL(281, sys_epoll_pwait) __SYSCALL(282, sys_signalfd) __SYSCALL(283, sys_timerfd_create) __SYSCALL(284, sys_eventfd) __SYSCALL(285, sys_fallocate) __SYSCALL(286, sys_timerfd_settime) __SYSCALL(287, sys_timerfd_gettime) __SYSCALL(288, sys_accept4) __SYSCALL(289, sys_signalfd4) __SYSCALL(290, sys_eventfd2) __SYSCALL(291, sys_epoll_create1) __SYSCALL(292, sys_dup3) __SYSCALL(293, sys_pipe2) __SYSCALL(294, sys_inotify_init1) __SYSCALL(295, sys_ni_syscall) __SYSCALL(296, sys_ni_syscall) __SYSCALL(297, sys_ni_syscall) __SYSCALL(298, sys_perf_event_open) __SYSCALL(299, sys_ni_syscall) __SYSCALL(300, sys_fanotify_init) __SYSCALL(301, sys_fanotify_mark) __SYSCALL(302, sys_prlimit64) __SYSCALL(303, sys_name_to_handle_at) __SYSCALL(304, sys_open_by_handle_at) __SYSCALL(305, sys_clock_adjtime) __SYSCALL(306, sys_syncfs) __SYSCALL(307, sys_ni_syscall) __SYSCALL(308, sys_setns) __SYSCALL(309, sys_getcpu) __SYSCALL(310, sys_ni_syscall) __SYSCALL(311, sys_ni_syscall) __SYSCALL(312, sys_kcmp) __SYSCALL(313, sys_finit_module) __SYSCALL(314, sys_sched_setattr) __SYSCALL(315, sys_sched_getattr) __SYSCALL(316, sys_renameat2) __SYSCALL(317, sys_seccomp) __SYSCALL(318, sys_getrandom) __SYSCALL(319, sys_memfd_create) __SYSCALL(320, sys_kexec_file_load) __SYSCALL(321, sys_bpf) __SYSCALL(322, sys_ni_syscall) __SYSCALL(323, sys_userfaultfd) __SYSCALL(324, sys_membarrier) __SYSCALL(325, sys_mlock2) __SYSCALL(326, sys_copy_file_range) __SYSCALL(327, sys_ni_syscall) __SYSCALL(328, sys_ni_syscall) __SYSCALL(329, sys_pkey_mprotect) __SYSCALL(330, sys_pkey_alloc) __SYSCALL(331, sys_pkey_free) __SYSCALL(332, sys_statx) __SYSCALL(333, sys_io_pgetevents) __SYSCALL(334, sys_rseq) __SYSCALL(335, sys_ni_syscall) __SYSCALL(336, sys_ni_syscall) __SYSCALL(337, sys_ni_syscall) __SYSCALL(338, sys_ni_syscall) __SYSCALL(339, sys_ni_syscall) __SYSCALL(340, sys_ni_syscall) __SYSCALL(341, sys_ni_syscall) __SYSCALL(342, sys_ni_syscall) __SYSCALL(343, sys_ni_syscall) __SYSCALL(344, sys_ni_syscall) __SYSCALL(345, sys_ni_syscall) __SYSCALL(346, sys_ni_syscall) __SYSCALL(347, sys_ni_syscall) __SYSCALL(348, sys_ni_syscall) __SYSCALL(349, sys_ni_syscall) __SYSCALL(350, sys_ni_syscall) __SYSCALL(351, sys_ni_syscall) __SYSCALL(352, sys_ni_syscall) __SYSCALL(353, sys_ni_syscall) __SYSCALL(354, sys_ni_syscall) __SYSCALL(355, sys_ni_syscall) __SYSCALL(356, sys_ni_syscall) __SYSCALL(357, sys_ni_syscall) __SYSCALL(358, sys_ni_syscall) __SYSCALL(359, sys_ni_syscall) __SYSCALL(360, sys_ni_syscall) __SYSCALL(361, sys_ni_syscall) __SYSCALL(362, sys_ni_syscall) __SYSCALL(363, sys_ni_syscall) __SYSCALL(364, sys_ni_syscall) __SYSCALL(365, sys_ni_syscall) __SYSCALL(366, sys_ni_syscall) __SYSCALL(367, sys_ni_syscall) __SYSCALL(368, sys_ni_syscall) __SYSCALL(369, sys_ni_syscall) __SYSCALL(370, sys_ni_syscall) __SYSCALL(371, sys_ni_syscall) __SYSCALL(372, sys_ni_syscall) __SYSCALL(373, sys_ni_syscall) __SYSCALL(374, sys_ni_syscall) __SYSCALL(375, sys_ni_syscall) __SYSCALL(376, sys_ni_syscall) __SYSCALL(377, sys_ni_syscall) __SYSCALL(378, sys_ni_syscall) __SYSCALL(379, sys_ni_syscall) __SYSCALL(380, sys_ni_syscall) __SYSCALL(381, sys_ni_syscall) __SYSCALL(382, sys_ni_syscall) __SYSCALL(383, sys_ni_syscall) __SYSCALL(384, sys_ni_syscall) __SYSCALL(385, sys_ni_syscall) __SYSCALL(386, sys_ni_syscall) __SYSCALL(387, sys_ni_syscall) __SYSCALL(388, sys_ni_syscall) __SYSCALL(389, sys_ni_syscall) __SYSCALL(390, sys_ni_syscall) __SYSCALL(391, sys_ni_syscall) __SYSCALL(392, sys_ni_syscall) __SYSCALL(393, sys_ni_syscall) __SYSCALL(394, sys_ni_syscall) __SYSCALL(395, sys_ni_syscall) __SYSCALL(396, sys_ni_syscall) __SYSCALL(397, sys_ni_syscall) __SYSCALL(398, sys_ni_syscall) __SYSCALL(399, sys_ni_syscall) __SYSCALL(400, sys_ni_syscall) __SYSCALL(401, sys_ni_syscall) __SYSCALL(402, sys_ni_syscall) __SYSCALL(403, sys_ni_syscall) __SYSCALL(404, sys_ni_syscall) __SYSCALL(405, sys_ni_syscall) __SYSCALL(406, sys_ni_syscall) __SYSCALL(407, sys_ni_syscall) __SYSCALL(408, sys_ni_syscall) __SYSCALL(409, sys_ni_syscall) __SYSCALL(410, sys_ni_syscall) __SYSCALL(411, sys_ni_syscall) __SYSCALL(412, sys_ni_syscall) __SYSCALL(413, sys_ni_syscall) __SYSCALL(414, sys_ni_syscall) __SYSCALL(415, sys_ni_syscall) __SYSCALL(416, sys_ni_syscall) __SYSCALL(417, sys_ni_syscall) __SYSCALL(418, sys_ni_syscall) __SYSCALL(419, sys_ni_syscall) __SYSCALL(420, sys_ni_syscall) __SYSCALL(421, sys_ni_syscall) __SYSCALL(422, sys_ni_syscall) __SYSCALL(423, sys_ni_syscall) __SYSCALL(424, sys_pidfd_send_signal) __SYSCALL(425, sys_io_uring_setup) __SYSCALL(426, sys_io_uring_enter) __SYSCALL(427, sys_io_uring_register) __SYSCALL(428, sys_open_tree) __SYSCALL(429, sys_move_mount) __SYSCALL(430, sys_fsopen) __SYSCALL(431, sys_fsconfig) __SYSCALL(432, sys_fsmount) __SYSCALL(433, sys_fspick) __SYSCALL(434, sys_pidfd_open) __SYSCALL(435, sys_clone3) __SYSCALL(436, sys_close_range) __SYSCALL(437, sys_openat2) __SYSCALL(438, sys_pidfd_getfd) __SYSCALL(439, sys_faccessat2) __SYSCALL(440, sys_process_madvise) __SYSCALL(441, sys_epoll_pwait2) __SYSCALL(442, sys_mount_setattr) __SYSCALL(443, sys_quotactl_fd) __SYSCALL(444, sys_landlock_create_ruleset) __SYSCALL(445, sys_landlock_add_rule) __SYSCALL(446, sys_landlock_restrict_self) __SYSCALL(447, sys_memfd_secret) __SYSCALL(448, sys_process_mrelease) __SYSCALL(449, sys_ni_syscall) __SYSCALL(450, sys_ni_syscall) __SYSCALL(451, sys_ni_syscall) __SYSCALL(452, sys_ni_syscall) __SYSCALL(453, sys_ni_syscall) __SYSCALL(454, sys_ni_syscall) __SYSCALL(455, sys_ni_syscall) __SYSCALL(456, sys_ni_syscall) __SYSCALL(457, sys_ni_syscall) __SYSCALL(458, sys_ni_syscall) __SYSCALL(459, sys_ni_syscall) __SYSCALL(460, sys_ni_syscall) __SYSCALL(461, sys_ni_syscall) __SYSCALL(462, sys_ni_syscall) __SYSCALL(463, sys_ni_syscall) __SYSCALL(464, sys_ni_syscall) __SYSCALL(465, sys_ni_syscall) __SYSCALL(466, sys_ni_syscall) __SYSCALL(467, sys_ni_syscall) __SYSCALL(468, sys_ni_syscall) __SYSCALL(469, sys_ni_syscall) __SYSCALL(470, sys_ni_syscall) __SYSCALL(471, sys_ni_syscall) __SYSCALL(472, sys_ni_syscall) __SYSCALL(473, sys_ni_syscall) __SYSCALL(474, sys_ni_syscall) __SYSCALL(475, sys_ni_syscall) __SYSCALL(476, sys_ni_syscall) __SYSCALL(477, sys_ni_syscall) __SYSCALL(478, sys_ni_syscall) __SYSCALL(479, sys_ni_syscall) __SYSCALL(480, sys_ni_syscall) __SYSCALL(481, sys_ni_syscall) __SYSCALL(482, sys_ni_syscall) __SYSCALL(483, sys_ni_syscall) __SYSCALL(484, sys_ni_syscall) __SYSCALL(485, sys_ni_syscall) __SYSCALL(486, sys_ni_syscall) __SYSCALL(487, sys_ni_syscall) __SYSCALL(488, sys_ni_syscall) __SYSCALL(489, sys_ni_syscall) __SYSCALL(490, sys_ni_syscall) __SYSCALL(491, sys_ni_syscall) __SYSCALL(492, sys_ni_syscall) __SYSCALL(493, sys_ni_syscall) __SYSCALL(494, sys_ni_syscall) __SYSCALL(495, sys_ni_syscall) __SYSCALL(496, sys_ni_syscall) __SYSCALL(497, sys_ni_syscall) __SYSCALL(498, sys_ni_syscall) __SYSCALL(499, sys_ni_syscall) __SYSCALL(500, sys_ni_syscall) __SYSCALL(501, sys_ni_syscall) __SYSCALL(502, sys_ni_syscall) __SYSCALL(503, sys_ni_syscall) __SYSCALL(504, sys_ni_syscall) __SYSCALL(505, sys_ni_syscall) __SYSCALL(506, sys_ni_syscall) __SYSCALL(507, sys_ni_syscall) __SYSCALL(508, sys_ni_syscall) __SYSCALL(509, sys_ni_syscall) __SYSCALL(510, sys_ni_syscall) __SYSCALL(511, sys_ni_syscall) __SYSCALL(512, compat_sys_rt_sigaction) __SYSCALL(513, compat_sys_x32_rt_sigreturn) __SYSCALL(514, compat_sys_ioctl) __SYSCALL(515, sys_readv) __SYSCALL(516, sys_writev) __SYSCALL(517, compat_sys_recvfrom) __SYSCALL(518, compat_sys_sendmsg) __SYSCALL(519, compat_sys_recvmsg) __SYSCALL(520, compat_sys_execve) __SYSCALL(521, compat_sys_ptrace) __SYSCALL(522, compat_sys_rt_sigpending) __SYSCALL(523, compat_sys_rt_sigtimedwait_time64) __SYSCALL(524, compat_sys_rt_sigqueueinfo) __SYSCALL(525, compat_sys_sigaltstack) __SYSCALL(526, compat_sys_timer_create) __SYSCALL(527, compat_sys_mq_notify) __SYSCALL(528, compat_sys_kexec_load) __SYSCALL(529, compat_sys_waitid) __SYSCALL(530, compat_sys_set_robust_list) __SYSCALL(531, compat_sys_get_robust_list) __SYSCALL(532, sys_vmsplice) __SYSCALL(533, sys_move_pages) __SYSCALL(534, compat_sys_preadv64) __SYSCALL(535, compat_sys_pwritev64) __SYSCALL(536, compat_sys_rt_tgsigqueueinfo) __SYSCALL(537, compat_sys_recvmmsg_time64) __SYSCALL(538, compat_sys_sendmmsg) __SYSCALL(539, sys_process_vm_readv) __SYSCALL(540, sys_process_vm_writev) __SYSCALL(541, sys_setsockopt) __SYSCALL(542, sys_getsockopt) __SYSCALL(543, compat_sys_io_setup) __SYSCALL(544, compat_sys_io_submit) __SYSCALL(545, compat_sys_execveat) __SYSCALL(546, compat_sys_preadv64v2) __SYSCALL(547, compat_sys_pwritev64v2) PK ! �o�$ $ module.lds.hnu �[��� #include <asm-generic/module.lds.h> PK ! �͢�x x xen-hypercalls.hnu �[��� /* auto-generated by scripts/xen-hypercall.sh */ HYPERCALL(arch_1) HYPERCALL(arch_2) HYPERCALL(arch_3) HYPERCALL(arch_4) HYPERCALL(arch_5) HYPERCALL(arch_6) HYPERCALL(arch_7) HYPERCALL(callback_op) HYPERCALL(console_io) HYPERCALL(dm_op) HYPERCALL(domctl) HYPERCALL(event_channel_op) HYPERCALL(event_channel_op_compat) HYPERCALL(fpu_taskswitch) HYPERCALL(get_debugreg) HYPERCALL(grant_table_op) HYPERCALL(hvm_op) HYPERCALL(iret) HYPERCALL(kexec_op) HYPERCALL(mca) HYPERCALL(memory_op) HYPERCALL(mmu_update) HYPERCALL(mmuext_op) HYPERCALL(multicall) HYPERCALL(nmi_op) HYPERCALL(physdev_op) HYPERCALL(physdev_op_compat) HYPERCALL(platform_op) HYPERCALL(sched_op) HYPERCALL(sched_op_compat) HYPERCALL(set_callbacks) HYPERCALL(set_debugreg) HYPERCALL(set_gdt) HYPERCALL(set_segment_base) HYPERCALL(set_timer_op) HYPERCALL(set_trap_table) HYPERCALL(stack_switch) HYPERCALL(sysctl) HYPERCALL(tmem_op) HYPERCALL(update_descriptor) HYPERCALL(update_va_mapping) HYPERCALL(update_va_mapping_otherdomain) HYPERCALL(vcpu_op) HYPERCALL(vm_assist) HYPERCALL(xc_reserved_op) HYPERCALL(xen_version) HYPERCALL(xenoprof_op) HYPERCALL(xenpmu_op) HYPERCALL(xsm_op) PK ! ��� � mmu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_MMU_H #define __ALPHA_MMU_H /* The alpha MMU context is one "unsigned long" bitmap per CPU */ typedef unsigned long mm_context_t[NR_CPUS]; #endif PK ! c,� � special_insns.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_SPECIAL_INSNS_H #define __ALPHA_SPECIAL_INSNS_H enum implver_enum { IMPLVER_EV4, IMPLVER_EV5, IMPLVER_EV6 }; #ifdef CONFIG_ALPHA_GENERIC #define implver() \ ({ unsigned long __implver; \ __asm__ ("implver %0" : "=r"(__implver)); \ (enum implver_enum) __implver; }) #else /* Try to eliminate some dead code. */ #ifdef CONFIG_ALPHA_EV4 #define implver() IMPLVER_EV4 #endif #ifdef CONFIG_ALPHA_EV5 #define implver() IMPLVER_EV5 #endif #if defined(CONFIG_ALPHA_EV6) #define implver() IMPLVER_EV6 #endif #endif enum amask_enum { AMASK_BWX = (1UL << 0), AMASK_FIX = (1UL << 1), AMASK_CIX = (1UL << 2), AMASK_MAX = (1UL << 8), AMASK_PRECISE_TRAP = (1UL << 9), }; #define amask(mask) \ ({ unsigned long __amask, __input = (mask); \ __asm__ ("amask %1,%0" : "=r"(__amask) : "rI"(__input)); \ __amask; }) #endif /* __ALPHA_SPECIAL_INSNS_H */ PK ! w�� gct.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_GCT_H #define __ALPHA_GCT_H typedef u64 gct_id; typedef u64 gct6_handle; typedef struct __gct6_node { u8 type; u8 subtype; u16 size; u32 hd_extension; gct6_handle owner; gct6_handle active_user; gct_id id; u64 flags; u16 rev; u16 change_counter; u16 max_child; u16 reserved1; gct6_handle saved_owner; gct6_handle affinity; gct6_handle parent; gct6_handle next; gct6_handle prev; gct6_handle child; u64 fw_flags; u64 os_usage; u64 fru_id; u32 checksum; u32 magic; /* 'GLXY' */ } gct6_node; typedef struct { u8 type; u8 subtype; void (*callout)(gct6_node *); } gct6_search_struct; #define GCT_NODE_MAGIC 0x59584c47 /* 'GLXY' */ /* * node types */ #define GCT_TYPE_HOSE 0x0E /* * node subtypes */ #define GCT_SUBTYPE_IO_PORT_MODULE 0x2C #define GCT_NODE_PTR(off) ((gct6_node *)((char *)hwrpb + \ hwrpb->frut_offset + \ (gct6_handle)(off))) \ int gct6_find_nodes(gct6_node *, gct6_search_struct *); #endif /* __ALPHA_GCT_H */ PK ! na�� � pci.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_PCI_H #define __ALPHA_PCI_H #ifdef __KERNEL__ #include <linux/spinlock.h> #include <linux/dma-mapping.h> #include <linux/scatterlist.h> #include <asm/machvec.h> /* * The following structure is used to manage multiple PCI busses. */ struct pci_iommu_arena; struct page; /* A controller. Used to manage multiple PCI busses. */ struct pci_controller { struct pci_controller *next; struct pci_bus *bus; struct resource *io_space; struct resource *mem_space; /* The following are for reporting to userland. The invariant is that if we report a BWX-capable dense memory, we do not report a sparse memory at all, even if it exists. */ unsigned long sparse_mem_base; unsigned long dense_mem_base; unsigned long sparse_io_base; unsigned long dense_io_base; /* This one's for the kernel only. It's in KSEG somewhere. */ unsigned long config_space_base; unsigned int index; /* For compatibility with current (as of July 2003) pciutils and XFree86. Eventually will be removed. */ unsigned int need_domain_info; struct pci_iommu_arena *sg_pci; struct pci_iommu_arena *sg_isa; void *sysdata; }; /* Override the logic in pci_scan_bus for skipping already-configured bus numbers. */ #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO alpha_mv.min_io_address #define PCIBIOS_MIN_MEM alpha_mv.min_mem_address /* IOMMU controls. */ /* TODO: integrate with include/asm-generic/pci.h ? */ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return channel ? 15 : 14; } #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) { struct pci_controller *hose = bus->sysdata; return hose->need_domain_info; } #endif /* __KERNEL__ */ /* Values for the `which' argument to sys_pciconfig_iobase. */ #define IOBASE_HOSE 0 #define IOBASE_SPARSE_MEM 1 #define IOBASE_DENSE_MEM 2 #define IOBASE_SPARSE_IO 3 #define IOBASE_DENSE_IO 4 #define IOBASE_ROOT_BUS 5 #define IOBASE_FROM_HOSE 0x10000 extern struct pci_dev *isa_bridge; extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t count); extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t count); extern int pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, enum pci_mmap_state mmap_state); extern void pci_adjust_legacy_attr(struct pci_bus *bus, enum pci_mmap_state mmap_type); #define HAVE_PCI_LEGACY 1 extern int pci_create_resource_files(struct pci_dev *dev); extern void pci_remove_resource_files(struct pci_dev *dev); #endif /* __ALPHA_PCI_H */ PK ! �g`p div64.hnu �[��� #include <asm-generic/div64.h> PK ! ̶Iw� � cache.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * include/asm-alpha/cache.h */ #ifndef __ARCH_ALPHA_CACHE_H #define __ARCH_ALPHA_CACHE_H /* Bytes per L1 (data) cache line. */ #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6) # define L1_CACHE_BYTES 64 # define L1_CACHE_SHIFT 6 #else /* Both EV4 and EV5 are write-through, read-allocate, direct-mapped, physical. */ # define L1_CACHE_BYTES 32 # define L1_CACHE_SHIFT 5 #endif #define SMP_CACHE_BYTES L1_CACHE_BYTES #endif PK ! �+ � � extable.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_EXTABLE_H #define _ASM_EXTABLE_H /* * About the exception table: * * - insn is a 32-bit pc-relative offset from the faulting insn. * - nextinsn is a 16-bit offset off of the faulting instruction * (not off of the *next* instruction as branches are). * - errreg is the register in which to place -EFAULT. * - valreg is the final target register for the load sequence * and will be zeroed. * * Either errreg or valreg may be $31, in which case nothing happens. * * The exception fixup information "just so happens" to be arranged * as in a MEM format instruction. This lets us emit our three * values like so: * * lda valreg, nextinsn(errreg) * */ struct exception_table_entry { signed int insn; union exception_fixup { unsigned unit; struct { signed int nextinsn : 16; unsigned int errreg : 5; unsigned int valreg : 5; } bits; } fixup; }; /* Returns the new pc */ #define fixup_exception(map_reg, _fixup, pc) \ ({ \ if ((_fixup)->fixup.bits.valreg != 31) \ map_reg((_fixup)->fixup.bits.valreg) = 0; \ if ((_fixup)->fixup.bits.errreg != 31) \ map_reg((_fixup)->fixup.bits.errreg) = -EFAULT; \ (pc) + (_fixup)->fixup.bits.nextinsn; \ }) #define ARCH_HAS_RELATIVE_EXTABLE #define swap_ex_entry_fixup(a, b, tmp, delta) \ do { \ (a)->fixup.unit = (b)->fixup.unit; \ (b)->fixup.unit = (tmp).fixup.unit; \ } while (0) #endif PK ! 8�7 ` ` word-at-a-time.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_WORD_AT_A_TIME_H #define _ASM_WORD_AT_A_TIME_H #include <asm/compiler.h> /* * word-at-a-time interface for Alpha. */ /* * We do not use the word_at_a_time struct on Alpha, but it needs to be * implemented to humour the generic code. */ struct word_at_a_time { const unsigned long unused; }; #define WORD_AT_A_TIME_CONSTANTS { 0 } /* Return nonzero if val has a zero */ static inline unsigned long has_zero(unsigned long val, unsigned long *bits, const struct word_at_a_time *c) { unsigned long zero_locations = __kernel_cmpbge(0, val); *bits = zero_locations; return zero_locations; } static inline unsigned long prep_zero_mask(unsigned long val, unsigned long bits, const struct word_at_a_time *c) { return bits; } #define create_zero_mask(bits) (bits) static inline unsigned long find_zero(unsigned long bits) { #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67) /* Simple if have CIX instructions */ return __kernel_cttz(bits); #else unsigned long t1, t2, t3; /* Retain lowest set bit only */ bits &= -bits; /* Binary search for lowest set bit */ t1 = bits & 0xf0; t2 = bits & 0xcc; t3 = bits & 0xaa; if (t1) t1 = 4; if (t2) t2 = 2; if (t3) t3 = 1; return t1 + t2 + t3; #endif } #define zero_bytemask(mask) ((2ul << (find_zero(mask) * 8)) - 1) #endif /* _ASM_WORD_AT_A_TIME_H */ PK ! �y|� � shmparam.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASMAXP_SHMPARAM_H #define _ASMAXP_SHMPARAM_H #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ #endif /* _ASMAXP_SHMPARAM_H */ PK ! ��B� percpu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_PERCPU_H #define __ALPHA_PERCPU_H /* * To calculate addresses of locally defined variables, GCC uses * 32-bit displacement from the GP. Which doesn't work for per cpu * variables in modules, as an offset to the kernel per cpu area is * way above 4G. * * Always use weak definitions for percpu variables in modules. */ #if defined(MODULE) && defined(CONFIG_SMP) #define ARCH_NEEDS_WEAK_PER_CPU #endif #include <asm-generic/percpu.h> #endif /* __ALPHA_PERCPU_H */ PK ! 3��� � cacheflush.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_CACHEFLUSH_H #define _ALPHA_CACHEFLUSH_H #include <linux/mm.h> /* Note that the following two definitions are _highly_ dependent on the contexts in which they are used in the kernel. I personally think it is criminal how loosely defined these macros are. */ /* We need to flush the kernel's icache after loading modules. The only other use of this macro is in load_aout_interp which is not used on Alpha. Note that this definition should *not* be used for userspace icache flushing. While functional, it is _way_ overkill. The icache is tagged with ASNs and it suffices to allocate a new ASN for the process. */ #ifndef CONFIG_SMP #define flush_icache_range(start, end) imb() #else #define flush_icache_range(start, end) smp_imb() extern void smp_imb(void); #endif /* We need to flush the userspace icache after setting breakpoints in ptrace. Instead of indiscriminately using imb, take advantage of the fact that icache entries are tagged with the ASN and load a new mm context. */ /* ??? Ought to use this in arch/alpha/kernel/signal.c too. */ #ifndef CONFIG_SMP #include <linux/sched.h> extern void __load_new_mm_context(struct mm_struct *); static inline void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, unsigned long addr, int len) { if (vma->vm_flags & VM_EXEC) { struct mm_struct *mm = vma->vm_mm; if (current->active_mm == mm) __load_new_mm_context(mm); else mm->context[smp_processor_id()] = 0; } } #define flush_icache_user_page flush_icache_user_page #else /* CONFIG_SMP */ extern void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, unsigned long addr, int len); #define flush_icache_user_page flush_icache_user_page #endif /* CONFIG_SMP */ /* This is used only in __do_fault and do_swap_page. */ #define flush_icache_page(vma, page) \ flush_icache_user_page((vma), (page), 0, 0) #include <asm-generic/cacheflush.h> #endif /* _ALPHA_CACHEFLUSH_H */ PK ! TgR ] ] vmalloc.hnu �[��� #ifndef _ASM_ALPHA_VMALLOC_H #define _ASM_ALPHA_VMALLOC_H #endif /* _ASM_ALPHA_VMALLOC_H */ PK ! �+x* parport.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * parport.h: platform-specific PC-style parport initialisation * * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> * * This file should only be included by drivers/parport/parport_pc.c. */ #ifndef _ASM_AXP_PARPORT_H #define _ASM_AXP_PARPORT_H 1 static int parport_pc_find_isa_ports (int autoirq, int autodma); static int parport_pc_find_nonpci_ports (int autoirq, int autodma) { return parport_pc_find_isa_ports (autoirq, autodma); } #endif /* !(_ASM_AXP_PARPORT_H) */ PK ! 4rH��$ �$ core_marvel.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Marvel systems use the IO7 I/O chip provides PCI/PCIX/AGP access * * This file is based on: * * Marvel / EV7 System Programmer's Manual * Revision 1.00 * 14 May 2001 */ #ifndef __ALPHA_MARVEL__H__ #define __ALPHA_MARVEL__H__ #include <linux/types.h> #include <linux/spinlock.h> #include <asm/compiler.h> #define MARVEL_MAX_PIDS 32 /* as long as we rely on 43-bit superpage */ #define MARVEL_IRQ_VEC_PE_SHIFT (10) #define MARVEL_IRQ_VEC_IRQ_MASK ((1 << MARVEL_IRQ_VEC_PE_SHIFT) - 1) #define MARVEL_NR_IRQS \ (16 + (MARVEL_MAX_PIDS * (1 << MARVEL_IRQ_VEC_PE_SHIFT))) /* * EV7 RBOX Registers */ typedef struct { volatile unsigned long csr __attribute__((aligned(16))); } ev7_csr; typedef struct { ev7_csr RBOX_CFG; /* 0x0000 */ ev7_csr RBOX_NSVC; ev7_csr RBOX_EWVC; ev7_csr RBOX_WHAMI; ev7_csr RBOX_TCTL; /* 0x0040 */ ev7_csr RBOX_INT; ev7_csr RBOX_IMASK; ev7_csr RBOX_IREQ; ev7_csr RBOX_INTQ; /* 0x0080 */ ev7_csr RBOX_INTA; ev7_csr RBOX_IT; ev7_csr RBOX_SCRATCH1; ev7_csr RBOX_SCRATCH2; /* 0x00c0 */ ev7_csr RBOX_L_ERR; } ev7_csrs; /* * EV7 CSR addressing macros */ #define EV7_MASK40(addr) ((addr) & ((1UL << 41) - 1)) #define EV7_KERN_ADDR(addr) ((void *)(IDENT_ADDR | EV7_MASK40(addr))) #define EV7_PE_MASK 0x1ffUL /* 9 bits ( 256 + mem/io ) */ #define EV7_IPE(pe) ((~((long)(pe)) & EV7_PE_MASK) << 35) #define EV7_CSR_PHYS(pe, off) (EV7_IPE(pe) | (0x7FFCUL << 20) | (off)) #define EV7_CSRS_PHYS(pe) (EV7_CSR_PHYS(pe, 0UL)) #define EV7_CSR_KERN(pe, off) (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off))) #define EV7_CSRS_KERN(pe) (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe))) #define EV7_CSR_OFFSET(name) ((unsigned long)&((ev7_csrs *)NULL)->name.csr) /* * IO7 registers */ typedef struct { volatile unsigned long csr __attribute__((aligned(64))); } io7_csr; typedef struct { /* I/O Port Control Registers */ io7_csr POx_CTRL; /* 0x0000 */ io7_csr POx_CACHE_CTL; io7_csr POx_TIMER; io7_csr POx_IO_ADR_EXT; io7_csr POx_MEM_ADR_EXT; /* 0x0100 */ io7_csr POx_XCAL_CTRL; io7_csr rsvd1[2]; /* ?? spec doesn't show 0x180 */ io7_csr POx_DM_SOURCE; /* 0x0200 */ io7_csr POx_DM_DEST; io7_csr POx_DM_SIZE; io7_csr POx_DM_CTRL; io7_csr rsvd2[4]; /* 0x0300 */ /* AGP Control Registers -- port 3 only */ io7_csr AGP_CAP_ID; /* 0x0400 */ io7_csr AGP_STAT; io7_csr AGP_CMD; io7_csr rsvd3; /* I/O Port Monitor Registers */ io7_csr POx_MONCTL; /* 0x0500 */ io7_csr POx_CTRA; io7_csr POx_CTRB; io7_csr POx_CTR56; io7_csr POx_SCRATCH; /* 0x0600 */ io7_csr POx_XTRA_A; io7_csr POx_XTRA_TS; io7_csr POx_XTRA_Z; io7_csr rsvd4; /* 0x0700 */ io7_csr POx_THRESHA; io7_csr POx_THRESHB; io7_csr rsvd5[33]; /* System Address Space Window Control Registers */ io7_csr POx_WBASE[4]; /* 0x1000 */ io7_csr POx_WMASK[4]; io7_csr POx_TBASE[4]; io7_csr POx_SG_TBIA; io7_csr POx_MSI_WBASE; io7_csr rsvd6[50]; /* I/O Port Error Registers */ io7_csr POx_ERR_SUM; io7_csr POx_FIRST_ERR; io7_csr POx_MSK_HEI; io7_csr POx_TLB_ERR; io7_csr POx_SPL_COMPLT; io7_csr POx_TRANS_SUM; io7_csr POx_FRC_PCI_ERR; io7_csr POx_MULT_ERR; io7_csr rsvd7[8]; /* I/O Port End of Interrupt Registers */ io7_csr EOI_DAT; io7_csr rsvd8[7]; io7_csr POx_IACK_SPECIAL; io7_csr rsvd9[103]; } io7_ioport_csrs; typedef struct { io7_csr IO_ASIC_REV; /* 0x30.0000 */ io7_csr IO_SYS_REV; io7_csr SER_CHAIN3; io7_csr PO7_RST1; io7_csr PO7_RST2; /* 0x30.0100 */ io7_csr POx_RST[4]; io7_csr IO7_DWNH; io7_csr IO7_MAF; io7_csr IO7_MAF_TO; io7_csr IO7_ACC_CLUMP; /* 0x30.0300 */ io7_csr IO7_PMASK; io7_csr IO7_IOMASK; io7_csr IO7_UPH; io7_csr IO7_UPH_TO; /* 0x30.0400 */ io7_csr RBX_IREQ_OFF; io7_csr RBX_INTA_OFF; io7_csr INT_RTY; io7_csr PO7_MONCTL; /* 0x30.0500 */ io7_csr PO7_CTRA; io7_csr PO7_CTRB; io7_csr PO7_CTR56; io7_csr PO7_SCRATCH; /* 0x30.0600 */ io7_csr PO7_XTRA_A; io7_csr PO7_XTRA_TS; io7_csr PO7_XTRA_Z; io7_csr PO7_PMASK; /* 0x30.0700 */ io7_csr PO7_THRESHA; io7_csr PO7_THRESHB; io7_csr rsvd1[97]; io7_csr PO7_ERROR_SUM; /* 0x30.2000 */ io7_csr PO7_BHOLE_MASK; io7_csr PO7_HEI_MSK; io7_csr PO7_CRD_MSK; io7_csr PO7_UNCRR_SYM; /* 0x30.2100 */ io7_csr PO7_CRRCT_SYM; io7_csr PO7_ERR_PKT[2]; io7_csr PO7_UGBGE_SYM; /* 0x30.2200 */ io7_csr rsbv2[887]; io7_csr PO7_LSI_CTL[128]; /* 0x31.0000 */ io7_csr rsvd3[123]; io7_csr HLT_CTL; /* 0x31.3ec0 */ io7_csr HPI_CTL; /* 0x31.3f00 */ io7_csr CRD_CTL; io7_csr STV_CTL; io7_csr HEI_CTL; io7_csr PO7_MSI_CTL[16]; /* 0x31.4000 */ io7_csr rsvd4[240]; /* * Interrupt Diagnostic / Test */ struct { io7_csr INT_PND; io7_csr INT_CLR; io7_csr INT_EOI; io7_csr rsvd[29]; } INT_DIAG[4]; io7_csr rsvd5[125]; /* 0x31.a000 */ io7_csr MISC_PND; /* 0x31.b800 */ io7_csr rsvd6[31]; io7_csr MSI_PND[16]; /* 0x31.c000 */ io7_csr rsvd7[16]; io7_csr MSI_CLR[16]; /* 0x31.c800 */ } io7_port7_csrs; /* * IO7 DMA Window Base register (POx_WBASEx) */ #define wbase_m_ena 0x1 #define wbase_m_sg 0x2 #define wbase_m_dac 0x4 #define wbase_m_addr 0xFFF00000 union IO7_POx_WBASE { struct { unsigned ena : 1; /* <0> */ unsigned sg : 1; /* <1> */ unsigned dac : 1; /* <2> -- window 3 only */ unsigned rsvd1 : 17; unsigned addr : 12; /* <31:20> */ unsigned rsvd2 : 32; } bits; unsigned as_long[2]; unsigned as_quad; }; /* * IO7 IID (Interrupt IDentifier) format * * For level-sensative interrupts, int_num is encoded as: * * bus/port slot/device INTx * <7:5> <4:2> <1:0> */ union IO7_IID { struct { unsigned int_num : 9; /* <8:0> */ unsigned tpu_mask : 4; /* <12:9> rsvd */ unsigned msi : 1; /* 13 */ unsigned ipe : 10; /* <23:14> */ unsigned long rsvd : 40; } bits; unsigned int as_long[2]; unsigned long as_quad; }; /* * IO7 addressing macros */ #define IO7_KERN_ADDR(addr) (EV7_KERN_ADDR(addr)) #define IO7_PORT_MASK 0x07UL /* 3 bits of port */ #define IO7_IPE(pe) (EV7_IPE(pe)) #define IO7_IPORT(port) ((~((long)(port)) & IO7_PORT_MASK) << 32) #define IO7_HOSE(pe, port) (IO7_IPE(pe) | IO7_IPORT(port)) #define IO7_MEM_PHYS(pe, port) (IO7_HOSE(pe, port) | 0x00000000UL) #define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL) #define IO7_IO_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFF000000UL) #define IO7_CSR_PHYS(pe, port, off) \ (IO7_HOSE(pe, port) | 0xFF800000UL | (off)) #define IO7_CSRS_PHYS(pe, port) (IO7_CSR_PHYS(pe, port, 0UL)) #define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL)) #define IO7_MEM_KERN(pe, port) (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port))) #define IO7_CONF_KERN(pe, port) (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port))) #define IO7_IO_KERN(pe, port) (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port))) #define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off))) #define IO7_CSRS_KERN(pe, port) (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port))) #define IO7_PORT7_CSRS_KERN(pe) (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe))) #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7) #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7) #define IO7_MEM_SPACE (2UL * 1024 * 1024 * 1024) /* 2GB MEM */ #define IO7_IO_SPACE (8UL * 1024 * 1024) /* 8MB I/O */ /* * Offset between ram physical addresses and pci64 DAC addresses */ #define IO7_DAC_OFFSET (1UL << 49) /* * This is needed to satisify the IO() macro used in initializing the machvec */ #define MARVEL_IACK_SC \ ((unsigned long) \ (&(((io7_ioport_csrs *)IO7_CSRS_KERN(0, 0))->POx_IACK_SPECIAL))) #ifdef __KERNEL__ /* * IO7 structs */ #define IO7_NUM_PORTS 4 #define IO7_AGP_PORT 3 struct io7_port { struct io7 *io7; struct pci_controller *hose; int enabled; unsigned int port; io7_ioport_csrs *csrs; unsigned long saved_wbase[4]; unsigned long saved_wmask[4]; unsigned long saved_tbase[4]; }; struct io7 { struct io7 *next; unsigned int pe; io7_port7_csrs *csrs; struct io7_port ports[IO7_NUM_PORTS]; raw_spinlock_t irq_lock; }; #ifndef __EXTERN_INLINE # define __EXTERN_INLINE extern inline # define __IO_EXTERN_INLINE #endif /* * I/O functions. All access through linear space. */ /* * Memory functions. All accesses through linear space. */ #define vucp volatile unsigned char __force * #define vusp volatile unsigned short __force * extern unsigned int marvel_ioread8(const void __iomem *); extern void marvel_iowrite8(u8 b, void __iomem *); __EXTERN_INLINE unsigned int marvel_ioread16(const void __iomem *addr) { return __kernel_ldwu(*(vusp)addr); } __EXTERN_INLINE void marvel_iowrite16(u16 b, void __iomem *addr) { __kernel_stw(b, *(vusp)addr); } extern void __iomem *marvel_ioremap(unsigned long addr, unsigned long size); extern void marvel_iounmap(volatile void __iomem *addr); extern void __iomem *marvel_ioportmap (unsigned long addr); __EXTERN_INLINE int marvel_is_ioaddr(unsigned long addr) { return (addr >> 40) & 1; } extern int marvel_is_mmio(const volatile void __iomem *); #undef vucp #undef vusp #undef __IO_PREFIX #define __IO_PREFIX marvel #define marvel_trivial_rw_bw 1 #define marvel_trivial_rw_lq 1 #define marvel_trivial_io_bw 0 #define marvel_trivial_io_lq 1 #define marvel_trivial_iounmap 0 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE # undef __EXTERN_INLINE # undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_MARVEL__H__ */ PK ! ȵ�� � io_trivial.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* Trivial implementations of basic i/o routines. Assumes that all of the hard work has been done by ioremap and ioportmap, and that access to i/o space is linear. */ /* This file may be included multiple times. */ #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) __EXTERN_INLINE unsigned int IO_CONCAT(__IO_PREFIX,ioread8)(const void __iomem *a) { return __kernel_ldbu(*(const volatile u8 __force *)a); } __EXTERN_INLINE unsigned int IO_CONCAT(__IO_PREFIX,ioread16)(const void __iomem *a) { return __kernel_ldwu(*(const volatile u16 __force *)a); } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,iowrite8)(u8 b, void __iomem *a) { __kernel_stb(b, *(volatile u8 __force *)a); } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,iowrite16)(u16 b, void __iomem *a) { __kernel_stw(b, *(volatile u16 __force *)a); } #endif #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) __EXTERN_INLINE unsigned int IO_CONCAT(__IO_PREFIX,ioread32)(const void __iomem *a) { return *(const volatile u32 __force *)a; } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,iowrite32)(u32 b, void __iomem *a) { *(volatile u32 __force *)a = b; } #endif #if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1 __EXTERN_INLINE u8 IO_CONCAT(__IO_PREFIX,readb)(const volatile void __iomem *a) { return __kernel_ldbu(*(const volatile u8 __force *)a); } __EXTERN_INLINE u16 IO_CONCAT(__IO_PREFIX,readw)(const volatile void __iomem *a) { return __kernel_ldwu(*(const volatile u16 __force *)a); } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,writeb)(u8 b, volatile void __iomem *a) { __kernel_stb(b, *(volatile u8 __force *)a); } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a) { __kernel_stw(b, *(volatile u16 __force *)a); } #elif IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 2 __EXTERN_INLINE u8 IO_CONCAT(__IO_PREFIX,readb)(const volatile void __iomem *a) { const void __iomem *addr = (const void __iomem *)a; return IO_CONCAT(__IO_PREFIX,ioread8)(addr); } __EXTERN_INLINE u16 IO_CONCAT(__IO_PREFIX,readw)(const volatile void __iomem *a) { const void __iomem *addr = (const void __iomem *)a; return IO_CONCAT(__IO_PREFIX,ioread16)(addr); } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,writeb)(u8 b, volatile void __iomem *a) { void __iomem *addr = (void __iomem *)a; IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr); } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a) { void __iomem *addr = (void __iomem *)a; IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr); } #endif #if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1 __EXTERN_INLINE u32 IO_CONCAT(__IO_PREFIX,readl)(const volatile void __iomem *a) { return *(const volatile u32 __force *)a; } __EXTERN_INLINE u64 IO_CONCAT(__IO_PREFIX,readq)(const volatile void __iomem *a) { return *(const volatile u64 __force *)a; } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,writel)(u32 b, volatile void __iomem *a) { *(volatile u32 __force *)a = b; } __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,writeq)(u64 b, volatile void __iomem *a) { *(volatile u64 __force *)a = b; } #endif #if IO_CONCAT(__IO_PREFIX,trivial_iounmap) __EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,iounmap)(volatile void __iomem *a) { } #endif PK ! �Ͻ�a a smp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SMP_H #define __ASM_SMP_H #include <linux/threads.h> #include <linux/cpumask.h> #include <linux/bitops.h> #include <asm/pal.h> /* HACK: Cabrio WHAMI return value is bogus if more than 8 bits used.. :-( */ static __inline__ unsigned char __hard_smp_processor_id(void) { register unsigned char __r0 __asm__("$0"); __asm__ __volatile__( "call_pal %1 #whami" : "=r"(__r0) :"i" (PAL_whami) : "$1", "$22", "$23", "$24", "$25"); return __r0; } #ifdef CONFIG_SMP #include <asm/irq.h> struct cpuinfo_alpha { unsigned long loops_per_jiffy; unsigned long last_asn; int need_new_asn; int asn_lock; unsigned long ipi_count; unsigned long prof_multiplier; unsigned long prof_counter; unsigned char mcheck_expected; unsigned char mcheck_taken; unsigned char mcheck_extra; } __attribute__((aligned(64))); extern struct cpuinfo_alpha cpu_data[NR_CPUS]; #define hard_smp_processor_id() __hard_smp_processor_id() #define raw_smp_processor_id() (current_thread_info()->cpu) extern int smp_num_cpus; extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); #else /* CONFIG_SMP */ #define hard_smp_processor_id() 0 #define smp_call_function_on_cpu(func,info,wait,cpu) ({ 0; }) #endif /* CONFIG_SMP */ #define NO_PROC_ID (-1) #endif PK ! o�4P� � asm-prototypes.hnu �[��� #include <linux/spinlock.h> #include <asm/checksum.h> #include <asm/console.h> #include <asm/page.h> #include <asm/string.h> #include <linux/uaccess.h> #include <asm-generic/asm-prototypes.h> extern void __divl(void); extern void __reml(void); extern void __divq(void); extern void __remq(void); extern void __divlu(void); extern void __remlu(void); extern void __divqu(void); extern void __remqu(void); extern unsigned long __udiv_qrnnd(unsigned long *, unsigned long, unsigned long , unsigned long); PK ! h�` ` tlbflush.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_TLBFLUSH_H #define _ALPHA_TLBFLUSH_H #include <linux/mm.h> #include <linux/sched.h> #include <asm/compiler.h> #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __MMU_EXTERN_INLINE #endif extern void __load_new_mm_context(struct mm_struct *); /* Use a few helper functions to hide the ugly broken ASN numbers on early Alphas (ev4 and ev45). */ __EXTERN_INLINE void ev4_flush_tlb_current(struct mm_struct *mm) { __load_new_mm_context(mm); tbiap(); } __EXTERN_INLINE void ev5_flush_tlb_current(struct mm_struct *mm) { __load_new_mm_context(mm); } /* Flush just one page in the current TLB set. We need to be very careful about the icache here, there is no way to invalidate a specific icache page. */ __EXTERN_INLINE void ev4_flush_tlb_current_page(struct mm_struct * mm, struct vm_area_struct *vma, unsigned long addr) { int tbi_flag = 2; if (vma->vm_flags & VM_EXEC) { __load_new_mm_context(mm); tbi_flag = 3; } tbi(tbi_flag, addr); } __EXTERN_INLINE void ev5_flush_tlb_current_page(struct mm_struct * mm, struct vm_area_struct *vma, unsigned long addr) { if (vma->vm_flags & VM_EXEC) __load_new_mm_context(mm); else tbi(2, addr); } #ifdef CONFIG_ALPHA_GENERIC # define flush_tlb_current alpha_mv.mv_flush_tlb_current # define flush_tlb_current_page alpha_mv.mv_flush_tlb_current_page #else # ifdef CONFIG_ALPHA_EV4 # define flush_tlb_current ev4_flush_tlb_current # define flush_tlb_current_page ev4_flush_tlb_current_page # else # define flush_tlb_current ev5_flush_tlb_current # define flush_tlb_current_page ev5_flush_tlb_current_page # endif #endif #ifdef __MMU_EXTERN_INLINE #undef __EXTERN_INLINE #undef __MMU_EXTERN_INLINE #endif /* Flush current user mapping. */ static inline void flush_tlb(void) { flush_tlb_current(current->active_mm); } /* Flush someone else's user mapping. */ static inline void flush_tlb_other(struct mm_struct *mm) { unsigned long *mmc = &mm->context[smp_processor_id()]; /* Check it's not zero first to avoid cacheline ping pong when possible. */ if (*mmc) *mmc = 0; } #ifndef CONFIG_SMP /* Flush everything (kernel mapping may also have changed due to vmalloc/vfree). */ static inline void flush_tlb_all(void) { tbia(); } /* Flush a specified user mapping. */ static inline void flush_tlb_mm(struct mm_struct *mm) { if (mm == current->active_mm) flush_tlb_current(mm); else flush_tlb_other(mm); } /* Page-granular tlb flush. */ static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { struct mm_struct *mm = vma->vm_mm; if (mm == current->active_mm) flush_tlb_current_page(mm, vma, addr); else flush_tlb_other(mm); } /* Flush a specified range of user mapping. On the Alpha we flush the whole user tlb. */ static inline void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { flush_tlb_mm(vma->vm_mm); } #else /* CONFIG_SMP */ extern void flush_tlb_all(void); extern void flush_tlb_mm(struct mm_struct *); extern void flush_tlb_page(struct vm_area_struct *, unsigned long); extern void flush_tlb_range(struct vm_area_struct *, unsigned long, unsigned long); #endif /* CONFIG_SMP */ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { flush_tlb_all(); } #endif /* _ALPHA_TLBFLUSH_H */ PK ! JYߓ� � mc146818rtc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Machine dependent access functions for RTC registers. */ #ifndef __ASM_ALPHA_MC146818RTC_H #define __ASM_ALPHA_MC146818RTC_H #include <asm/io.h> #ifndef RTC_PORT #define RTC_PORT(x) (0x70 + (x)) #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ #endif /* * The yet supported machines all access the RTC index register via * an ISA port access but the way to access the date register differs ... */ #define CMOS_READ(addr) ({ \ outb_p((addr),RTC_PORT(0)); \ inb_p(RTC_PORT(1)); \ }) #define CMOS_WRITE(val, addr) ({ \ outb_p((addr),RTC_PORT(0)); \ outb_p((val),RTC_PORT(1)); \ }) #endif /* __ASM_ALPHA_MC146818RTC_H */ PK ! OW*< tlb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_TLB_H #define _ALPHA_TLB_H #include <asm-generic/tlb.h> #define __pte_free_tlb(tlb, pte, address) pte_free((tlb)->mm, pte) #define __pmd_free_tlb(tlb, pmd, address) pmd_free((tlb)->mm, pmd) #endif PK ! ��a�t t err_ev6.hnu �[��� #ifndef __ALPHA_ERR_EV6_H #define __ALPHA_ERR_EV6_H 1 /* Dummy include for now. */ #endif /* __ALPHA_ERR_EV6_H */ PK ! ��{� � thread_info.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_THREAD_INFO_H #define _ALPHA_THREAD_INFO_H #ifdef __KERNEL__ #ifndef __ASSEMBLY__ #include <asm/processor.h> #include <asm/types.h> #include <asm/hwrpb.h> #include <asm/sysinfo.h> #endif #ifndef __ASSEMBLY__ struct thread_info { struct pcb_struct pcb; /* palcode state */ struct task_struct *task; /* main task structure */ unsigned int flags; /* low level flags */ unsigned int ieee_state; /* see fpu.h */ mm_segment_t addr_limit; /* thread address space */ unsigned cpu; /* current CPU */ int preempt_count; /* 0 => preemptable, <0 => BUG */ unsigned int status; /* thread-synchronous flags */ int bpt_nsaved; unsigned long bpt_addr[2]; /* breakpoint handling */ unsigned int bpt_insn[2]; }; /* * Macros/functions for gaining access to the thread information structure. */ #define INIT_THREAD_INFO(tsk) \ { \ .task = &tsk, \ .addr_limit = KERNEL_DS, \ .preempt_count = INIT_PREEMPT_COUNT, \ } /* How to get the thread information struct from C. */ register struct thread_info *__current_thread_info __asm__("$8"); #define current_thread_info() __current_thread_info #endif /* __ASSEMBLY__ */ /* Thread information allocation. */ #define THREAD_SIZE_ORDER 1 #define THREAD_SIZE (2*PAGE_SIZE) /* * Thread information flags: * - these are process state flags and used from assembly * - pending work-to-be-done flags come first and must be assigned to be * within bits 0 to 7 to fit in and immediate operand. * * TIF_SYSCALL_TRACE is known to be 0 via blbs. */ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_NOTIFY_RESUME 1 /* callback before returning to user */ #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_SYSCALL_AUDIT 4 /* syscall audit active */ #define TIF_NOTIFY_SIGNAL 5 /* signal notifications exist */ #define TIF_DIE_IF_KERNEL 9 /* dik recursion lock */ #define TIF_MEMDIE 13 /* is terminating due to OOM killer */ #define TIF_POLLING_NRFLAG 14 /* idle is polling for TIF_NEED_RESCHED */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) #define _TIF_NOTIFY_SIGNAL (1<<TIF_NOTIFY_SIGNAL) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) /* Work to do on interrupt/exception return. */ #define _TIF_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \ _TIF_NOTIFY_RESUME | _TIF_NOTIFY_SIGNAL) /* Work to do on any return to userspace. */ #define _TIF_ALLWORK_MASK (_TIF_WORK_MASK \ | _TIF_SYSCALL_TRACE) #define TS_UAC_NOPRINT 0x0001 /* ! Preserve the following three */ #define TS_UAC_NOFIX 0x0002 /* ! flags as they match */ #define TS_UAC_SIGBUS 0x0004 /* ! userspace part of 'osf_sysinfo' */ #define SET_UNALIGN_CTL(task,value) ({ \ __u32 status = task_thread_info(task)->status & ~UAC_BITMASK; \ if (value & PR_UNALIGN_NOPRINT) \ status |= TS_UAC_NOPRINT; \ if (value & PR_UNALIGN_SIGBUS) \ status |= TS_UAC_SIGBUS; \ if (value & 4) /* alpha-specific */ \ status |= TS_UAC_NOFIX; \ task_thread_info(task)->status = status; \ 0; }) #define GET_UNALIGN_CTL(task,value) ({ \ __u32 status = task_thread_info(task)->status & ~UAC_BITMASK; \ __u32 res = 0; \ if (status & TS_UAC_NOPRINT) \ res |= PR_UNALIGN_NOPRINT; \ if (status & TS_UAC_SIGBUS) \ res |= PR_UNALIGN_SIGBUS; \ if (status & TS_UAC_NOFIX) \ res |= 4; \ put_user(res, (int __user *)(value)); \ }) #endif /* __KERNEL__ */ #endif /* _ALPHA_THREAD_INFO_H */ PK ! �� ̍ � processor.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * include/asm-alpha/processor.h * * Copyright (C) 1994 Linus Torvalds */ #ifndef __ASM_ALPHA_PROCESSOR_H #define __ASM_ALPHA_PROCESSOR_H /* * We have a 42-bit user address space: 4TB user VM... */ #define TASK_SIZE (0x40000000000UL) #define STACK_TOP (0x00120000000UL) #define STACK_TOP_MAX 0x00120000000UL /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ #define TASK_UNMAPPED_BASE (TASK_SIZE / 2) typedef struct { unsigned long seg; } mm_segment_t; /* This is dead. Everything has been moved to thread_info. */ struct thread_struct { }; #define INIT_THREAD { } /* Do necessary setup to start up a newly executed thread. */ struct pt_regs; extern void start_thread(struct pt_regs *, unsigned long, unsigned long); /* Free all resources held by a thread. */ struct task_struct; extern void release_thread(struct task_struct *); unsigned long __get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) #define KSTK_ESP(tsk) \ ((tsk) == current ? rdusp() : task_thread_info(tsk)->pcb.usp) #define cpu_relax() barrier() #define ARCH_HAS_PREFETCH #define ARCH_HAS_PREFETCHW #define ARCH_HAS_SPINLOCK_PREFETCH #ifndef CONFIG_SMP /* Nothing to prefetch. */ #define spin_lock_prefetch(lock) do { } while (0) #endif extern inline void prefetch(const void *ptr) { __builtin_prefetch(ptr, 0, 3); } extern inline void prefetchw(const void *ptr) { __builtin_prefetch(ptr, 1, 3); } #ifdef CONFIG_SMP extern inline void spin_lock_prefetch(const void *ptr) { __builtin_prefetch(ptr, 1, 3); } #endif #endif /* __ASM_ALPHA_PROCESSOR_H */ PK ! ���q q sfp-machine.hnu �[��� /* Machine-dependent software floating-point definitions. Alpha kernel version. Copyright (C) 1997,1998,1999 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Richard Henderson (rth@cygnus.com), Jakub Jelinek (jakub@redhat.com) and David S. Miller (davem@redhat.com). The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with the GNU C Library; see the file COPYING.LIB. If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _SFP_MACHINE_H #define _SFP_MACHINE_H #define _FP_W_TYPE_SIZE 64 #define _FP_W_TYPE unsigned long #define _FP_WS_TYPE signed long #define _FP_I_TYPE long #define _FP_MUL_MEAT_S(R,X,Y) \ _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y) #define _FP_MUL_MEAT_D(R,X,Y) \ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) #define _FP_MUL_MEAT_Q(R,X,Y) \ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) #define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm) #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv(D,R,X,Y) #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) #define _FP_NANFRAC_S _FP_QNANBIT_S #define _FP_NANFRAC_D _FP_QNANBIT_D #define _FP_NANFRAC_Q _FP_QNANBIT_Q #define _FP_NANSIGN_S 1 #define _FP_NANSIGN_D 1 #define _FP_NANSIGN_Q 1 #define _FP_KEEPNANFRACP 1 /* Alpha Architecture Handbook, 4.7.10.4 sais that * we should prefer any type of NaN in Fb, then Fa. */ #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ do { \ R##_s = Y##_s; \ _FP_FRAC_COPY_##wc(R,X); \ R##_c = FP_CLS_NAN; \ } while (0) /* Obtain the current rounding mode. */ #define FP_ROUNDMODE mode #define FP_RND_NEAREST (FPCR_DYN_NORMAL >> FPCR_DYN_SHIFT) #define FP_RND_ZERO (FPCR_DYN_CHOPPED >> FPCR_DYN_SHIFT) #define FP_RND_PINF (FPCR_DYN_PLUS >> FPCR_DYN_SHIFT) #define FP_RND_MINF (FPCR_DYN_MINUS >> FPCR_DYN_SHIFT) /* Exception flags. */ #define FP_EX_INVALID IEEE_TRAP_ENABLE_INV #define FP_EX_OVERFLOW IEEE_TRAP_ENABLE_OVF #define FP_EX_UNDERFLOW IEEE_TRAP_ENABLE_UNF #define FP_EX_DIVZERO IEEE_TRAP_ENABLE_DZE #define FP_EX_INEXACT IEEE_TRAP_ENABLE_INE #define FP_EX_DENORM IEEE_TRAP_ENABLE_DNO #define FP_DENORM_ZERO (swcr & IEEE_MAP_DMZ) /* We write the results always */ #define FP_INHIBIT_RESULTS 0 #endif PK ! +�Nc c spinlock.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_SPINLOCK_H #define _ALPHA_SPINLOCK_H #include <linux/kernel.h> #include <asm/current.h> #include <asm/barrier.h> #include <asm/processor.h> /* * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. * * We make no fairness assumptions. They have a cost. */ #define arch_spin_is_locked(x) ((x)->lock != 0) static inline int arch_spin_value_unlocked(arch_spinlock_t lock) { return lock.lock == 0; } static inline void arch_spin_unlock(arch_spinlock_t * lock) { mb(); lock->lock = 0; } static inline void arch_spin_lock(arch_spinlock_t * lock) { long tmp; __asm__ __volatile__( "1: ldl_l %0,%1\n" " bne %0,2f\n" " lda %0,1\n" " stl_c %0,%1\n" " beq %0,2f\n" " mb\n" ".subsection 2\n" "2: ldl %0,%1\n" " bne %0,2b\n" " br 1b\n" ".previous" : "=&r" (tmp), "=m" (lock->lock) : "m"(lock->lock) : "memory"); } static inline int arch_spin_trylock(arch_spinlock_t *lock) { return !test_and_set_bit(0, &lock->lock); } /***********************************************************/ static inline void arch_read_lock(arch_rwlock_t *lock) { long regx; __asm__ __volatile__( "1: ldl_l %1,%0\n" " blbs %1,6f\n" " subl %1,2,%1\n" " stl_c %1,%0\n" " beq %1,6f\n" " mb\n" ".subsection 2\n" "6: ldl %1,%0\n" " blbs %1,6b\n" " br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx) : "m" (*lock) : "memory"); } static inline void arch_write_lock(arch_rwlock_t *lock) { long regx; __asm__ __volatile__( "1: ldl_l %1,%0\n" " bne %1,6f\n" " lda %1,1\n" " stl_c %1,%0\n" " beq %1,6f\n" " mb\n" ".subsection 2\n" "6: ldl %1,%0\n" " bne %1,6b\n" " br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx) : "m" (*lock) : "memory"); } static inline int arch_read_trylock(arch_rwlock_t * lock) { long regx; int success; __asm__ __volatile__( "1: ldl_l %1,%0\n" " lda %2,0\n" " blbs %1,2f\n" " subl %1,2,%2\n" " stl_c %2,%0\n" " beq %2,6f\n" "2: mb\n" ".subsection 2\n" "6: br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx), "=&r" (success) : "m" (*lock) : "memory"); return success; } static inline int arch_write_trylock(arch_rwlock_t * lock) { long regx; int success; __asm__ __volatile__( "1: ldl_l %1,%0\n" " lda %2,0\n" " bne %1,2f\n" " lda %2,1\n" " stl_c %2,%0\n" " beq %2,6f\n" "2: mb\n" ".subsection 2\n" "6: br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx), "=&r" (success) : "m" (*lock) : "memory"); return success; } static inline void arch_read_unlock(arch_rwlock_t * lock) { long regx; __asm__ __volatile__( " mb\n" "1: ldl_l %1,%0\n" " addl %1,2,%1\n" " stl_c %1,%0\n" " beq %1,6f\n" ".subsection 2\n" "6: br 1b\n" ".previous" : "=m" (*lock), "=&r" (regx) : "m" (*lock) : "memory"); } static inline void arch_write_unlock(arch_rwlock_t * lock) { mb(); lock->lock = 0; } #endif /* _ALPHA_SPINLOCK_H */ PK ! AS# serial.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * include/asm-alpha/serial.h */ /* * This assumes you have a 1.8432 MHz clock for your UART. * * It'd be nice if someone built a serial card with a 24.576 MHz * clock, since the 16550A is capable of handling a top speed of 1.5 * megabits/second; but this requires the faster clock. */ #define BASE_BAUD ( 1843200 / 16 ) /* Standard COM flags (except for COM4, because of the 8514 problem) */ #ifdef CONFIG_SERIAL_8250_DETECT_IRQ #define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ) #define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | UPF_AUTO_IRQ) #else #define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST) #define STD_COM4_FLAGS UPF_BOOT_AUTOCONF #endif #define SERIAL_PORT_DFNS \ /* UART CLK PORT IRQ FLAGS */ \ { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ PK ! '�;� � user.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_USER_H #define _ALPHA_USER_H #include <linux/sched.h> #include <linux/ptrace.h> #include <asm/page.h> #include <asm/reg.h> /* * Core file format: The core file is written in such a way that gdb * can understand it and provide useful information to the user (under * linux we use the `trad-core' bfd, NOT the osf-core). The file contents * are as follows: * * upage: 1 page consisting of a user struct that tells gdb * what is present in the file. Directly after this is a * copy of the task_struct, which is currently not used by gdb, * but it may come in handy at some point. All of the registers * are stored as part of the upage. The upage should always be * only one page long. * data: The data segment follows next. We use current->end_text to * current->brk to pick up all of the user variables, plus any memory * that may have been sbrk'ed. No attempt is made to determine if a * page is demand-zero or if a page is totally unused, we just cover * the entire range. All of the addresses are rounded in such a way * that an integral number of pages is written. * stack: We need the stack information in order to get a meaningful * backtrace. We need to write the data from usp to * current->start_stack, so we round each of these in order to be able * to write an integer number of pages. */ struct user { unsigned long regs[EF_SIZE/8+32]; /* integer and fp regs */ size_t u_tsize; /* text size (pages) */ size_t u_dsize; /* data size (pages) */ size_t u_ssize; /* stack size (pages) */ unsigned long start_code; /* text starting address */ unsigned long start_data; /* data starting address */ unsigned long start_stack; /* stack starting address */ long int signal; /* signal causing core dump */ unsigned long u_ar0; /* help gdb find registers */ unsigned long magic; /* identifies a core file */ char u_comm[32]; /* user command name */ }; #define NBPG PAGE_SIZE #define UPAGES 1 #define HOST_TEXT_START_ADDR (u.start_code) #define HOST_DATA_START_ADDR (u.start_data) #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) #endif /* _ALPHA_USER_H */ PK ! �U�ښ � sparsemem.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ALPHA_SPARSEMEM_H #define _ASM_ALPHA_SPARSEMEM_H #ifdef CONFIG_SPARSEMEM #define SECTION_SIZE_BITS 27 /* * According to "Alpha Architecture Reference Manual" physical * addresses are at most 48 bits. * https://download.majix.org/dec/alpha_arch_ref.pdf */ #define MAX_PHYSMEM_BITS 48 #endif /* CONFIG_SPARSEMEM */ #endif /* _ASM_ALPHA_SPARSEMEM_H */ PK ! 5��8�- �- core_lca.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_LCA__H__ #define __ALPHA_LCA__H__ #include <asm/compiler.h> #include <asm/mce.h> /* * Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068, * for example). * * This file is based on: * * DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors * Hardware Reference Manual; Digital Equipment Corp.; May 1994; * Maynard, MA; Order Number: EC-N2681-71. */ /* * NOTE: The LCA uses a Host Address Extension (HAE) register to access * PCI addresses that are beyond the first 27 bits of address * space. Updating the HAE requires an external cycle (and * a memory barrier), which tends to be slow. Instead of updating * it on each sparse memory access, we keep the current HAE value * cached in variable cache_hae. Only if the cached HAE differs * from the desired HAE value do we actually updated HAE register. * The HAE register is preserved by the interrupt handler entry/exit * code, so this scheme works even in the presence of interrupts. * * Dense memory space doesn't require the HAE, but is restricted to * aligned 32 and 64 bit accesses. Special Cycle and Interrupt * Acknowledge cycles may also require the use of the HAE. The LCA * limits I/O address space to the bottom 24 bits of address space, * but this easily covers the 16 bit ISA I/O address space. */ /* * NOTE 2! The memory operations do not set any memory barriers, as * it's not needed for cases like a frame buffer that is essentially * memory-like. You need to do them by hand if the operations depend * on ordering. * * Similarly, the port I/O operations do a "mb" only after a write * operation: if an mb is needed before (as in the case of doing * memory mapped I/O first, and then a port I/O operation to the same * device), it needs to be done by hand. * * After the above has bitten me 100 times, I'll give up and just do * the mb all the time, but right now I'm hoping this will work out. * Avoiding mb's may potentially be a noticeable speed improvement, * but I can't honestly say I've tested it. * * Handling interrupts that need to do mb's to synchronize to * non-interrupts is another fun race area. Don't do it (because if * you do, I'll have to do *everything* with interrupts disabled, * ugh). */ /* * Memory Controller registers: */ #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL) #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL) #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL) #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL) #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL) #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL) #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL) #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL) #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL) #define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL) #define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL) #define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL) #define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL) #define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL) #define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL) #define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL) #define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL) #define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL) #define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL) /* * I/O Controller registers: */ #define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL) #define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL) #define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL) #define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL) #define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL) #define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL) #define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL) #define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL) #define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL) #define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL) #define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL) #define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL) #define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL) #define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL) #define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL) #define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL) #define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL) #define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL) #define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL) #define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL) #define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL) #define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL) /* * Memory spaces: */ #define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL) #define LCA_CONF (IDENT_ADDR + 0x1e0000000UL) #define LCA_IO (IDENT_ADDR + 0x1c0000000UL) #define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) #define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL) /* * Bit definitions for I/O Controller status register 0: */ #define LCA_IOC_STAT0_CMD 0xf #define LCA_IOC_STAT0_ERR (1<<4) #define LCA_IOC_STAT0_LOST (1<<5) #define LCA_IOC_STAT0_THIT (1<<6) #define LCA_IOC_STAT0_TREF (1<<7) #define LCA_IOC_STAT0_CODE_SHIFT 8 #define LCA_IOC_STAT0_CODE_MASK 0x7 #define LCA_IOC_STAT0_P_NBR_SHIFT 13 #define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff #define LCA_HAE_ADDRESS LCA_IOC_HAE /* LCA PMR Power Management register defines */ #define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL) #define LCA_PMR_PDIV 0x7 /* Primary clock divisor */ #define LCA_PMR_ODIV 0x38 /* Override clock divisor */ #define LCA_PMR_INTO 0x40 /* Interrupt override */ #define LCA_PMR_DMAO 0x80 /* DMA override */ #define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even bits */ #define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even bits */ #define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8L /* LCA PMR Macros */ #define LCA_READ_PMR (*(volatile unsigned long *)LCA_PMR_ADDR) #define LCA_WRITE_PMR(d) (*((volatile unsigned long *)LCA_PMR_ADDR) = (d)) #define LCA_GET_PRIMARY(r) ((r) & LCA_PMR_PDIV) #define LCA_GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV) #define LCA_SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK)|(c))) /* LCA PMR Divisor values */ #define LCA_PMR_DIV_1 0x0 #define LCA_PMR_DIV_1_5 0x1 #define LCA_PMR_DIV_2 0x2 #define LCA_PMR_DIV_4 0x3 #define LCA_PMR_DIV_8 0x4 #define LCA_PMR_DIV_16 0x5 #define LCA_PMR_DIV_MIN DIV_1 #define LCA_PMR_DIV_MAX DIV_16 /* * Data structure for handling LCA machine checks. Correctable errors * result in a short logout frame, uncorrectable ones in a long one. */ struct el_lca_mcheck_short { struct el_common h; /* common logout header */ unsigned long esr; /* error-status register */ unsigned long ear; /* error-address register */ unsigned long dc_stat; /* dcache status register */ unsigned long ioc_stat0; /* I/O controller status register 0 */ unsigned long ioc_stat1; /* I/O controller status register 1 */ }; struct el_lca_mcheck_long { struct el_common h; /* common logout header */ unsigned long pt[31]; /* PAL temps */ unsigned long exc_addr; /* exception address */ unsigned long pad1[3]; unsigned long pal_base; /* PALcode base address */ unsigned long hier; /* hw interrupt enable */ unsigned long hirr; /* hw interrupt request */ unsigned long mm_csr; /* MMU control & status */ unsigned long dc_stat; /* data cache status */ unsigned long dc_addr; /* data cache addr register */ unsigned long abox_ctl; /* address box control register */ unsigned long esr; /* error status register */ unsigned long ear; /* error address register */ unsigned long car; /* cache control register */ unsigned long ioc_stat0; /* I/O controller status register 0 */ unsigned long ioc_stat1; /* I/O controller status register 1 */ unsigned long va; /* virtual address register */ }; union el_lca { struct el_common * c; struct el_lca_mcheck_long * l; struct el_lca_mcheck_short * s; }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * Unlike Jensen, the Noname machines have no concept of local * I/O---everything goes over the PCI bus. * * There is plenty room for optimization here. In particular, * the Alpha's insb/insw/extb/extw should be useful in moving * data to/from the right byte-lanes. */ #define vip volatile int __force * #define vuip volatile unsigned int __force * #define vulp volatile unsigned long __force * #define LCA_SET_HAE \ do { \ if (addr >= (1UL << 24)) { \ unsigned long msb = addr & 0xf8000000; \ addr -= msb; \ set_hae(msb); \ } \ } while (0) __EXTERN_INLINE unsigned int lca_ioread8(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; if (addr >= LCA_DENSE_MEM) { addr -= LCA_DENSE_MEM; LCA_SET_HAE; base_and_type = LCA_SPARSE_MEM + 0x00; } else { addr -= LCA_IO; base_and_type = LCA_IO + 0x00; } result = *(vip) ((addr << 5) + base_and_type); return __kernel_extbl(result, addr & 3); } __EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long w, base_and_type; if (addr >= LCA_DENSE_MEM) { addr -= LCA_DENSE_MEM; LCA_SET_HAE; base_and_type = LCA_SPARSE_MEM + 0x00; } else { addr -= LCA_IO; base_and_type = LCA_IO + 0x00; } w = __kernel_insbl(b, addr & 3); *(vuip) ((addr << 5) + base_and_type) = w; } __EXTERN_INLINE unsigned int lca_ioread16(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; if (addr >= LCA_DENSE_MEM) { addr -= LCA_DENSE_MEM; LCA_SET_HAE; base_and_type = LCA_SPARSE_MEM + 0x08; } else { addr -= LCA_IO; base_and_type = LCA_IO + 0x08; } result = *(vip) ((addr << 5) + base_and_type); return __kernel_extwl(result, addr & 3); } __EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long w, base_and_type; if (addr >= LCA_DENSE_MEM) { addr -= LCA_DENSE_MEM; LCA_SET_HAE; base_and_type = LCA_SPARSE_MEM + 0x08; } else { addr -= LCA_IO; base_and_type = LCA_IO + 0x08; } w = __kernel_inswl(b, addr & 3); *(vuip) ((addr << 5) + base_and_type) = w; } __EXTERN_INLINE unsigned int lca_ioread32(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; if (addr < LCA_DENSE_MEM) addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; return *(vuip)addr; } __EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; if (addr < LCA_DENSE_MEM) addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; *(vuip)addr = b; } __EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr) { return (void __iomem *)(addr + LCA_IO); } __EXTERN_INLINE void __iomem *lca_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + LCA_DENSE_MEM); } __EXTERN_INLINE int lca_is_ioaddr(unsigned long addr) { return addr >= IDENT_ADDR + 0x120000000UL; } __EXTERN_INLINE int lca_is_mmio(const volatile void __iomem *addr) { return (unsigned long)addr >= LCA_DENSE_MEM; } #undef vip #undef vuip #undef vulp #undef __IO_PREFIX #define __IO_PREFIX lca #define lca_trivial_rw_bw 2 #define lca_trivial_rw_lq 1 #define lca_trivial_io_bw 0 #define lca_trivial_io_lq 0 #define lca_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_LCA__H__ */ PK ! /z[��= �= core_cia.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_CIA__H__ #define __ALPHA_CIA__H__ /* Define to experiment with fitting everything into one 512MB HAE window. */ #define CIA_ONE_HAE_WINDOW 1 #include <linux/types.h> #include <asm/compiler.h> /* * CIA is the internal name for the 21171 chipset which provides * memory controller and PCI access for the 21164 chip based systems. * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS). * * The lineage is a bit confused, since the 21174 was reportedly started * from the 21171 Pass 1 mask, and so is missing bug fixes that appear * in 21171 Pass 2 and 21172, but it also contains additional features. * * This file is based on: * * DECchip 21171 Core Logic Chipset * Technical Reference Manual * * EC-QE18B-TE * * david.rusling@reo.mts.dec.com Initial Version. * */ /* * CIA ADDRESS BIT DEFINITIONS * * 3333 3333 3322 2222 2222 1111 1111 11 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- * 1 000 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- * | |\| * | Byte Enable --+ | * | Transfer Length --+ * +-- IO space, not cached * * Byte Transfer * Enable Length Transfer Byte Address * adr<6:5> adr<4:3> Length Enable Adder * --------------------------------------------- * 00 00 Byte 1110 0x000 * 01 00 Byte 1101 0x020 * 10 00 Byte 1011 0x040 * 11 00 Byte 0111 0x060 * * 00 01 Word 1100 0x008 * 01 01 Word 1001 0x028 <= Not supported in this code. * 10 01 Word 0011 0x048 * * 00 10 Tribyte 1000 0x010 * 01 10 Tribyte 0001 0x030 * * 10 11 Longword 0000 0x058 * * Note that byte enables are asserted low. * */ #define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */ #define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */ #define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */ /* * 21171-CA Control and Status Registers */ #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL) # define CIA_REV_MASK 0xff #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL) #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL) # define CIA_CTRL_PCI_EN (1 << 0) # define CIA_CTRL_PCI_LOCK_EN (1 << 1) # define CIA_CTRL_PCI_LOOP_EN (1 << 2) # define CIA_CTRL_FST_BB_EN (1 << 3) # define CIA_CTRL_PCI_MST_EN (1 << 4) # define CIA_CTRL_PCI_MEM_EN (1 << 5) # define CIA_CTRL_PCI_REQ64_EN (1 << 6) # define CIA_CTRL_PCI_ACK64_EN (1 << 7) # define CIA_CTRL_ADDR_PE_EN (1 << 8) # define CIA_CTRL_PERR_EN (1 << 9) # define CIA_CTRL_FILL_ERR_EN (1 << 10) # define CIA_CTRL_MCHK_ERR_EN (1 << 11) # define CIA_CTRL_ECC_CHK_EN (1 << 12) # define CIA_CTRL_ASSERT_IDLE_BC (1 << 13) # define CIA_CTRL_COM_IDLE_BC (1 << 14) # define CIA_CTRL_CSR_IOA_BYPASS (1 << 15) # define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16) # define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17) # define CIA_CTRL_ARB_CPU_EN (1 << 18) # define CIA_CTRL_EN_ARB_LINK (1 << 19) # define CIA_CTRL_RD_TYPE_SHIFT 20 # define CIA_CTRL_RL_TYPE_SHIFT 24 # define CIA_CTRL_RM_TYPE_SHIFT 28 # define CIA_CTRL_EN_DMA_RD_PERF (1 << 31) #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL) # define CIA_CNFG_IOA_BWEN (1 << 0) # define CIA_CNFG_PCI_MWEN (1 << 4) # define CIA_CNFG_PCI_DWEN (1 << 5) # define CIA_CNFG_PCI_WLEN (1 << 8) #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL) #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL) #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL) #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL) #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL) # define CIA_CACK_EN_LOCK_EN (1 << 0) # define CIA_CACK_EN_MB_EN (1 << 1) # define CIA_CACK_EN_SET_DIRTY_EN (1 << 2) # define CIA_CACK_EN_BC_VICTIM_EN (1 << 3) /* * 21171-CA Diagnostic Registers */ #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL) #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL) /* * 21171-CA Performance Monitor registers */ #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL) #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL) /* * 21171-CA Error registers */ #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL) #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL) #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL) # define CIA_ERR_COR_ERR (1 << 0) # define CIA_ERR_UN_COR_ERR (1 << 1) # define CIA_ERR_CPU_PE (1 << 2) # define CIA_ERR_MEM_NEM (1 << 3) # define CIA_ERR_PCI_SERR (1 << 4) # define CIA_ERR_PERR (1 << 5) # define CIA_ERR_PCI_ADDR_PE (1 << 6) # define CIA_ERR_RCVD_MAS_ABT (1 << 7) # define CIA_ERR_RCVD_TAR_ABT (1 << 8) # define CIA_ERR_PA_PTE_INV (1 << 9) # define CIA_ERR_FROM_WRT_ERR (1 << 10) # define CIA_ERR_IOA_TIMEOUT (1 << 11) # define CIA_ERR_LOST_CORR_ERR (1 << 16) # define CIA_ERR_LOST_UN_CORR_ERR (1 << 17) # define CIA_ERR_LOST_CPU_PE (1 << 18) # define CIA_ERR_LOST_MEM_NEM (1 << 19) # define CIA_ERR_LOST_PERR (1 << 21) # define CIA_ERR_LOST_PCI_ADDR_PE (1 << 22) # define CIA_ERR_LOST_RCVD_MAS_ABT (1 << 23) # define CIA_ERR_LOST_RCVD_TAR_ABT (1 << 24) # define CIA_ERR_LOST_PA_PTE_INV (1 << 25) # define CIA_ERR_LOST_FROM_WRT_ERR (1 << 26) # define CIA_ERR_LOST_IOA_TIMEOUT (1 << 27) # define CIA_ERR_VALID (1 << 31) #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL) #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL) #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL) #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL) #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL) #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL) #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL) #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL) /* * 21171-CA System configuration registers */ #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL) #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL) #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL) #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL) #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL) #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL) #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL) #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL) #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL) #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL) #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL) #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL) /* * 2117A-CA PCI Address and Scatter-Gather Registers. */ #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL) #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL) #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL) #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL) #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL) #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL) #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL) #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL) #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL) #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL) #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL) #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL) #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL) #define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100) #define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100) #define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100) #define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL) /* * 2117A-CA Address Translation Registers. */ /* 8 tag registers, the first 4 of which are lockable. */ #define CIA_IOC_TB_TAGn(n) \ (IDENT_ADDR + 0x8760000800UL + (n)*0x40) /* 4 page registers per tag register. */ #define CIA_IOC_TBn_PAGEm(n,m) \ (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40) /* * Memory spaces: */ #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL) #define CIA_CONF (IDENT_ADDR + 0x8700000000UL) #define CIA_IO (IDENT_ADDR + 0x8580000000UL) #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL) #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL) #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL) #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL) #define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL) #define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL) #define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL) #define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL) /* * ALCOR's GRU ASIC registers */ #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL) #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL) #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL) #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL) #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL) #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL) #define GRU_SCR (IDENT_ADDR + 0x8780000300UL) #define GRU_LED (IDENT_ADDR + 0x8780000800UL) #define GRU_RESET (IDENT_ADDR + 0x8780000900UL) #define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL #define XLT_GRU_INT_REQ_BITS 0x80003fffUL #define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0) /* * PYXIS interrupt control registers */ #define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL) #define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL) #define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL) #define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL) #define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL) #define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL) #define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL) #define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL) #define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL) #define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL) /* Offset between ram physical addresses and pci64 DAC bus addresses. */ #define PYXIS_DAC_OFFSET (1UL << 40) /* * Data structure for handling CIA machine checks. */ /* System-specific info. */ struct el_CIA_sysdata_mcheck { unsigned long cpu_err0; unsigned long cpu_err1; unsigned long cia_err; unsigned long cia_stat; unsigned long err_mask; unsigned long cia_syn; unsigned long mem_err0; unsigned long mem_err1; unsigned long pci_err0; unsigned long pci_err1; unsigned long pci_err2; }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE /* Do not touch, this should *NOT* be static inline */ #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * CIA (the 2117x PCI/memory support chipset for the EV5 (21164) * series of processors uses a sparse address mapping scheme to * get at PCI memory and I/O. */ /* * Memory functions. 64-bit and 32-bit accesses are done through * dense memory space, everything else through sparse space. * * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 * which gives 1Gbyte of accessible space which relates exactly * to the amount of PCI memory mapping *into* system address space. * See p 6-17 of the specification but it looks something like this: * * 21164 Address: * * 3 2 1 * 9876543210987654321098765432109876543210 * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset * LL = Transfer length * * PCI Address: * * 3 2 1 * 10987654321098765432109876543210 * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR * */ #define vip volatile int __force * #define vuip volatile unsigned int __force * #define vulp volatile unsigned long __force * __EXTERN_INLINE unsigned int cia_ioread8(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; if (addr >= CIA_DENSE_MEM) base_and_type = CIA_SPARSE_MEM + 0x00; else base_and_type = CIA_IO + 0x00; /* We can use CIA_MEM_R1_MASK for io ports too, since it is large enough to cover all io ports, and smaller than CIA_IO. */ addr &= CIA_MEM_R1_MASK; result = *(vip) ((addr << 5) + base_and_type); return __kernel_extbl(result, addr & 3); } __EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long w, base_and_type; if (addr >= CIA_DENSE_MEM) base_and_type = CIA_SPARSE_MEM + 0x00; else base_and_type = CIA_IO + 0x00; addr &= CIA_MEM_R1_MASK; w = __kernel_insbl(b, addr & 3); *(vuip) ((addr << 5) + base_and_type) = w; } __EXTERN_INLINE unsigned int cia_ioread16(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; if (addr >= CIA_DENSE_MEM) base_and_type = CIA_SPARSE_MEM + 0x08; else base_and_type = CIA_IO + 0x08; addr &= CIA_MEM_R1_MASK; result = *(vip) ((addr << 5) + base_and_type); return __kernel_extwl(result, addr & 3); } __EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long w, base_and_type; if (addr >= CIA_DENSE_MEM) base_and_type = CIA_SPARSE_MEM + 0x08; else base_and_type = CIA_IO + 0x08; addr &= CIA_MEM_R1_MASK; w = __kernel_inswl(b, addr & 3); *(vuip) ((addr << 5) + base_and_type) = w; } __EXTERN_INLINE unsigned int cia_ioread32(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; if (addr < CIA_DENSE_MEM) addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18; return *(vuip)addr; } __EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; if (addr < CIA_DENSE_MEM) addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18; *(vuip)addr = b; } __EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr) { return (void __iomem *)(addr + CIA_IO); } __EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + CIA_DENSE_MEM); } __EXTERN_INLINE int cia_is_ioaddr(unsigned long addr) { return addr >= IDENT_ADDR + 0x8000000000UL; } __EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr) { return (unsigned long)addr >= CIA_DENSE_MEM; } __EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr) { return (void __iomem *)(addr + CIA_BW_IO); } __EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + CIA_BW_MEM); } __EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr) { return addr >= IDENT_ADDR + 0x8000000000UL; } __EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr) { return (unsigned long)addr < CIA_BW_IO; } #undef vip #undef vuip #undef vulp #undef __IO_PREFIX #define __IO_PREFIX cia #define cia_trivial_rw_bw 2 #define cia_trivial_rw_lq 1 #define cia_trivial_io_bw 0 #define cia_trivial_io_lq 0 #define cia_trivial_iounmap 1 #include <asm/io_trivial.h> #undef __IO_PREFIX #define __IO_PREFIX cia_bwx #define cia_bwx_trivial_rw_bw 1 #define cia_bwx_trivial_rw_lq 1 #define cia_bwx_trivial_io_bw 1 #define cia_bwx_trivial_io_lq 1 #define cia_bwx_trivial_iounmap 1 #include <asm/io_trivial.h> #undef __IO_PREFIX #ifdef CONFIG_ALPHA_PYXIS #define __IO_PREFIX cia_bwx #else #define __IO_PREFIX cia #endif #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_CIA__H__ */ PK ! �B� pal.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_PAL_H #define __ALPHA_PAL_H #include <uapi/asm/pal.h> #ifndef __ASSEMBLY__ extern void halt(void) __attribute__((noreturn)); #define __halt() __asm__ __volatile__ ("call_pal %0 #halt" : : "i" (PAL_halt)) #define imb() \ __asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory") #define draina() \ __asm__ __volatile__ ("call_pal %0 #draina" : : "i" (PAL_draina) : "memory") #define __CALL_PAL_R0(NAME, TYPE) \ extern inline TYPE NAME(void) \ { \ register TYPE __r0 __asm__("$0"); \ __asm__ __volatile__( \ "call_pal %1 # " #NAME \ :"=r" (__r0) \ :"i" (PAL_ ## NAME) \ :"$1", "$16", "$22", "$23", "$24", "$25"); \ return __r0; \ } #define __CALL_PAL_W1(NAME, TYPE0) \ extern inline void NAME(TYPE0 arg0) \ { \ register TYPE0 __r16 __asm__("$16") = arg0; \ __asm__ __volatile__( \ "call_pal %1 # "#NAME \ : "=r"(__r16) \ : "i"(PAL_ ## NAME), "0"(__r16) \ : "$1", "$22", "$23", "$24", "$25"); \ } #define __CALL_PAL_W2(NAME, TYPE0, TYPE1) \ extern inline void NAME(TYPE0 arg0, TYPE1 arg1) \ { \ register TYPE0 __r16 __asm__("$16") = arg0; \ register TYPE1 __r17 __asm__("$17") = arg1; \ __asm__ __volatile__( \ "call_pal %2 # "#NAME \ : "=r"(__r16), "=r"(__r17) \ : "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \ : "$1", "$22", "$23", "$24", "$25"); \ } #define __CALL_PAL_RW1(NAME, RTYPE, TYPE0) \ extern inline RTYPE NAME(TYPE0 arg0) \ { \ register RTYPE __r0 __asm__("$0"); \ register TYPE0 __r16 __asm__("$16") = arg0; \ __asm__ __volatile__( \ "call_pal %2 # "#NAME \ : "=r"(__r16), "=r"(__r0) \ : "i"(PAL_ ## NAME), "0"(__r16) \ : "$1", "$22", "$23", "$24", "$25"); \ return __r0; \ } #define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1) \ extern inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \ { \ register RTYPE __r0 __asm__("$0"); \ register TYPE0 __r16 __asm__("$16") = arg0; \ register TYPE1 __r17 __asm__("$17") = arg1; \ __asm__ __volatile__( \ "call_pal %3 # "#NAME \ : "=r"(__r16), "=r"(__r17), "=r"(__r0) \ : "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \ : "$1", "$22", "$23", "$24", "$25"); \ return __r0; \ } __CALL_PAL_W1(cflush, unsigned long); __CALL_PAL_R0(rdmces, unsigned long); __CALL_PAL_R0(rdps, unsigned long); __CALL_PAL_R0(rdusp, unsigned long); __CALL_PAL_RW1(swpipl, unsigned long, unsigned long); __CALL_PAL_R0(whami, unsigned long); __CALL_PAL_W2(wrent, void*, unsigned long); __CALL_PAL_W1(wripir, unsigned long); __CALL_PAL_W1(wrkgp, unsigned long); __CALL_PAL_W1(wrmces, unsigned long); __CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long); __CALL_PAL_W1(wrusp, unsigned long); __CALL_PAL_W1(wrvptptr, unsigned long); __CALL_PAL_RW1(wtint, unsigned long, unsigned long); /* * TB routines.. */ #define __tbi(nr,arg,arg1...) \ ({ \ register unsigned long __r16 __asm__("$16") = (nr); \ register unsigned long __r17 __asm__("$17"); arg; \ __asm__ __volatile__( \ "call_pal %3 #__tbi" \ :"=r" (__r16),"=r" (__r17) \ :"0" (__r16),"i" (PAL_tbi) ,##arg1 \ :"$0", "$1", "$22", "$23", "$24", "$25"); \ }) #define tbi(x,y) __tbi(x,__r17=(y),"1" (__r17)) #define tbisi(x) __tbi(1,__r17=(x),"1" (__r17)) #define tbisd(x) __tbi(2,__r17=(x),"1" (__r17)) #define tbis(x) __tbi(3,__r17=(x),"1" (__r17)) #define tbiap() __tbi(-1, /* no second argument */) #define tbia() __tbi(-2, /* no second argument */) /* * QEMU Cserv routines.. */ static inline unsigned long qemu_get_walltime(void) { register unsigned long v0 __asm__("$0"); register unsigned long a0 __asm__("$16") = 3; asm("call_pal %2 # cserve get_time" : "=r"(v0), "+r"(a0) : "i"(PAL_cserve) : "$17", "$18", "$19", "$20", "$21"); return v0; } static inline unsigned long qemu_get_alarm(void) { register unsigned long v0 __asm__("$0"); register unsigned long a0 __asm__("$16") = 4; asm("call_pal %2 # cserve get_alarm" : "=r"(v0), "+r"(a0) : "i"(PAL_cserve) : "$17", "$18", "$19", "$20", "$21"); return v0; } static inline void qemu_set_alarm_rel(unsigned long expire) { register unsigned long a0 __asm__("$16") = 5; register unsigned long a1 __asm__("$17") = expire; asm volatile("call_pal %2 # cserve set_alarm_rel" : "+r"(a0), "+r"(a1) : "i"(PAL_cserve) : "$0", "$18", "$19", "$20", "$21"); } static inline void qemu_set_alarm_abs(unsigned long expire) { register unsigned long a0 __asm__("$16") = 6; register unsigned long a1 __asm__("$17") = expire; asm volatile("call_pal %2 # cserve set_alarm_abs" : "+r"(a0), "+r"(a1) : "i"(PAL_cserve) : "$0", "$18", "$19", "$20", "$21"); } static inline unsigned long qemu_get_vmtime(void) { register unsigned long v0 __asm__("$0"); register unsigned long a0 __asm__("$16") = 7; asm("call_pal %2 # cserve get_time" : "=r"(v0), "+r"(a0) : "i"(PAL_cserve) : "$17", "$18", "$19", "$20", "$21"); return v0; } #endif /* !__ASSEMBLY__ */ #endif /* __ALPHA_PAL_H */ PK ! ��5� � core_polaris.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_POLARIS__H__ #define __ALPHA_POLARIS__H__ #include <linux/types.h> #include <asm/compiler.h> /* * POLARIS is the internal name for a core logic chipset which provides * memory controller and PCI access for the 21164PC chip based systems. * * This file is based on: * * Polaris System Controller * Device Functional Specification * 22-Jan-98 * Rev. 4.2 * */ /* Polaris memory regions */ #define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000UL) #define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000UL) #define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000UL) #define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000UL) #define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000UL) #define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000UL) #define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000UL) #define POLARIS_IACK_SC POLARIS_IACK_BASE /* The Polaris command/status registers live in PCI Config space for * bus 0/device 0. As such, they may be bytes, words, or doublewords. */ #define POLARIS_W_VENID (POLARIS_DENSE_CONFIG_BASE) #define POLARIS_W_DEVID (POLARIS_DENSE_CONFIG_BASE+2) #define POLARIS_W_CMD (POLARIS_DENSE_CONFIG_BASE+4) #define POLARIS_W_STATUS (POLARIS_DENSE_CONFIG_BASE+6) /* * Data structure for handling POLARIS machine checks: */ struct el_POLARIS_sysdata_mcheck { u_long psc_status; u_long psc_pcictl0; u_long psc_pcictl1; u_long psc_pcictl2; }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * POLARIS, the PCI/memory support chipset for the PCA56 (21164PC) * processors, can use either a sparse address mapping scheme, or the * so-called byte-word PCI address space, to get at PCI memory and I/O. * * However, we will support only the BWX form. */ /* * Memory functions. Polaris allows all accesses (byte/word * as well as long/quad) to be done through dense space. * * We will only support DENSE access via BWX insns. */ __EXTERN_INLINE void __iomem *polaris_ioportmap(unsigned long addr) { return (void __iomem *)(addr + POLARIS_DENSE_IO_BASE); } __EXTERN_INLINE void __iomem *polaris_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + POLARIS_DENSE_MEM_BASE); } __EXTERN_INLINE int polaris_is_ioaddr(unsigned long addr) { return addr >= POLARIS_SPARSE_MEM_BASE; } __EXTERN_INLINE int polaris_is_mmio(const volatile void __iomem *addr) { return (unsigned long)addr < POLARIS_SPARSE_IO_BASE; } #undef __IO_PREFIX #define __IO_PREFIX polaris #define polaris_trivial_rw_bw 1 #define polaris_trivial_rw_lq 1 #define polaris_trivial_io_bw 1 #define polaris_trivial_io_lq 1 #define polaris_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_POLARIS__H__ */ PK ! :�i i perf_event.hnu �[��� #ifndef __ASM_ALPHA_PERF_EVENT_H #define __ASM_ALPHA_PERF_EVENT_H #endif /* __ASM_ALPHA_PERF_EVENT_H */ PK ! k*@��C �C core_apecs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_APECS__H__ #define __ALPHA_APECS__H__ #include <linux/types.h> #include <asm/compiler.h> /* * APECS is the internal name for the 2107x chipset which provides * memory controller and PCI access for the 21064 chip based systems. * * This file is based on: * * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets * Data Sheet * * EC-N0648-72 * * * david.rusling@reo.mts.dec.com Initial Version. * */ /* An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address that get passed through the PCI<->ISA bridge chip. So we've gotta use both windows to max out the physical memory we can DMA to. Sigh... If we try a window at 0 for 1GB as a work-around, we run into conflicts with ISA/PCI bus memory which can't be relocated, like VGA aperture and BIOS ROMs. So we must put the windows high enough to avoid these areas. We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1, and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1. Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually be used for that range (via virt_to_bus()). Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb, to keep virt_to_bus() from returning an address in the first window, for a data area that goes beyond the 64Mb first DMA window. Sigh... The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but we can't just use that here, because of header file looping... :-( Window 1 will be used for all DMA from the ISA bus; yes, that does limit what memory an ISA floppy or sound card or Ethernet can touch, but it's also a known limitation on other platforms as well. We use the same technique that is used on INTEL platforms with similar limitation: set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init(). We trust that any ISA bus device drivers will *always* ask for DMAable memory explicitly via kmalloc()/get_free_pages() flags arguments. Note that most PCI bus devices' drivers do *not* explicitly ask for DMAable memory; they count on being able to DMA to any memory they get from kmalloc()/get_free_pages(). They will also use window 1 for any physical memory accesses below 64Mb; the rest will be handled by window 2, maxing out at 1Gb of memory. I trust this is enough... :-) We hope that the area before the first window is large enough so that there will be no overlap at the top end (64Mb). We *must* locate the PCI cards' memory just below window 1, so that there's still the possibility of being able to access it via SPARSE space. This is important for cards such as the Matrox Millennium, whose Xserver wants to access memory-mapped registers in byte and short lengths. Note that the XL is treated differently from the AVANTI, even though for most other things they are identical. It didn't seem reasonable to make the AVANTI support pay for the limitations of the XL. It is true, however, that an XL kernel will run on an AVANTI without problems. %%% All of this should be obviated by the ability to route everything through the iommu. */ /* * 21071-DA Control and Status registers. * These are used for PCI memory access. */ #define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL) #define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL) #define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL) #define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL) #define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL) #define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL) #define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL) #define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL) #define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL) #define APECS_IOC_PB2R (IDENT_ADDR + 0x1A0000120UL) #define APECS_IOC_PM1R (IDENT_ADDR + 0x1A0000140UL) #define APECS_IOC_PM2R (IDENT_ADDR + 0x1A0000160UL) #define APECS_IOC_HAXR0 (IDENT_ADDR + 0x1A0000180UL) #define APECS_IOC_HAXR1 (IDENT_ADDR + 0x1A00001A0UL) #define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL) #define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL) #define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL) #define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL) #define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL) #define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL) #define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL) #define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL) #define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL) #define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL) #define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL) #define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL) #define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL) #define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL) #define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL) #define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL) #define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL) #define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL) #define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL) /* * 21071-CA Control and Status registers. * These are used to program memory timing, * configure memory and initialise the B-Cache. */ #define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL) #define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL) #define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL) #define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL) #define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL) #define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL) #define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL) #define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL) #define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL) #define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL) #define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL) #define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL) #define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL) /* Bank x Base Address Register */ #define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL) #define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL) #define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL) #define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL) #define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL) #define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL) #define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL) #define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL) #define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL) /* Bank x Configuration Register */ #define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL) #define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL) #define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL) #define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL) #define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL) #define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL) #define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL) #define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL) #define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL) /* Bank x Timing Register A */ #define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL) #define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL) #define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL) #define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL) #define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL) #define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL) #define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL) #define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL) #define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL) /* Bank x Timing Register B */ #define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL) #define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL) #define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL) #define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL) #define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL) #define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL) #define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL) #define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL) #define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL) /* * Memory spaces: */ #define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL) #define APECS_CONF (IDENT_ADDR + 0x1e0000000UL) #define APECS_IO (IDENT_ADDR + 0x1c0000000UL) #define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) #define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL) /* * Bit definitions for I/O Controller status register 0: */ #define APECS_IOC_STAT0_CMD 0xf #define APECS_IOC_STAT0_ERR (1<<4) #define APECS_IOC_STAT0_LOST (1<<5) #define APECS_IOC_STAT0_THIT (1<<6) #define APECS_IOC_STAT0_TREF (1<<7) #define APECS_IOC_STAT0_CODE_SHIFT 8 #define APECS_IOC_STAT0_CODE_MASK 0x7 #define APECS_IOC_STAT0_P_NBR_SHIFT 13 #define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff #define APECS_HAE_ADDRESS APECS_IOC_HAXR1 /* * Data structure for handling APECS machine checks: */ struct el_apecs_mikasa_sysdata_mcheck { unsigned long coma_gcr; unsigned long coma_edsr; unsigned long coma_ter; unsigned long coma_elar; unsigned long coma_ehar; unsigned long coma_ldlr; unsigned long coma_ldhr; unsigned long coma_base0; unsigned long coma_base1; unsigned long coma_base2; unsigned long coma_base3; unsigned long coma_cnfg0; unsigned long coma_cnfg1; unsigned long coma_cnfg2; unsigned long coma_cnfg3; unsigned long epic_dcsr; unsigned long epic_pear; unsigned long epic_sear; unsigned long epic_tbr1; unsigned long epic_tbr2; unsigned long epic_pbr1; unsigned long epic_pbr2; unsigned long epic_pmr1; unsigned long epic_pmr2; unsigned long epic_harx1; unsigned long epic_harx2; unsigned long epic_pmlt; unsigned long epic_tag0; unsigned long epic_tag1; unsigned long epic_tag2; unsigned long epic_tag3; unsigned long epic_tag4; unsigned long epic_tag5; unsigned long epic_tag6; unsigned long epic_tag7; unsigned long epic_data0; unsigned long epic_data1; unsigned long epic_data2; unsigned long epic_data3; unsigned long epic_data4; unsigned long epic_data5; unsigned long epic_data6; unsigned long epic_data7; unsigned long pceb_vid; unsigned long pceb_did; unsigned long pceb_revision; unsigned long pceb_command; unsigned long pceb_status; unsigned long pceb_latency; unsigned long pceb_control; unsigned long pceb_arbcon; unsigned long pceb_arbpri; unsigned long esc_id; unsigned long esc_revision; unsigned long esc_int0; unsigned long esc_int1; unsigned long esc_elcr0; unsigned long esc_elcr1; unsigned long esc_last_eisa; unsigned long esc_nmi_stat; unsigned long pci_ir; unsigned long pci_imr; unsigned long svr_mgr; }; /* This for the normal APECS machines. */ struct el_apecs_sysdata_mcheck { unsigned long coma_gcr; unsigned long coma_edsr; unsigned long coma_ter; unsigned long coma_elar; unsigned long coma_ehar; unsigned long coma_ldlr; unsigned long coma_ldhr; unsigned long coma_base0; unsigned long coma_base1; unsigned long coma_base2; unsigned long coma_cnfg0; unsigned long coma_cnfg1; unsigned long coma_cnfg2; unsigned long epic_dcsr; unsigned long epic_pear; unsigned long epic_sear; unsigned long epic_tbr1; unsigned long epic_tbr2; unsigned long epic_pbr1; unsigned long epic_pbr2; unsigned long epic_pmr1; unsigned long epic_pmr2; unsigned long epic_harx1; unsigned long epic_harx2; unsigned long epic_pmlt; unsigned long epic_tag0; unsigned long epic_tag1; unsigned long epic_tag2; unsigned long epic_tag3; unsigned long epic_tag4; unsigned long epic_tag5; unsigned long epic_tag6; unsigned long epic_tag7; unsigned long epic_data0; unsigned long epic_data1; unsigned long epic_data2; unsigned long epic_data3; unsigned long epic_data4; unsigned long epic_data5; unsigned long epic_data6; unsigned long epic_data7; }; struct el_apecs_procdata { unsigned long paltemp[32]; /* PAL TEMP REGS. */ /* EV4-specific fields */ unsigned long exc_addr; /* Address of excepting instruction. */ unsigned long exc_sum; /* Summary of arithmetic traps. */ unsigned long exc_mask; /* Exception mask (from exc_sum). */ unsigned long iccsr; /* IBox hardware enables. */ unsigned long pal_base; /* Base address for PALcode. */ unsigned long hier; /* Hardware Interrupt Enable. */ unsigned long hirr; /* Hardware Interrupt Request. */ unsigned long csr; /* D-stream fault info. */ unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */ unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ unsigned long abox_ctl; /* ABox Control Register. */ unsigned long biu_stat; /* BIU Status. */ unsigned long biu_addr; /* BUI Address. */ unsigned long biu_ctl; /* BIU Control. */ unsigned long fill_syndrome;/* For correcting ECC errors. */ unsigned long fill_addr; /* Cache block which was being read */ unsigned long va; /* Effective VA of fault or miss. */ unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/ }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * Unlike Jensen, the APECS machines have no concept of local * I/O---everything goes over the PCI bus. * * There is plenty room for optimization here. In particular, * the Alpha's insb/insw/extb/extw should be useful in moving * data to/from the right byte-lanes. */ #define vip volatile int __force * #define vuip volatile unsigned int __force * #define vulp volatile unsigned long __force * #define APECS_SET_HAE \ do { \ if (addr >= (1UL << 24)) { \ unsigned long msb = addr & 0xf8000000; \ addr -= msb; \ set_hae(msb); \ } \ } while (0) __EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; if (addr >= APECS_DENSE_MEM) { addr -= APECS_DENSE_MEM; APECS_SET_HAE; base_and_type = APECS_SPARSE_MEM + 0x00; } else { addr -= APECS_IO; base_and_type = APECS_IO + 0x00; } result = *(vip) ((addr << 5) + base_and_type); return __kernel_extbl(result, addr & 3); } __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long w, base_and_type; if (addr >= APECS_DENSE_MEM) { addr -= APECS_DENSE_MEM; APECS_SET_HAE; base_and_type = APECS_SPARSE_MEM + 0x00; } else { addr -= APECS_IO; base_and_type = APECS_IO + 0x00; } w = __kernel_insbl(b, addr & 3); *(vuip) ((addr << 5) + base_and_type) = w; } __EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; if (addr >= APECS_DENSE_MEM) { addr -= APECS_DENSE_MEM; APECS_SET_HAE; base_and_type = APECS_SPARSE_MEM + 0x08; } else { addr -= APECS_IO; base_and_type = APECS_IO + 0x08; } result = *(vip) ((addr << 5) + base_and_type); return __kernel_extwl(result, addr & 3); } __EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long w, base_and_type; if (addr >= APECS_DENSE_MEM) { addr -= APECS_DENSE_MEM; APECS_SET_HAE; base_and_type = APECS_SPARSE_MEM + 0x08; } else { addr -= APECS_IO; base_and_type = APECS_IO + 0x08; } w = __kernel_inswl(b, addr & 3); *(vuip) ((addr << 5) + base_and_type) = w; } __EXTERN_INLINE unsigned int apecs_ioread32(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; if (addr < APECS_DENSE_MEM) addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18; return *(vuip)addr; } __EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; if (addr < APECS_DENSE_MEM) addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18; *(vuip)addr = b; } __EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr) { return (void __iomem *)(addr + APECS_IO); } __EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + APECS_DENSE_MEM); } __EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr) { return addr >= IDENT_ADDR + 0x180000000UL; } __EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr) { return (unsigned long)addr >= APECS_DENSE_MEM; } #undef APECS_SET_HAE #undef vip #undef vuip #undef vulp #undef __IO_PREFIX #define __IO_PREFIX apecs #define apecs_trivial_io_bw 0 #define apecs_trivial_io_lq 0 #define apecs_trivial_rw_bw 2 #define apecs_trivial_rw_lq 1 #define apecs_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_APECS__H__ */ PK ! zb{� kdebug.hnu �[��� #include <asm-generic/kdebug.h> PK ! ��0 � � barrier.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __BARRIER_H #define __BARRIER_H #define mb() __asm__ __volatile__("mb": : :"memory") #define rmb() __asm__ __volatile__("mb": : :"memory") #define wmb() __asm__ __volatile__("wmb": : :"memory") #define __smp_load_acquire(p) \ ({ \ compiletime_assert_atomic_type(*p); \ __READ_ONCE(*p); \ }) #ifdef CONFIG_SMP #define __ASM_SMP_MB "\tmb\n" #else #define __ASM_SMP_MB #endif #include <asm-generic/barrier.h> #endif /* __BARRIER_H */ PK ! �h+ linkage.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_LINKAGE_H #define __ASM_LINKAGE_H #define cond_syscall(x) asm(".weak\t" #x "\n" #x " = sys_ni_syscall") #define SYSCALL_ALIAS(alias, name) \ asm ( #alias " = " #name "\n\t.globl " #alias) #endif PK ! `" �I I mmu_context.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_MMU_CONTEXT_H #define __ALPHA_MMU_CONTEXT_H /* * get a new mmu context.. * * Copyright (C) 1996, Linus Torvalds */ #include <linux/mm_types.h> #include <linux/sched.h> #include <asm/machvec.h> #include <asm/compiler.h> #include <asm-generic/mm_hooks.h> /* * Force a context reload. This is needed when we change the page * table pointer or when we update the ASN of the current process. */ /* Don't get into trouble with dueling __EXTERN_INLINEs. */ #ifndef __EXTERN_INLINE #include <asm/io.h> #endif static inline unsigned long __reload_thread(struct pcb_struct *pcb) { register unsigned long a0 __asm__("$16"); register unsigned long v0 __asm__("$0"); a0 = virt_to_phys(pcb); __asm__ __volatile__( "call_pal %2 #__reload_thread" : "=r"(v0), "=r"(a0) : "i"(PAL_swpctx), "r"(a0) : "$1", "$22", "$23", "$24", "$25"); return v0; } /* * The maximum ASN's the processor supports. On the EV4 this is 63 * but the PAL-code doesn't actually use this information. On the * EV5 this is 127, and EV6 has 255. * * On the EV4, the ASNs are more-or-less useless anyway, as they are * only used as an icache tag, not for TB entries. On the EV5 and EV6, * ASN's also validate the TB entries, and thus make a lot more sense. * * The EV4 ASN's don't even match the architecture manual, ugh. And * I quote: "If a processor implements address space numbers (ASNs), * and the old PTE has the Address Space Match (ASM) bit clear (ASNs * in use) and the Valid bit set, then entries can also effectively be * made coherent by assigning a new, unused ASN to the currently * running process and not reusing the previous ASN before calling the * appropriate PALcode routine to invalidate the translation buffer (TB)". * * In short, the EV4 has a "kind of" ASN capability, but it doesn't actually * work correctly and can thus not be used (explaining the lack of PAL-code * support). */ #define EV4_MAX_ASN 63 #define EV5_MAX_ASN 127 #define EV6_MAX_ASN 255 #ifdef CONFIG_ALPHA_GENERIC # define MAX_ASN (alpha_mv.max_asn) #else # ifdef CONFIG_ALPHA_EV4 # define MAX_ASN EV4_MAX_ASN # elif defined(CONFIG_ALPHA_EV5) # define MAX_ASN EV5_MAX_ASN # else # define MAX_ASN EV6_MAX_ASN # endif #endif /* * cpu_last_asn(processor): * 63 0 * +-------------+----------------+--------------+ * | asn version | this processor | hardware asn | * +-------------+----------------+--------------+ */ #include <asm/smp.h> #ifdef CONFIG_SMP #define cpu_last_asn(cpuid) (cpu_data[cpuid].last_asn) #else extern unsigned long last_asn; #define cpu_last_asn(cpuid) last_asn #endif /* CONFIG_SMP */ #define WIDTH_HARDWARE_ASN 8 #define ASN_FIRST_VERSION (1UL << WIDTH_HARDWARE_ASN) #define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1) /* * NOTE! The way this is set up, the high bits of the "asn_cache" (and * the "mm->context") are the ASN _version_ code. A version of 0 is * always considered invalid, so to invalidate another process you only * need to do "p->mm->context = 0". * * If we need more ASN's than the processor has, we invalidate the old * user TLB's (tbiap()) and start a new ASN version. That will automatically * force a new asn for any other processes the next time they want to * run. */ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __MMU_EXTERN_INLINE #endif extern inline unsigned long __get_new_mm_context(struct mm_struct *mm, long cpu) { unsigned long asn = cpu_last_asn(cpu); unsigned long next = asn + 1; if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) { tbiap(); imb(); next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION; } cpu_last_asn(cpu) = next; return next; } __EXTERN_INLINE void ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, struct task_struct *next) { /* Check if our ASN is of an older version, and thus invalid. */ unsigned long asn; unsigned long mmc; long cpu = smp_processor_id(); #ifdef CONFIG_SMP cpu_data[cpu].asn_lock = 1; barrier(); #endif asn = cpu_last_asn(cpu); mmc = next_mm->context[cpu]; if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) { mmc = __get_new_mm_context(next_mm, cpu); next_mm->context[cpu] = mmc; } #ifdef CONFIG_SMP else cpu_data[cpu].need_new_asn = 1; #endif /* Always update the PCB ASN. Another thread may have allocated a new mm->context (via flush_tlb_mm) without the ASN serial number wrapping. We have no way to detect when this is needed. */ task_thread_info(next)->pcb.asn = mmc & HARDWARE_ASN_MASK; } __EXTERN_INLINE void ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, struct task_struct *next) { /* As described, ASN's are broken for TLB usage. But we can optimize for switching between threads -- if the mm is unchanged from current we needn't flush. */ /* ??? May not be needed because EV4 PALcode recognizes that ASN's are broken and does a tbiap itself on swpctx, under the "Must set ASN or flush" rule. At least this is true for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com). I'm going to leave this here anyway, just to Be Sure. -- r~ */ if (prev_mm != next_mm) tbiap(); /* Do continue to allocate ASNs, because we can still use them to avoid flushing the icache. */ ev5_switch_mm(prev_mm, next_mm, next); } extern void __load_new_mm_context(struct mm_struct *); #ifdef CONFIG_SMP #define check_mmu_context() \ do { \ int cpu = smp_processor_id(); \ cpu_data[cpu].asn_lock = 0; \ barrier(); \ if (cpu_data[cpu].need_new_asn) { \ struct mm_struct * mm = current->active_mm; \ cpu_data[cpu].need_new_asn = 0; \ if (!mm->context[cpu]) \ __load_new_mm_context(mm); \ } \ } while(0) #else #define check_mmu_context() do { } while(0) #endif __EXTERN_INLINE void ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm) { __load_new_mm_context(next_mm); } __EXTERN_INLINE void ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm) { __load_new_mm_context(next_mm); tbiap(); } #ifdef CONFIG_ALPHA_GENERIC # define switch_mm(a,b,c) alpha_mv.mv_switch_mm((a),(b),(c)) # define activate_mm(x,y) alpha_mv.mv_activate_mm((x),(y)) #else # ifdef CONFIG_ALPHA_EV4 # define switch_mm(a,b,c) ev4_switch_mm((a),(b),(c)) # define activate_mm(x,y) ev4_activate_mm((x),(y)) # else # define switch_mm(a,b,c) ev5_switch_mm((a),(b),(c)) # define activate_mm(x,y) ev5_activate_mm((x),(y)) # endif #endif #define init_new_context init_new_context static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int i; for_each_online_cpu(i) mm->context[i] = 0; if (tsk != current) task_thread_info(tsk)->pcb.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; return 0; } #define enter_lazy_tlb enter_lazy_tlb static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { task_thread_info(tsk)->pcb.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; } #include <asm-generic/mmu_context.h> #ifdef __MMU_EXTERN_INLINE #undef __EXTERN_INLINE #undef __MMU_EXTERN_INLINE #endif #endif /* __ALPHA_MMU_CONTEXT_H */ PK ! ���m�, �, core_titan.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_TITAN__H__ #define __ALPHA_TITAN__H__ #include <linux/types.h> #include <asm/compiler.h> /* * TITAN is the internal names for a core logic chipset which provides * memory controller and PCI/AGP access for 21264 based systems. * * This file is based on: * * Titan Chipset Engineering Specification * Revision 0.12 * 13 July 1999 * */ /* XXX: Do we need to conditionalize on this? */ #ifdef USE_48_BIT_KSEG #define TI_BIAS 0x80000000000UL #else #define TI_BIAS 0x10000000000UL #endif /* * CChip, DChip, and PChip registers */ typedef struct { volatile unsigned long csr __attribute__((aligned(64))); } titan_64; typedef struct { titan_64 csc; titan_64 mtr; titan_64 misc; titan_64 mpd; titan_64 aar0; titan_64 aar1; titan_64 aar2; titan_64 aar3; titan_64 dim0; titan_64 dim1; titan_64 dir0; titan_64 dir1; titan_64 drir; titan_64 prben; titan_64 iic0; titan_64 iic1; titan_64 mpr0; titan_64 mpr1; titan_64 mpr2; titan_64 mpr3; titan_64 rsvd[2]; titan_64 ttr; titan_64 tdr; titan_64 dim2; titan_64 dim3; titan_64 dir2; titan_64 dir3; titan_64 iic2; titan_64 iic3; titan_64 pwr; titan_64 reserved[17]; titan_64 cmonctla; titan_64 cmonctlb; titan_64 cmoncnt01; titan_64 cmoncnt23; titan_64 cpen; } titan_cchip; typedef struct { titan_64 dsc; titan_64 str; titan_64 drev; titan_64 dsc2; } titan_dchip; typedef struct { titan_64 wsba[4]; titan_64 wsm[4]; titan_64 tba[4]; titan_64 pctl; titan_64 plat; titan_64 reserved0[2]; union { struct { titan_64 serror; titan_64 serren; titan_64 serrset; titan_64 reserved0; titan_64 gperror; titan_64 gperren; titan_64 gperrset; titan_64 reserved1; titan_64 gtlbiv; titan_64 gtlbia; titan_64 reserved2[2]; titan_64 sctl; titan_64 reserved3[3]; } g; struct { titan_64 agperror; titan_64 agperren; titan_64 agperrset; titan_64 agplastwr; titan_64 aperror; titan_64 aperren; titan_64 aperrset; titan_64 reserved0; titan_64 atlbiv; titan_64 atlbia; titan_64 reserved1[6]; } a; } port_specific; titan_64 sprst; titan_64 reserved1[31]; } titan_pachip_port; typedef struct { titan_pachip_port g_port; titan_pachip_port a_port; } titan_pachip; #define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL)) #define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL)) #define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL)) #define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL)) extern unsigned TITAN_agp; extern int TITAN_bootcpu; /* * TITAN PA-chip Window Space Base Address register. * (WSBA[0-2]) */ #define wsba_m_ena 0x1 #define wsba_m_sg 0x2 #define wsba_m_addr 0xFFF00000 #define wmask_k_sz1gb 0x3FF00000 union TPAchipWSBA { struct { unsigned wsba_v_ena : 1; unsigned wsba_v_sg : 1; unsigned wsba_v_rsvd1 : 18; unsigned wsba_v_addr : 12; unsigned wsba_v_rsvd2 : 32; } wsba_r_bits; int wsba_q_whole [2]; }; /* * TITAN PA-chip Control Register * This definition covers both the G-Port GPCTL and the A-PORT APCTL. * Bits <51:0> are the same in both cases. APCTL<63:52> are only * applicable to AGP. */ #define pctl_m_fbtb 0x00000001 #define pctl_m_thdis 0x00000002 #define pctl_m_chaindis 0x00000004 #define pctl_m_tgtlat 0x00000018 #define pctl_m_hole 0x00000020 #define pctl_m_mwin 0x00000040 #define pctl_m_arbena 0x00000080 #define pctl_m_prigrp 0x0000FF00 #define pctl_m_ppri 0x00010000 #define pctl_m_pcispd66 0x00020000 #define pctl_m_cngstlt 0x003C0000 #define pctl_m_ptpdesten 0x3FC00000 #define pctl_m_dpcen 0x40000000 #define pctl_m_apcen 0x0000000080000000UL #define pctl_m_dcrtv 0x0000000300000000UL #define pctl_m_en_stepping 0x0000000400000000UL #define apctl_m_rsvd1 0x000FFFF800000000UL #define apctl_m_agp_rate 0x0030000000000000UL #define apctl_m_agp_sba_en 0x0040000000000000UL #define apctl_m_agp_en 0x0080000000000000UL #define apctl_m_rsvd2 0x0100000000000000UL #define apctl_m_agp_present 0x0200000000000000UL #define apctl_agp_hp_rd 0x1C00000000000000UL #define apctl_agp_lp_rd 0xE000000000000000UL #define gpctl_m_rsvd 0xFFFFFFF800000000UL union TPAchipPCTL { struct { unsigned pctl_v_fbtb : 1; /* A/G [0] */ unsigned pctl_v_thdis : 1; /* A/G [1] */ unsigned pctl_v_chaindis : 1; /* A/G [2] */ unsigned pctl_v_tgtlat : 2; /* A/G [4:3] */ unsigned pctl_v_hole : 1; /* A/G [5] */ unsigned pctl_v_mwin : 1; /* A/G [6] */ unsigned pctl_v_arbena : 1; /* A/G [7] */ unsigned pctl_v_prigrp : 8; /* A/G [15:8] */ unsigned pctl_v_ppri : 1; /* A/G [16] */ unsigned pctl_v_pcispd66 : 1; /* A/G [17] */ unsigned pctl_v_cngstlt : 4; /* A/G [21:18] */ unsigned pctl_v_ptpdesten : 8; /* A/G [29:22] */ unsigned pctl_v_dpcen : 1; /* A/G [30] */ unsigned pctl_v_apcen : 1; /* A/G [31] */ unsigned pctl_v_dcrtv : 2; /* A/G [33:32] */ unsigned pctl_v_en_stepping :1; /* A/G [34] */ unsigned apctl_v_rsvd1 : 17; /* A [51:35] */ unsigned apctl_v_agp_rate : 2; /* A [53:52] */ unsigned apctl_v_agp_sba_en : 1; /* A [54] */ unsigned apctl_v_agp_en : 1; /* A [55] */ unsigned apctl_v_rsvd2 : 1; /* A [56] */ unsigned apctl_v_agp_present : 1; /* A [57] */ unsigned apctl_v_agp_hp_rd : 3; /* A [60:58] */ unsigned apctl_v_agp_lp_rd : 3; /* A [63:61] */ } pctl_r_bits; unsigned int pctl_l_whole [2]; unsigned long pctl_q_whole; }; /* * SERROR / SERREN / SERRSET */ union TPAchipSERR { struct { unsigned serr_v_lost_uecc : 1; /* [0] */ unsigned serr_v_uecc : 1; /* [1] */ unsigned serr_v_cre : 1; /* [2] */ unsigned serr_v_nxio : 1; /* [3] */ unsigned serr_v_lost_cre : 1; /* [4] */ unsigned serr_v_rsvd0 : 10; /* [14:5] */ unsigned serr_v_addr : 32; /* [46:15] */ unsigned serr_v_rsvd1 : 5; /* [51:47] */ unsigned serr_v_source : 2; /* [53:52] */ unsigned serr_v_cmd : 2; /* [55:54] */ unsigned serr_v_syn : 8; /* [63:56] */ } serr_r_bits; unsigned int serr_l_whole[2]; unsigned long serr_q_whole; }; /* * GPERROR / APERROR / GPERREN / APERREN / GPERRSET / APERRSET */ union TPAchipPERR { struct { unsigned long perr_v_lost : 1; /* [0] */ unsigned long perr_v_serr : 1; /* [1] */ unsigned long perr_v_perr : 1; /* [2] */ unsigned long perr_v_dcrto : 1; /* [3] */ unsigned long perr_v_sge : 1; /* [4] */ unsigned long perr_v_ape : 1; /* [5] */ unsigned long perr_v_ta : 1; /* [6] */ unsigned long perr_v_dpe : 1; /* [7] */ unsigned long perr_v_nds : 1; /* [8] */ unsigned long perr_v_iptpr : 1; /* [9] */ unsigned long perr_v_iptpw : 1; /* [10] */ unsigned long perr_v_rsvd0 : 3; /* [13:11] */ unsigned long perr_v_addr : 33; /* [46:14] */ unsigned long perr_v_dac : 1; /* [47] */ unsigned long perr_v_mwin : 1; /* [48] */ unsigned long perr_v_rsvd1 : 3; /* [51:49] */ unsigned long perr_v_cmd : 4; /* [55:52] */ unsigned long perr_v_rsvd2 : 8; /* [63:56] */ } perr_r_bits; unsigned int perr_l_whole[2]; unsigned long perr_q_whole; }; /* * AGPERROR / AGPERREN / AGPERRSET */ union TPAchipAGPERR { struct { unsigned agperr_v_lost : 1; /* [0] */ unsigned agperr_v_lpqfull : 1; /* [1] */ unsigned apgerr_v_hpqfull : 1; /* [2] */ unsigned agperr_v_rescmd : 1; /* [3] */ unsigned agperr_v_ipte : 1; /* [4] */ unsigned agperr_v_ptp : 1; /* [5] */ unsigned agperr_v_nowindow : 1; /* [6] */ unsigned agperr_v_rsvd0 : 8; /* [14:7] */ unsigned agperr_v_addr : 32; /* [46:15] */ unsigned agperr_v_rsvd1 : 1; /* [47] */ unsigned agperr_v_dac : 1; /* [48] */ unsigned agperr_v_mwin : 1; /* [49] */ unsigned agperr_v_cmd : 3; /* [52:50] */ unsigned agperr_v_length : 6; /* [58:53] */ unsigned agperr_v_fence : 1; /* [59] */ unsigned agperr_v_rsvd2 : 4; /* [63:60] */ } agperr_r_bits; unsigned int agperr_l_whole[2]; unsigned long agperr_q_whole; }; /* * Memory spaces: * Hose numbers are assigned as follows: * 0 - pachip 0 / G Port * 1 - pachip 1 / G Port * 2 - pachip 0 / A Port * 3 - pachip 1 / A Port */ #define TITAN_HOSE_SHIFT (33) #define TITAN_HOSE(h) (((unsigned long)(h)) << TITAN_HOSE_SHIFT) #define TITAN_BASE (IDENT_ADDR + TI_BIAS) #define TITAN_MEM(h) (TITAN_BASE+TITAN_HOSE(h)+0x000000000UL) #define _TITAN_IACK_SC(h) (TITAN_BASE+TITAN_HOSE(h)+0x1F8000000UL) #define TITAN_IO(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FC000000UL) #define TITAN_CONF(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FE000000UL) #define TITAN_HOSE_MASK TITAN_HOSE(3) #define TITAN_IACK_SC _TITAN_IACK_SC(0) /* hack! */ /* * The canonical non-remaped I/O and MEM addresses have these values * subtracted out. This is arranged so that folks manipulating ISA * devices can use their familiar numbers and have them map to bus 0. */ #define TITAN_IO_BIAS TITAN_IO(0) #define TITAN_MEM_BIAS TITAN_MEM(0) /* The IO address space is larger than 0xffff */ #define TITAN_IO_SPACE (TITAN_CONF(0) - TITAN_IO(0)) /* TIG Space */ #define TITAN_TIG_SPACE (TITAN_BASE + 0x100000000UL) /* Offset between ram physical addresses and pci64 DAC bus addresses. */ /* ??? Just a guess. Ought to confirm it hasn't been moved. */ #define TITAN_DAC_OFFSET (1UL << 40) /* * Data structure for handling TITAN machine checks: */ #define SCB_Q_SYSERR 0x620 #define SCB_Q_PROCERR 0x630 #define SCB_Q_SYSMCHK 0x660 #define SCB_Q_PROCMCHK 0x670 #define SCB_Q_SYSEVENT 0x680 /* environmental / system management */ struct el_TITAN_sysdata_mcheck { u64 summary; /* 0x00 */ u64 c_dirx; /* 0x08 */ u64 c_misc; /* 0x10 */ u64 p0_serror; /* 0x18 */ u64 p0_gperror; /* 0x20 */ u64 p0_aperror; /* 0x28 */ u64 p0_agperror;/* 0x30 */ u64 p1_serror; /* 0x38 */ u64 p1_gperror; /* 0x40 */ u64 p1_aperror; /* 0x48 */ u64 p1_agperror;/* 0x50 */ }; /* * System area for a privateer 680 environmental/system management mcheck */ struct el_PRIVATEER_envdata_mcheck { u64 summary; /* 0x00 */ u64 c_dirx; /* 0x08 */ u64 smir; /* 0x10 */ u64 cpuir; /* 0x18 */ u64 psir; /* 0x20 */ u64 fault; /* 0x28 */ u64 sys_doors; /* 0x30 */ u64 temp_warn; /* 0x38 */ u64 fan_ctrl; /* 0x40 */ u64 code; /* 0x48 */ u64 reserved; /* 0x50 */ }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * TITAN, a 21??? PCI/memory support chipset for the EV6 (21264) * can only use linear accesses to get at PCI/AGP memory and I/O spaces. */ /* * Memory functions. all accesses are done through linear space. */ extern void __iomem *titan_ioportmap(unsigned long addr); extern void __iomem *titan_ioremap(unsigned long addr, unsigned long size); extern void titan_iounmap(volatile void __iomem *addr); __EXTERN_INLINE int titan_is_ioaddr(unsigned long addr) { return addr >= TITAN_BASE; } extern int titan_is_mmio(const volatile void __iomem *addr); #undef __IO_PREFIX #define __IO_PREFIX titan #define titan_trivial_rw_bw 1 #define titan_trivial_rw_lq 1 #define titan_trivial_io_bw 1 #define titan_trivial_io_lq 1 #define titan_trivial_iounmap 0 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_TITAN__H__ */ PK ! ���� � err_common.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * linux/include/asm-alpha/err_common.h * * Copyright (C) 2000 Jeff Wiedemeier (Compaq Computer Corporation) * * Contains declarations and macros to support Alpha error handling * implementations. */ #ifndef __ALPHA_ERR_COMMON_H #define __ALPHA_ERR_COMMON_H 1 /* * SCB Vector definitions */ #define SCB_Q_SYSERR 0x620 #define SCB_Q_PROCERR 0x630 #define SCB_Q_SYSMCHK 0x660 #define SCB_Q_PROCMCHK 0x670 #define SCB_Q_SYSEVENT 0x680 /* * Disposition definitions for logout frame parser */ #define MCHK_DISPOSITION_UNKNOWN_ERROR 0x00 #define MCHK_DISPOSITION_REPORT 0x01 #define MCHK_DISPOSITION_DISMISS 0x02 /* * Error Log definitions */ /* * Types */ #define EL_CLASS__TERMINATION (0) # define EL_TYPE__TERMINATION__TERMINATION (0) #define EL_CLASS__HEADER (5) # define EL_TYPE__HEADER__SYSTEM_ERROR_FRAME (1) # define EL_TYPE__HEADER__SYSTEM_EVENT_FRAME (2) # define EL_TYPE__HEADER__HALT_FRAME (3) # define EL_TYPE__HEADER__LOGOUT_FRAME (19) #define EL_CLASS__GENERAL_NOTIFICATION (9) #define EL_CLASS__PCI_ERROR_FRAME (11) #define EL_CLASS__REGATTA_FAMILY (12) # define EL_TYPE__REGATTA__PROCESSOR_ERROR_FRAME (1) # define EL_TYPE__REGATTA__SYSTEM_ERROR_FRAME (2) # define EL_TYPE__REGATTA__ENVIRONMENTAL_FRAME (3) # define EL_TYPE__REGATTA__TITAN_PCHIP0_EXTENDED (8) # define EL_TYPE__REGATTA__TITAN_PCHIP1_EXTENDED (9) # define EL_TYPE__REGATTA__TITAN_MEMORY_EXTENDED (10) # define EL_TYPE__REGATTA__PROCESSOR_DBL_ERROR_HALT (11) # define EL_TYPE__REGATTA__SYSTEM_DBL_ERROR_HALT (12) #define EL_CLASS__PAL (14) # define EL_TYPE__PAL__LOGOUT_FRAME (1) # define EL_TYPE__PAL__EV7_PROCESSOR (4) # define EL_TYPE__PAL__EV7_ZBOX (5) # define EL_TYPE__PAL__EV7_RBOX (6) # define EL_TYPE__PAL__EV7_IO (7) # define EL_TYPE__PAL__ENV__AMBIENT_TEMPERATURE (10) # define EL_TYPE__PAL__ENV__AIRMOVER_FAN (11) # define EL_TYPE__PAL__ENV__VOLTAGE (12) # define EL_TYPE__PAL__ENV__INTRUSION (13) # define EL_TYPE__PAL__ENV__POWER_SUPPLY (14) # define EL_TYPE__PAL__ENV__LAN (15) # define EL_TYPE__PAL__ENV__HOT_PLUG (16) union el_timestamp { struct { u8 second; u8 minute; u8 hour; u8 day; u8 month; u8 year; } b; u64 as_int; }; struct el_subpacket { u16 length; /* length of header (in bytes) */ u16 class; /* header class and type... */ u16 type; /* ...determine content */ u16 revision; /* header revision */ union { struct { /* Class 5, Type 1 - System Error */ u32 frame_length; u32 frame_packet_count; } sys_err; struct { /* Class 5, Type 2 - System Event */ union el_timestamp timestamp; u32 frame_length; u32 frame_packet_count; } sys_event; struct { /* Class 5, Type 3 - Double Error Halt */ u16 halt_code; u16 reserved; union el_timestamp timestamp; u32 frame_length; u32 frame_packet_count; } err_halt; struct { /* Clasee 5, Type 19 - Logout Frame Header */ u32 frame_length; u32 frame_flags; u32 cpu_offset; u32 system_offset; } logout_header; struct { /* Class 12 - Regatta */ u64 cpuid; u64 data_start[1]; } regatta_frame; struct { /* Raw */ u64 data_start[1]; } raw; } by_type; }; #endif /* __ALPHA_ERR_COMMON_H */ PK ! B��U� � checksum.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_CHECKSUM_H #define _ALPHA_CHECKSUM_H #include <linux/in6.h> /* * This is a version of ip_compute_csum() optimized for IP headers, * which always checksum on 4 octet boundaries. */ extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl); /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, __u32 len, __u8 proto, __wsum sum); __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len, __u8 proto, __wsum sum); /* * computes the checksum of a memory block at buff, length len, * and adds in "sum" (32-bit) * * returns a 32-bit number suitable for feeding into itself * or csum_tcpudp_magic * * this function must be called with even lengths, except * for the last fragment, which may be odd * * it's best to have buff aligned on a 32-bit boundary */ extern __wsum csum_partial(const void *buff, int len, __wsum sum); /* * the same as csum_partial, but copies from src while it * checksums * * here even more important to align src and dst on a 32-bit (or even * better 64-bit) boundary */ #define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER #define _HAVE_ARCH_CSUM_AND_COPY __wsum csum_and_copy_from_user(const void __user *src, void *dst, int len); __wsum csum_partial_copy_nocheck(const void *src, void *dst, int len); /* * this routine is used for miscellaneous IP-like checksums, mainly * in icmp.c */ extern __sum16 ip_compute_csum(const void *buff, int len); /* * Fold a partial checksum without adding pseudo headers */ static inline __sum16 csum_fold(__wsum csum) { u32 sum = (__force u32)csum; sum = (sum & 0xffff) + (sum >> 16); sum = (sum & 0xffff) + (sum >> 16); return (__force __sum16)~sum; } #define _HAVE_ARCH_IPV6_CSUM extern __sum16 csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, __u32 len, __u8 proto, __wsum sum); #endif PK ! Pӄ�^ ^ local.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_LOCAL_H #define _ALPHA_LOCAL_H #include <linux/percpu.h> #include <linux/atomic.h> typedef struct { atomic_long_t a; } local_t; #define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } #define local_read(l) atomic_long_read(&(l)->a) #define local_set(l,i) atomic_long_set(&(l)->a, (i)) #define local_inc(l) atomic_long_inc(&(l)->a) #define local_dec(l) atomic_long_dec(&(l)->a) #define local_add(i,l) atomic_long_add((i),(&(l)->a)) #define local_sub(i,l) atomic_long_sub((i),(&(l)->a)) static __inline__ long local_add_return(long i, local_t * l) { long temp, result; __asm__ __volatile__( "1: ldq_l %0,%1\n" " addq %0,%3,%2\n" " addq %0,%3,%0\n" " stq_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (l->a.counter), "=&r" (result) :"Ir" (i), "m" (l->a.counter) : "memory"); return result; } static __inline__ long local_sub_return(long i, local_t * l) { long temp, result; __asm__ __volatile__( "1: ldq_l %0,%1\n" " subq %0,%3,%2\n" " subq %0,%3,%0\n" " stq_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (l->a.counter), "=&r" (result) :"Ir" (i), "m" (l->a.counter) : "memory"); return result; } #define local_cmpxchg(l, o, n) \ (cmpxchg_local(&((l)->a.counter), (o), (n))) #define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n))) /** * local_add_unless - add unless the number is a given value * @l: pointer of type local_t * @a: the amount to add to l... * @u: ...unless l is equal to u. * * Atomically adds @a to @l, so long as it was not @u. * Returns non-zero if @l was not @u, and zero otherwise. */ #define local_add_unless(l, a, u) \ ({ \ long c, old; \ c = local_read(l); \ for (;;) { \ if (unlikely(c == (u))) \ break; \ old = local_cmpxchg((l), c, c + (a)); \ if (likely(old == c)) \ break; \ c = old; \ } \ c != (u); \ }) #define local_inc_not_zero(l) local_add_unless((l), 1, 0) #define local_add_negative(a, l) (local_add_return((a), (l)) < 0) #define local_dec_return(l) local_sub_return(1,(l)) #define local_inc_return(l) local_add_return(1,(l)) #define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0) #define local_inc_and_test(l) (local_add_return(1, (l)) == 0) #define local_dec_and_test(l) (local_sub_return(1, (l)) == 0) /* Verify if faster than atomic ops */ #define __local_inc(l) ((l)->a.counter++) #define __local_dec(l) ((l)->a.counter++) #define __local_add(i,l) ((l)->a.counter+=(i)) #define __local_sub(i,l) ((l)->a.counter-=(i)) #endif /* _ALPHA_LOCAL_H */ PK ! 3z1V V dma-mapping.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_DMA_MAPPING_H #define _ALPHA_DMA_MAPPING_H extern const struct dma_map_ops alpha_pci_ops; static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) { #ifdef CONFIG_ALPHA_JENSEN return NULL; #else return &alpha_pci_ops; #endif } #endif /* _ALPHA_DMA_MAPPING_H */ PK ! �0F� � futex.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ALPHA_FUTEX_H #define _ASM_ALPHA_FUTEX_H #ifdef __KERNEL__ #include <linux/futex.h> #include <linux/uaccess.h> #include <asm/errno.h> #include <asm/barrier.h> #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ __asm__ __volatile__( \ __ASM_SMP_MB \ "1: ldl_l %0,0(%2)\n" \ insn \ "2: stl_c %1,0(%2)\n" \ " beq %1,4f\n" \ " mov $31,%1\n" \ "3: .subsection 2\n" \ "4: br 1b\n" \ " .previous\n" \ EXC(1b,3b,$31,%1) \ EXC(2b,3b,$31,%1) \ : "=&r" (oldval), "=&r"(ret) \ : "r" (uaddr), "r"(oparg) \ : "memory") static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) { int oldval = 0, ret; if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; switch (op) { case FUTEX_OP_SET: __futex_atomic_op("mov %3,%1\n", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ADD: __futex_atomic_op("addl %0,%3,%1\n", ret, oldval, uaddr, oparg); break; case FUTEX_OP_OR: __futex_atomic_op("or %0,%3,%1\n", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ANDN: __futex_atomic_op("andnot %0,%3,%1\n", ret, oldval, uaddr, oparg); break; case FUTEX_OP_XOR: __futex_atomic_op("xor %0,%3,%1\n", ret, oldval, uaddr, oparg); break; default: ret = -ENOSYS; } if (!ret) *oval = oldval; return ret; } static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { int ret = 0, cmp; u32 prev; if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; __asm__ __volatile__ ( __ASM_SMP_MB "1: ldl_l %1,0(%3)\n" " cmpeq %1,%4,%2\n" " beq %2,3f\n" " mov %5,%2\n" "2: stl_c %2,0(%3)\n" " beq %2,4f\n" "3: .subsection 2\n" "4: br 1b\n" " .previous\n" EXC(1b,3b,$31,%0) EXC(2b,3b,$31,%0) : "+r"(ret), "=&r"(prev), "=&r"(cmp) : "r"(uaddr), "r"((long)(int)oldval), "r"(newval) : "memory"); *uval = prev; return ret; } #endif /* __KERNEL__ */ #endif /* _ASM_ALPHA_FUTEX_H */ PK ! ��T�' ' mce.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_MCE_H #define __ALPHA_MCE_H /* * This is the logout header that should be common to all platforms * (assuming they are running OSF/1 PALcode, I guess). */ struct el_common { unsigned int size; /* size in bytes of logout area */ unsigned int sbz1 : 30; /* should be zero */ unsigned int err2 : 1; /* second error */ unsigned int retry : 1; /* retry flag */ unsigned int proc_offset; /* processor-specific offset */ unsigned int sys_offset; /* system-specific offset */ unsigned int code; /* machine check code */ unsigned int frame_rev; /* frame revision */ }; /* Machine Check Frame for uncorrectable errors (Large format) * --- This is used to log uncorrectable errors such as * double bit ECC errors. * --- These errors are detected by both processor and systems. */ struct el_common_EV5_uncorrectable_mcheck { unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */ unsigned long paltemp[24]; /* PAL TEMP REGS. */ unsigned long exc_addr; /* Address of excepting instruction*/ unsigned long exc_sum; /* Summary of arithmetic traps. */ unsigned long exc_mask; /* Exception mask (from exc_sum). */ unsigned long pal_base; /* Base address for PALcode. */ unsigned long isr; /* Interrupt Status Reg. */ unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */ unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity <12> set TAG parity*/ unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1: <2> Data error in bank 0 <3> Data error in bank 1 <4> Tag error in bank 0 <5> Tag error in bank 1 */ unsigned long va; /* Effective VA of fault or miss. */ unsigned long mm_stat; /* Holds the reason for D-stream fault or D-cache parity errors */ unsigned long sc_addr; /* Address that was being accessed when EV5 detected Secondary cache failure. */ unsigned long sc_stat; /* Helps determine if the error was TAG/Data parity(Secondary Cache)*/ unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */ unsigned long ei_addr; /* Physical address of any transfer that is logged in EV5 EI_STAT */ unsigned long fill_syndrome; /* For correcting ECC errors. */ unsigned long ei_stat; /* Helps identify reason of any processor uncorrectable error at its external interface. */ unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/ }; struct el_common_EV6_mcheck { unsigned int FrameSize; /* Bytes, including this field */ unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */ unsigned int CpuOffset; /* Offset to CPU-specific info */ unsigned int SystemOffset; /* Offset to system-specific info */ unsigned int MCHK_Code; unsigned int MCHK_Frame_Rev; unsigned long I_STAT; /* EV6 Internal Processor Registers */ unsigned long DC_STAT; /* (See the 21264 Spec) */ unsigned long C_ADDR; unsigned long DC1_SYNDROME; unsigned long DC0_SYNDROME; unsigned long C_STAT; unsigned long C_STS; unsigned long MM_STAT; unsigned long EXC_ADDR; unsigned long IER_CM; unsigned long ISUM; unsigned long RESERVED0; unsigned long PAL_BASE; unsigned long I_CTL; unsigned long PCTX; }; #endif /* __ALPHA_MCE_H */ PK ! �<x� � compiler.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_COMPILER_H #define __ALPHA_COMPILER_H #include <uapi/asm/compiler.h> #endif /* __ALPHA_COMPILER_H */ PK ! AH> vga.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Access to VGA videoram * * (c) 1998 Martin Mares <mj@ucw.cz> */ #ifndef _LINUX_ASM_VGA_H_ #define _LINUX_ASM_VGA_H_ #include <asm/io.h> #define VT_BUF_HAVE_RW #define VT_BUF_HAVE_MEMSETW #define VT_BUF_HAVE_MEMCPYW static inline void scr_writew(u16 val, volatile u16 *addr) { if (__is_ioaddr(addr)) __raw_writew(val, (volatile u16 __iomem *) addr); else *addr = val; } static inline u16 scr_readw(volatile const u16 *addr) { if (__is_ioaddr(addr)) return __raw_readw((volatile const u16 __iomem *) addr); else return *addr; } static inline void scr_memsetw(u16 *s, u16 c, unsigned int count) { if (__is_ioaddr(s)) memsetw_io((u16 __iomem *) s, c, count); else memset16(s, c, count / 2); } /* Do not trust that the usage will be correct; analyze the arguments. */ extern void scr_memcpyw(u16 *d, const u16 *s, unsigned int count); /* ??? These are currently only used for downloading character sets. As such, they don't need memory barriers. Is this all they are intended to be used for? */ #define vga_readb(a) readb((u8 __iomem *)(a)) #define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a)) #ifdef CONFIG_VGA_HOSE #include <linux/ioport.h> #include <linux/pci.h> extern struct pci_controller *pci_vga_hose; # define __is_port_vga(a) \ (((a) >= 0x3b0) && ((a) < 0x3e0) && \ ((a) != 0x3b3) && ((a) != 0x3d3)) # define __is_mem_vga(a) \ (((a) >= 0xa0000) && ((a) <= 0xc0000)) # define FIXUP_IOADDR_VGA(a) do { \ if (pci_vga_hose && __is_port_vga(a)) \ (a) += pci_vga_hose->io_space->start; \ } while(0) # define FIXUP_MEMADDR_VGA(a) do { \ if (pci_vga_hose && __is_mem_vga(a)) \ (a) += pci_vga_hose->mem_space->start; \ } while(0) #else /* CONFIG_VGA_HOSE */ # define pci_vga_hose 0 # define __is_port_vga(a) 0 # define __is_mem_vga(a) 0 # define FIXUP_IOADDR_VGA(a) # define FIXUP_MEMADDR_VGA(a) #endif /* CONFIG_VGA_HOSE */ #define VGA_MAP_MEM(x,s) ((unsigned long) ioremap(x, s)) #endif PK ! z��x x err_ev7.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_ERR_EV7_H #define __ALPHA_ERR_EV7_H 1 /* * Data for el packet class PAL (14), type LOGOUT_FRAME (1) */ struct ev7_pal_logout_subpacket { u32 mchk_code; u32 subpacket_count; u64 whami; u64 rbox_whami; u64 rbox_int; u64 exc_addr; union el_timestamp timestamp; u64 halt_code; u64 reserved; }; /* * Data for el packet class PAL (14), type EV7_PROCESSOR (4) */ struct ev7_pal_processor_subpacket { u64 i_stat; u64 dc_stat; u64 c_addr; u64 c_syndrome_1; u64 c_syndrome_0; u64 c_stat; u64 c_sts; u64 mm_stat; u64 exc_addr; u64 ier_cm; u64 isum; u64 pal_base; u64 i_ctl; u64 process_context; u64 cbox_ctl; u64 cbox_stp_ctl; u64 cbox_acc_ctl; u64 cbox_lcl_set; u64 cbox_gbl_set; u64 bbox_ctl; u64 bbox_err_sts; u64 bbox_err_idx; u64 cbox_ddp_err_sts; u64 bbox_dat_rmp; u64 reserved[2]; }; /* * Data for el packet class PAL (14), type EV7_ZBOX (5) */ struct ev7_pal_zbox_subpacket { u32 zbox0_dram_err_status_1; u32 zbox0_dram_err_status_2; u32 zbox0_dram_err_status_3; u32 zbox0_dram_err_ctl; u32 zbox0_dram_err_adr; u32 zbox0_dift_timeout; u32 zbox0_dram_mapper_ctl; u32 zbox0_frc_err_adr; u32 zbox0_dift_err_status; u32 reserved1; u32 zbox1_dram_err_status_1; u32 zbox1_dram_err_status_2; u32 zbox1_dram_err_status_3; u32 zbox1_dram_err_ctl; u32 zbox1_dram_err_adr; u32 zbox1_dift_timeout; u32 zbox1_dram_mapper_ctl; u32 zbox1_frc_err_adr; u32 zbox1_dift_err_status; u32 reserved2; u64 cbox_ctl; u64 cbox_stp_ctl; u64 zbox0_error_pa; u64 zbox1_error_pa; u64 zbox0_ored_syndrome; u64 zbox1_ored_syndrome; u64 reserved3[2]; }; /* * Data for el packet class PAL (14), type EV7_RBOX (6) */ struct ev7_pal_rbox_subpacket { u64 rbox_cfg; u64 rbox_n_cfg; u64 rbox_s_cfg; u64 rbox_e_cfg; u64 rbox_w_cfg; u64 rbox_n_err; u64 rbox_s_err; u64 rbox_e_err; u64 rbox_w_err; u64 rbox_io_cfg; u64 rbox_io_err; u64 rbox_l_err; u64 rbox_whoami; u64 rbox_imask; u64 rbox_intq; u64 rbox_int; u64 reserved[2]; }; /* * Data for el packet class PAL (14), type EV7_IO (7) */ struct ev7_pal_io_one_port { u64 pox_err_sum; u64 pox_tlb_err; u64 pox_spl_cmplt; u64 pox_trans_sum; u64 pox_first_err; u64 pox_mult_err; u64 pox_dm_source; u64 pox_dm_dest; u64 pox_dm_size; u64 pox_dm_ctrl; u64 reserved; }; struct ev7_pal_io_subpacket { u64 io_asic_rev; u64 io_sys_rev; u64 io7_uph; u64 hpi_ctl; u64 crd_ctl; u64 hei_ctl; u64 po7_error_sum; u64 po7_uncrr_sym; u64 po7_crrct_sym; u64 po7_ugbge_sym; u64 po7_err_pkt0; u64 po7_err_pkt1; u64 reserved[2]; struct ev7_pal_io_one_port ports[4]; }; /* * Environmental subpacket. Data used for el packets: * class PAL (14), type AMBIENT_TEMPERATURE (10) * class PAL (14), type AIRMOVER_FAN (11) * class PAL (14), type VOLTAGE (12) * class PAL (14), type INTRUSION (13) * class PAL (14), type POWER_SUPPLY (14) * class PAL (14), type LAN (15) * class PAL (14), type HOT_PLUG (16) */ struct ev7_pal_environmental_subpacket { u16 cabinet; u16 drawer; u16 reserved1[2]; u8 module_type; u8 unit_id; /* unit reporting condition */ u8 reserved2; u8 condition; /* condition reported */ }; /* * Convert environmental type to index */ static inline int ev7_lf_env_index(int type) { BUG_ON((type < EL_TYPE__PAL__ENV__AMBIENT_TEMPERATURE) || (type > EL_TYPE__PAL__ENV__HOT_PLUG)); return type - EL_TYPE__PAL__ENV__AMBIENT_TEMPERATURE; } /* * Data for generic el packet class PAL. */ struct ev7_pal_subpacket { union { struct ev7_pal_logout_subpacket logout; /* Type 1 */ struct ev7_pal_processor_subpacket ev7; /* Type 4 */ struct ev7_pal_zbox_subpacket zbox; /* Type 5 */ struct ev7_pal_rbox_subpacket rbox; /* Type 6 */ struct ev7_pal_io_subpacket io; /* Type 7 */ struct ev7_pal_environmental_subpacket env; /* Type 10-16 */ u64 as_quad[1]; /* Raw u64 */ } by_type; }; /* * Struct to contain collected logout from subpackets. */ struct ev7_lf_subpackets { struct ev7_pal_logout_subpacket *logout; /* Type 1 */ struct ev7_pal_processor_subpacket *ev7; /* Type 4 */ struct ev7_pal_zbox_subpacket *zbox; /* Type 5 */ struct ev7_pal_rbox_subpacket *rbox; /* Type 6 */ struct ev7_pal_io_subpacket *io; /* Type 7 */ struct ev7_pal_environmental_subpacket *env[7]; /* Type 10-16 */ unsigned int io_pid; }; #endif /* __ALPHA_ERR_EV7_H */ PK ! ���F� � core_irongate.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_IRONGATE__H__ #define __ALPHA_IRONGATE__H__ #include <linux/types.h> #include <asm/compiler.h> /* * IRONGATE is the internal name for the AMD-751 K7 core logic chipset * which provides memory controller and PCI access for NAUTILUS-based * EV6 (21264) systems. * * This file is based on: * * IronGate management library, (c) 1999 Alpha Processor, Inc. * Copyright (C) 1999 Alpha Processor, Inc., * (David Daniel, Stig Telfer, Soohoon Lee) */ /* * The 21264 supports, and internally recognizes, a 44-bit physical * address space that is divided equally between memory address space * and I/O address space. Memory address space resides in the lower * half of the physical address space (PA[43]=0) and I/O address space * resides in the upper half of the physical address space (PA[43]=1). */ /* * Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access * through the routines given is 32-bit. * * The first 0x40 bytes are standard as per the PCI spec. */ typedef volatile __u32 igcsr32; typedef struct { igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */ igcsr32 stat_cmd; /* 0x04 - status, command */ igcsr32 class; /* 0x08 - class code, rev ID */ igcsr32 latency; /* 0x0C - header type, PCI latency */ igcsr32 bar0; /* 0x10 - BAR0 - AGP */ igcsr32 bar1; /* 0x14 - BAR1 - GART */ igcsr32 bar2; /* 0x18 - Power Management reg block */ igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */ igcsr32 capptr; /* 0x34 - Capabilities pointer */ igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */ igcsr32 bacsr10; /* 0x40 - base address chip selects */ igcsr32 bacsr32; /* 0x44 - base address chip selects */ igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects 761: ECC, mode/status */ igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */ igcsr32 drammap; /* 0x50 - address mapping control */ igcsr32 dramtm; /* 0x54 - timing, driver strength */ igcsr32 dramms; /* 0x58 - DRAM mode/status */ igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */ igcsr32 biu0; /* 0x60 - bus interface unit */ igcsr32 biusip; /* 0x64 - Serial initialisation pkt */ igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */ igcsr32 mro; /* 0x70 - memory request optimiser */ igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */ igcsr32 whami; /* 0x80 - who am I */ igcsr32 pciarb; /* 0x84 - PCI arbitration control */ igcsr32 pcicfg; /* 0x88 - PCI config status */ igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */ igcsr32 pci_mem; /* 0x9C - PCI top of memory, 761 only */ /* AGP (bus 1) control registers */ igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */ igcsr32 agpstat; /* 0xA4 - AGP status register */ igcsr32 agpcmd; /* 0xA8 - AGP control register */ igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */ igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */ } Irongate0; typedef struct { igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */ igcsr32 stat_cmd; /* 0x04 - Status and Command regs */ igcsr32 class; /* 0x08 - subclass, baseclass etc */ igcsr32 htype; /* 0x0C - header type (at 0x0E) */ igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */ igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */ igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */ igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */ igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */ igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */ igcsr32 io_baselim; /* 0x30 - IO base, IO limit */ igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */ igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */ } Irongate1; extern igcsr32 *IronECC; /* * Memory spaces: */ /* Irongate is consistent with a subset of the Tsunami memory map */ #ifdef USE_48_BIT_KSEG #define IRONGATE_BIAS 0x80000000000UL #else #define IRONGATE_BIAS 0x10000000000UL #endif #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL) #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL) #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL) #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL) /* * PCI Configuration space accesses are formed like so: * * 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 : * : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 : * ---bus numer--- -device-- -fun- ---register---- */ #define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \ ((dev)<<11) | \ ((fun)<<8) | \ (reg) ) #define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0)) #define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0)) /* * Data structure for handling IRONGATE machine checks: * This is the standard OSF logout frame */ #define SCB_Q_SYSERR 0x620 /* OSF definitions */ #define SCB_Q_PROCERR 0x630 #define SCB_Q_SYSMCHK 0x660 #define SCB_Q_PROCMCHK 0x670 struct el_IRONGATE_sysdata_mcheck { __u32 FrameSize; /* Bytes, including this field */ __u32 FrameFlags; /* <31> = Retry, <30> = Second Error */ __u32 CpuOffset; /* Offset to CPU-specific into */ __u32 SystemOffset; /* Offset to system-specific info */ __u32 MCHK_Code; __u32 MCHK_Frame_Rev; __u64 I_STAT; __u64 DC_STAT; __u64 C_ADDR; __u64 DC1_SYNDROME; __u64 DC0_SYNDROME; __u64 C_STAT; __u64 C_STS; __u64 RESERVED0; __u64 EXC_ADDR; __u64 IER_CM; __u64 ISUM; __u64 MM_STAT; __u64 PAL_BASE; __u64 I_CTL; __u64 PCTX; }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and * K7 can only use linear accesses to get at PCI memory and I/O spaces. */ /* * Memory functions. All accesses are done through linear space. */ __EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr) { return (void __iomem *)(addr + IRONGATE_IO); } extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size); extern void irongate_iounmap(volatile void __iomem *addr); __EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr) { return addr >= IRONGATE_MEM; } __EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr; return addr < IRONGATE_IO || addr >= IRONGATE_CONF; } #undef __IO_PREFIX #define __IO_PREFIX irongate #define irongate_trivial_rw_bw 1 #define irongate_trivial_rw_lq 1 #define irongate_trivial_io_bw 1 #define irongate_trivial_io_lq 1 #define irongate_trivial_iounmap 0 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_IRONGATE__H__ */ PK ! ���%� � hwrpb.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_HWRPB_H #define __ALPHA_HWRPB_H #define INIT_HWRPB ((struct hwrpb_struct *) 0x10000000) /* * DEC processor types for Alpha systems. Found in HWRPB. * These values are architected. */ #define EV3_CPU 1 /* EV3 */ #define EV4_CPU 2 /* EV4 (21064) */ #define LCA4_CPU 4 /* LCA4 (21066/21068) */ #define EV5_CPU 5 /* EV5 (21164) */ #define EV45_CPU 6 /* EV4.5 (21064/xxx) */ #define EV56_CPU 7 /* EV5.6 (21164) */ #define EV6_CPU 8 /* EV6 (21264) */ #define PCA56_CPU 9 /* PCA56 (21164PC) */ #define PCA57_CPU 10 /* PCA57 (notyet) */ #define EV67_CPU 11 /* EV67 (21264A) */ #define EV68CB_CPU 12 /* EV68CB (21264C) */ #define EV68AL_CPU 13 /* EV68AL (21264B) */ #define EV68CX_CPU 14 /* EV68CX (21264D) */ #define EV7_CPU 15 /* EV7 (21364) */ #define EV79_CPU 16 /* EV79 (21364??) */ #define EV69_CPU 17 /* EV69 (21264/EV69A) */ /* * DEC system types for Alpha systems. Found in HWRPB. * These values are architected. */ #define ST_ADU 1 /* Alpha ADU systype */ #define ST_DEC_4000 2 /* Cobra systype */ #define ST_DEC_7000 3 /* Ruby systype */ #define ST_DEC_3000_500 4 /* Flamingo systype */ #define ST_DEC_2000_300 6 /* Jensen systype */ #define ST_DEC_3000_300 7 /* Pelican systype */ #define ST_DEC_2100_A500 9 /* Sable systype */ #define ST_DEC_AXPVME_64 10 /* AXPvme system type */ #define ST_DEC_AXPPCI_33 11 /* NoName system type */ #define ST_DEC_TLASER 12 /* Turbolaser systype */ #define ST_DEC_2100_A50 13 /* Avanti systype */ #define ST_DEC_MUSTANG 14 /* Mustang systype */ #define ST_DEC_ALCOR 15 /* Alcor (EV5) systype */ #define ST_DEC_1000 17 /* Mikasa systype */ #define ST_DEC_EB64 18 /* EB64 systype */ #define ST_DEC_EB66 19 /* EB66 systype */ #define ST_DEC_EB64P 20 /* EB64+ systype */ #define ST_DEC_BURNS 21 /* laptop systype */ #define ST_DEC_RAWHIDE 22 /* Rawhide systype */ #define ST_DEC_K2 23 /* K2 systype */ #define ST_DEC_LYNX 24 /* Lynx systype */ #define ST_DEC_XL 25 /* Alpha XL systype */ #define ST_DEC_EB164 26 /* EB164 systype */ #define ST_DEC_NORITAKE 27 /* Noritake systype */ #define ST_DEC_CORTEX 28 /* Cortex systype */ #define ST_DEC_MIATA 30 /* Miata systype */ #define ST_DEC_XXM 31 /* XXM systype */ #define ST_DEC_TAKARA 32 /* Takara systype */ #define ST_DEC_YUKON 33 /* Yukon systype */ #define ST_DEC_TSUNAMI 34 /* Tsunami systype */ #define ST_DEC_WILDFIRE 35 /* Wildfire systype */ #define ST_DEC_CUSCO 36 /* CUSCO systype */ #define ST_DEC_EIGER 37 /* Eiger systype */ #define ST_DEC_TITAN 38 /* Titan systype */ #define ST_DEC_MARVEL 39 /* Marvel systype */ /* UNOFFICIAL!!! */ #define ST_UNOFFICIAL_BIAS 100 #define ST_DTI_RUFFIAN 101 /* RUFFIAN systype */ /* Alpha Processor, Inc. systems */ #define ST_API_BIAS 200 #define ST_API_NAUTILUS 201 /* UP1000 systype */ struct pcb_struct { unsigned long ksp; unsigned long usp; unsigned long ptbr; unsigned int pcc; unsigned int asn; unsigned long unique; unsigned long flags; unsigned long res1, res2; }; struct percpu_struct { unsigned long hwpcb[16]; unsigned long flags; unsigned long pal_mem_size; unsigned long pal_scratch_size; unsigned long pal_mem_pa; unsigned long pal_scratch_pa; unsigned long pal_revision; unsigned long type; unsigned long variation; unsigned long revision; unsigned long serial_no[2]; unsigned long logout_area_pa; unsigned long logout_area_len; unsigned long halt_PCBB; unsigned long halt_PC; unsigned long halt_PS; unsigned long halt_arg; unsigned long halt_ra; unsigned long halt_pv; unsigned long halt_reason; unsigned long res; unsigned long ipc_buffer[21]; unsigned long palcode_avail[16]; unsigned long compatibility; unsigned long console_data_log_pa; unsigned long console_data_log_length; unsigned long bcache_info; }; struct procdesc_struct { unsigned long weird_vms_stuff; unsigned long address; }; struct vf_map_struct { unsigned long va; unsigned long pa; unsigned long count; }; struct crb_struct { struct procdesc_struct * dispatch_va; struct procdesc_struct * dispatch_pa; struct procdesc_struct * fixup_va; struct procdesc_struct * fixup_pa; /* virtual->physical map */ unsigned long map_entries; unsigned long map_pages; struct vf_map_struct map[1]; }; struct memclust_struct { unsigned long start_pfn; unsigned long numpages; unsigned long numtested; unsigned long bitmap_va; unsigned long bitmap_pa; unsigned long bitmap_chksum; unsigned long usage; }; struct memdesc_struct { unsigned long chksum; unsigned long optional_pa; unsigned long numclusters; struct memclust_struct cluster[0]; }; struct dsr_struct { long smm; /* SMM nubber used by LMF */ unsigned long lurt_off; /* offset to LURT table */ unsigned long sysname_off; /* offset to sysname char count */ }; struct hwrpb_struct { unsigned long phys_addr; /* check: physical address of the hwrpb */ unsigned long id; /* check: "HWRPB\0\0\0" */ unsigned long revision; unsigned long size; /* size of hwrpb */ unsigned long cpuid; unsigned long pagesize; /* 8192, I hope */ unsigned long pa_bits; /* number of physical address bits */ unsigned long max_asn; unsigned char ssn[16]; /* system serial number: big bother is watching */ unsigned long sys_type; unsigned long sys_variation; unsigned long sys_revision; unsigned long intr_freq; /* interval clock frequency * 4096 */ unsigned long cycle_freq; /* cycle counter frequency */ unsigned long vptb; /* Virtual Page Table Base address */ unsigned long res1; unsigned long tbhb_offset; /* Translation Buffer Hint Block */ unsigned long nr_processors; unsigned long processor_size; unsigned long processor_offset; unsigned long ctb_nr; unsigned long ctb_size; /* console terminal block size */ unsigned long ctbt_offset; /* console terminal block table offset */ unsigned long crb_offset; /* console callback routine block */ unsigned long mddt_offset; /* memory data descriptor table */ unsigned long cdb_offset; /* configuration data block (or NULL) */ unsigned long frut_offset; /* FRU table (or NULL) */ void (*save_terminal)(unsigned long); unsigned long save_terminal_data; void (*restore_terminal)(unsigned long); unsigned long restore_terminal_data; void (*CPU_restart)(unsigned long); unsigned long CPU_restart_data; unsigned long res2; unsigned long res3; unsigned long chksum; unsigned long rxrdy; unsigned long txrdy; unsigned long dsr_offset; /* "Dynamic System Recognition Data Block Table" */ }; #ifdef __KERNEL__ extern struct hwrpb_struct *hwrpb; static inline void hwrpb_update_checksum(struct hwrpb_struct *h) { unsigned long sum = 0, *l; for (l = (unsigned long *) h; l < (unsigned long *) &h->chksum; ++l) sum += *l; h->chksum = sum; } #endif /* __KERNEL__ */ #endif /* __ALPHA_HWRPB_H */ PK ! �{ӕ-" -" atomic.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_ATOMIC_H #define _ALPHA_ATOMIC_H #include <linux/types.h> #include <asm/barrier.h> #include <asm/cmpxchg.h> /* * Atomic operations that C can't guarantee us. Useful for * resource counting etc... * * But use these as seldom as possible since they are much slower * than regular operations. */ /* * To ensure dependency ordering is preserved for the _relaxed and * _release atomics, an smp_mb() is unconditionally inserted into the * _relaxed variants, which are used to build the barriered versions. * Avoid redundant back-to-back fences in the _acquire and _fence * versions. */ #define __atomic_acquire_fence() #define __atomic_post_full_fence() #define ATOMIC64_INIT(i) { (i) } #define arch_atomic_read(v) READ_ONCE((v)->counter) #define arch_atomic64_read(v) READ_ONCE((v)->counter) #define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i)) #define arch_atomic64_set(v,i) WRITE_ONCE((v)->counter, (i)) /* * To get proper branch prediction for the main line, we must branch * forward to code at the end of this object's .text section, then * branch back to restart the operation. */ #define ATOMIC_OP(op, asm_op) \ static __inline__ void arch_atomic_##op(int i, atomic_t * v) \ { \ unsigned long temp; \ __asm__ __volatile__( \ "1: ldl_l %0,%1\n" \ " " #asm_op " %0,%2,%0\n" \ " stl_c %0,%1\n" \ " beq %0,2f\n" \ ".subsection 2\n" \ "2: br 1b\n" \ ".previous" \ :"=&r" (temp), "=m" (v->counter) \ :"Ir" (i), "m" (v->counter)); \ } \ #define ATOMIC_OP_RETURN(op, asm_op) \ static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \ { \ long temp, result; \ __asm__ __volatile__( \ "1: ldl_l %0,%1\n" \ " " #asm_op " %0,%3,%2\n" \ " " #asm_op " %0,%3,%0\n" \ " stl_c %0,%1\n" \ " beq %0,2f\n" \ ".subsection 2\n" \ "2: br 1b\n" \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ smp_mb(); \ return result; \ } #define ATOMIC_FETCH_OP(op, asm_op) \ static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \ { \ long temp, result; \ __asm__ __volatile__( \ "1: ldl_l %2,%1\n" \ " " #asm_op " %2,%3,%0\n" \ " stl_c %0,%1\n" \ " beq %0,2f\n" \ ".subsection 2\n" \ "2: br 1b\n" \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ smp_mb(); \ return result; \ } #define ATOMIC64_OP(op, asm_op) \ static __inline__ void arch_atomic64_##op(s64 i, atomic64_t * v) \ { \ s64 temp; \ __asm__ __volatile__( \ "1: ldq_l %0,%1\n" \ " " #asm_op " %0,%2,%0\n" \ " stq_c %0,%1\n" \ " beq %0,2f\n" \ ".subsection 2\n" \ "2: br 1b\n" \ ".previous" \ :"=&r" (temp), "=m" (v->counter) \ :"Ir" (i), "m" (v->counter)); \ } \ #define ATOMIC64_OP_RETURN(op, asm_op) \ static __inline__ s64 \ arch_atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \ { \ s64 temp, result; \ __asm__ __volatile__( \ "1: ldq_l %0,%1\n" \ " " #asm_op " %0,%3,%2\n" \ " " #asm_op " %0,%3,%0\n" \ " stq_c %0,%1\n" \ " beq %0,2f\n" \ ".subsection 2\n" \ "2: br 1b\n" \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ smp_mb(); \ return result; \ } #define ATOMIC64_FETCH_OP(op, asm_op) \ static __inline__ s64 \ arch_atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \ { \ s64 temp, result; \ __asm__ __volatile__( \ "1: ldq_l %2,%1\n" \ " " #asm_op " %2,%3,%0\n" \ " stq_c %0,%1\n" \ " beq %0,2f\n" \ ".subsection 2\n" \ "2: br 1b\n" \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ smp_mb(); \ return result; \ } #define ATOMIC_OPS(op) \ ATOMIC_OP(op, op##l) \ ATOMIC_OP_RETURN(op, op##l) \ ATOMIC_FETCH_OP(op, op##l) \ ATOMIC64_OP(op, op##q) \ ATOMIC64_OP_RETURN(op, op##q) \ ATOMIC64_FETCH_OP(op, op##q) ATOMIC_OPS(add) ATOMIC_OPS(sub) #define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed #define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed #define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed #define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed #define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed #define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed #define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed #define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed #define arch_atomic_andnot arch_atomic_andnot #define arch_atomic64_andnot arch_atomic64_andnot #undef ATOMIC_OPS #define ATOMIC_OPS(op, asm) \ ATOMIC_OP(op, asm) \ ATOMIC_FETCH_OP(op, asm) \ ATOMIC64_OP(op, asm) \ ATOMIC64_FETCH_OP(op, asm) ATOMIC_OPS(and, and) ATOMIC_OPS(andnot, bic) ATOMIC_OPS(or, bis) ATOMIC_OPS(xor, xor) #define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed #define arch_atomic_fetch_andnot_relaxed arch_atomic_fetch_andnot_relaxed #define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed #define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed #define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed #define arch_atomic64_fetch_andnot_relaxed arch_atomic64_fetch_andnot_relaxed #define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed #define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed #undef ATOMIC_OPS #undef ATOMIC64_FETCH_OP #undef ATOMIC64_OP_RETURN #undef ATOMIC64_OP #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN #undef ATOMIC_OP #define arch_atomic64_cmpxchg(v, old, new) \ (arch_cmpxchg(&((v)->counter), old, new)) #define arch_atomic64_xchg(v, new) \ (arch_xchg(&((v)->counter), new)) #define arch_atomic_cmpxchg(v, old, new) \ (arch_cmpxchg(&((v)->counter), old, new)) #define arch_atomic_xchg(v, new) \ (arch_xchg(&((v)->counter), new)) /** * arch_atomic_fetch_add_unless - add unless the number is a given value * @v: pointer of type atomic_t * @a: the amount to add to v... * @u: ...unless v is equal to u. * * Atomically adds @a to @v, so long as it was not @u. * Returns the old value of @v. */ static __inline__ int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u) { int c, new, old; smp_mb(); __asm__ __volatile__( "1: ldl_l %[old],%[mem]\n" " cmpeq %[old],%[u],%[c]\n" " addl %[old],%[a],%[new]\n" " bne %[c],2f\n" " stl_c %[new],%[mem]\n" " beq %[new],3f\n" "2:\n" ".subsection 2\n" "3: br 1b\n" ".previous" : [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c) : [mem] "m"(*v), [a] "rI"(a), [u] "rI"((long)u) : "memory"); smp_mb(); return old; } #define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless /** * arch_atomic64_fetch_add_unless - add unless the number is a given value * @v: pointer of type atomic64_t * @a: the amount to add to v... * @u: ...unless v is equal to u. * * Atomically adds @a to @v, so long as it was not @u. * Returns the old value of @v. */ static __inline__ s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u) { s64 c, new, old; smp_mb(); __asm__ __volatile__( "1: ldq_l %[old],%[mem]\n" " cmpeq %[old],%[u],%[c]\n" " addq %[old],%[a],%[new]\n" " bne %[c],2f\n" " stq_c %[new],%[mem]\n" " beq %[new],3f\n" "2:\n" ".subsection 2\n" "3: br 1b\n" ".previous" : [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c) : [mem] "m"(*v), [a] "rI"(a), [u] "rI"(u) : "memory"); smp_mb(); return old; } #define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless /* * arch_atomic64_dec_if_positive - decrement by 1 if old value positive * @v: pointer of type atomic_t * * The function returns the old value of *v minus 1, even if * the atomic variable, v, was not decremented. */ static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) { s64 old, tmp; smp_mb(); __asm__ __volatile__( "1: ldq_l %[old],%[mem]\n" " subq %[old],1,%[tmp]\n" " ble %[old],2f\n" " stq_c %[tmp],%[mem]\n" " beq %[tmp],3f\n" "2:\n" ".subsection 2\n" "3: br 1b\n" ".previous" : [old] "=&r"(old), [tmp] "=&r"(tmp) : [mem] "m"(*v) : "memory"); smp_mb(); return old - 1; } #define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive #endif /* _ALPHA_ATOMIC_H */ PK ! tՋ> > a.out.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_A_OUT_H__ #define __ALPHA_A_OUT_H__ #include <uapi/asm/a.out.h> /* Assume that start addresses below 4G belong to a TASO application. Unfortunately, there is no proper bit in the exec header to check. Worse, we have to notice the start address before swapping to use /sbin/loader, which of course is _not_ a TASO application. */ #define SET_AOUT_PERSONALITY(BFPM, EX) \ set_personality (((BFPM->taso || EX.ah.entry < 0x100000000L \ ? ADDR_LIMIT_32BIT : 0) | PER_OSF4)) #endif /* __A_OUT_GNU_H__ */ PK ! �����! �! core_wildfire.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_WILDFIRE__H__ #define __ALPHA_WILDFIRE__H__ #include <linux/types.h> #include <asm/compiler.h> #define WILDFIRE_MAX_QBB 8 /* more than 8 requires other mods */ #define WILDFIRE_PCA_PER_QBB 4 #define WILDFIRE_IRQ_PER_PCA 64 #define WILDFIRE_NR_IRQS \ (WILDFIRE_MAX_QBB * WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA) extern unsigned char wildfire_hard_qbb_map[WILDFIRE_MAX_QBB]; extern unsigned char wildfire_soft_qbb_map[WILDFIRE_MAX_QBB]; #define QBB_MAP_EMPTY 0xff extern unsigned long wildfire_hard_qbb_mask; extern unsigned long wildfire_soft_qbb_mask; extern unsigned long wildfire_gp_mask; extern unsigned long wildfire_hs_mask; extern unsigned long wildfire_iop_mask; extern unsigned long wildfire_ior_mask; extern unsigned long wildfire_pca_mask; extern unsigned long wildfire_cpu_mask; extern unsigned long wildfire_mem_mask; #define WILDFIRE_QBB_EXISTS(qbbno) (wildfire_soft_qbb_mask & (1 << (qbbno))) #define WILDFIRE_MEM_EXISTS(qbbno) (wildfire_mem_mask & (0xf << ((qbbno) << 2))) #define WILDFIRE_PCA_EXISTS(qbbno, pcano) \ (wildfire_pca_mask & (1 << (((qbbno) << 2) + (pcano)))) typedef struct { volatile unsigned long csr __attribute__((aligned(64))); } wildfire_64; typedef struct { volatile unsigned long csr __attribute__((aligned(256))); } wildfire_256; typedef struct { volatile unsigned long csr __attribute__((aligned(2048))); } wildfire_2k; typedef struct { wildfire_64 qsd_whami; wildfire_64 qsd_rev; wildfire_64 qsd_port_present; wildfire_64 qsd_port_active; wildfire_64 qsd_fault_ena; wildfire_64 qsd_cpu_int_ena; wildfire_64 qsd_mem_config; wildfire_64 qsd_err_sum; wildfire_64 ce_sum[4]; wildfire_64 dev_init[4]; wildfire_64 it_int[4]; wildfire_64 ip_int[4]; wildfire_64 uce_sum[4]; wildfire_64 se_sum__non_dev_int[4]; wildfire_64 scratch[4]; wildfire_64 qsd_timer; wildfire_64 qsd_diag; } wildfire_qsd; typedef struct { wildfire_256 qsd_whami; wildfire_256 __pad1; wildfire_256 ce_sum; wildfire_256 dev_init; wildfire_256 it_int; wildfire_256 ip_int; wildfire_256 uce_sum; wildfire_256 se_sum; } wildfire_fast_qsd; typedef struct { wildfire_2k qsa_qbb_id; wildfire_2k __pad1; wildfire_2k qsa_port_ena; wildfire_2k qsa_scratch; wildfire_2k qsa_config[5]; wildfire_2k qsa_ref_int; wildfire_2k qsa_qbb_pop[2]; wildfire_2k qsa_dtag_fc; wildfire_2k __pad2[3]; wildfire_2k qsa_diag; wildfire_2k qsa_diag_lock[4]; wildfire_2k __pad3[11]; wildfire_2k qsa_cpu_err_sum; wildfire_2k qsa_misc_err_sum; wildfire_2k qsa_tmo_err_sum; wildfire_2k qsa_err_ena; wildfire_2k qsa_tmo_config; wildfire_2k qsa_ill_cmd_err_sum; wildfire_2k __pad4[26]; wildfire_2k qsa_busy_mask; wildfire_2k qsa_arr_valid; wildfire_2k __pad5[2]; wildfire_2k qsa_port_map[4]; wildfire_2k qsa_arr_addr[8]; wildfire_2k qsa_arr_mask[8]; } wildfire_qsa; typedef struct { wildfire_64 ioa_config; wildfire_64 iod_config; wildfire_64 iop_switch_credits; wildfire_64 __pad1; wildfire_64 iop_hose_credits; wildfire_64 __pad2[11]; struct { wildfire_64 __pad3; wildfire_64 init; } iop_hose[4]; wildfire_64 ioa_hose_0_ctrl; wildfire_64 iod_hose_0_ctrl; wildfire_64 ioa_hose_1_ctrl; wildfire_64 iod_hose_1_ctrl; wildfire_64 ioa_hose_2_ctrl; wildfire_64 iod_hose_2_ctrl; wildfire_64 ioa_hose_3_ctrl; wildfire_64 iod_hose_3_ctrl; struct { wildfire_64 target; wildfire_64 __pad4; } iop_dev_int[4]; wildfire_64 iop_err_int_target; wildfire_64 __pad5[7]; wildfire_64 iop_qbb_err_sum; wildfire_64 __pad6; wildfire_64 iop_qbb_se_sum; wildfire_64 __pad7; wildfire_64 ioa_err_sum; wildfire_64 iod_err_sum; wildfire_64 __pad8[4]; wildfire_64 ioa_diag_force_err; wildfire_64 iod_diag_force_err; wildfire_64 __pad9[4]; wildfire_64 iop_diag_send_err_int; wildfire_64 __pad10[15]; wildfire_64 ioa_scratch; wildfire_64 iod_scratch; } wildfire_iop; typedef struct { wildfire_2k gpa_qbb_map[4]; wildfire_2k gpa_mem_pop_map; wildfire_2k gpa_scratch; wildfire_2k gpa_diag; wildfire_2k gpa_config_0; wildfire_2k __pad1; wildfire_2k gpa_init_id; wildfire_2k gpa_config_2; /* not complete */ } wildfire_gp; typedef struct { wildfire_64 pca_what_am_i; wildfire_64 pca_err_sum; wildfire_64 pca_diag_force_err; wildfire_64 pca_diag_send_err_int; wildfire_64 pca_hose_credits; wildfire_64 pca_scratch; wildfire_64 pca_micro_addr; wildfire_64 pca_micro_data; wildfire_64 pca_pend_int; wildfire_64 pca_sent_int; wildfire_64 __pad1; wildfire_64 pca_stdio_edge_level; wildfire_64 __pad2[52]; struct { wildfire_64 target; wildfire_64 enable; } pca_int[4]; wildfire_64 __pad3[56]; wildfire_64 pca_alt_sent_int[32]; } wildfire_pca; typedef struct { wildfire_64 ne_what_am_i; /* not complete */ } wildfire_ne; typedef struct { wildfire_64 fe_what_am_i; /* not complete */ } wildfire_fe; typedef struct { wildfire_64 pci_io_addr_ext; wildfire_64 pci_ctrl; wildfire_64 pci_err_sum; wildfire_64 pci_err_addr; wildfire_64 pci_stall_cnt; wildfire_64 pci_iack_special; wildfire_64 __pad1[2]; wildfire_64 pci_pend_int; wildfire_64 pci_sent_int; wildfire_64 __pad2[54]; struct { wildfire_64 wbase; wildfire_64 wmask; wildfire_64 tbase; } pci_window[4]; wildfire_64 pci_flush_tlb; wildfire_64 pci_perf_mon; } wildfire_pci; #define WILDFIRE_ENTITY_SHIFT 18 #define WILDFIRE_GP_ENTITY (0x10UL << WILDFIRE_ENTITY_SHIFT) #define WILDFIRE_IOP_ENTITY (0x08UL << WILDFIRE_ENTITY_SHIFT) #define WILDFIRE_QSA_ENTITY (0x04UL << WILDFIRE_ENTITY_SHIFT) #define WILDFIRE_QSD_ENTITY_SLOW (0x05UL << WILDFIRE_ENTITY_SHIFT) #define WILDFIRE_QSD_ENTITY_FAST (0x01UL << WILDFIRE_ENTITY_SHIFT) #define WILDFIRE_PCA_ENTITY(pca) ((0xc|(pca))<<WILDFIRE_ENTITY_SHIFT) #define WILDFIRE_BASE (IDENT_ADDR | (1UL << 40)) #define WILDFIRE_QBB_MASK 0x0fUL /* for now, only 4 bits/16 QBBs */ #define WILDFIRE_QBB(q) ((~((long)(q)) & WILDFIRE_QBB_MASK) << 36) #define WILDFIRE_HOSE(h) ((long)(h) << 33) #define WILDFIRE_QBB_IO(q) (WILDFIRE_BASE | WILDFIRE_QBB(q)) #define WILDFIRE_QBB_HOSE(q,h) (WILDFIRE_QBB_IO(q) | WILDFIRE_HOSE(h)) #define WILDFIRE_MEM(q,h) (WILDFIRE_QBB_HOSE(q,h) | 0x000000000UL) #define WILDFIRE_CONF(q,h) (WILDFIRE_QBB_HOSE(q,h) | 0x1FE000000UL) #define WILDFIRE_IO(q,h) (WILDFIRE_QBB_HOSE(q,h) | 0x1FF000000UL) #define WILDFIRE_qsd(q) \ ((wildfire_qsd *)(WILDFIRE_QBB_IO(q)|WILDFIRE_QSD_ENTITY_SLOW|(((1UL<<13)-1)<<23))) #define WILDFIRE_fast_qsd() \ ((wildfire_fast_qsd *)(WILDFIRE_QBB_IO(0)|WILDFIRE_QSD_ENTITY_FAST|(((1UL<<13)-1)<<23))) #define WILDFIRE_qsa(q) \ ((wildfire_qsa *)(WILDFIRE_QBB_IO(q)|WILDFIRE_QSA_ENTITY|(((1UL<<13)-1)<<23))) #define WILDFIRE_iop(q) \ ((wildfire_iop *)(WILDFIRE_QBB_IO(q)|WILDFIRE_IOP_ENTITY|(((1UL<<13)-1)<<23))) #define WILDFIRE_gp(q) \ ((wildfire_gp *)(WILDFIRE_QBB_IO(q)|WILDFIRE_GP_ENTITY|(((1UL<<13)-1)<<23))) #define WILDFIRE_pca(q,pca) \ ((wildfire_pca *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(pca)|(((1UL<<13)-1)<<23))) #define WILDFIRE_ne(q,pca) \ ((wildfire_ne *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(pca)|(((1UL<<13)-1)<<23)|(1UL<<16))) #define WILDFIRE_fe(q,pca) \ ((wildfire_fe *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(pca)|(((1UL<<13)-1)<<23)|(3UL<<15))) #define WILDFIRE_pci(q,h) \ ((wildfire_pci *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(((h)&6)>>1)|((((h)&1)|2)<<16)|(((1UL<<13)-1)<<23))) #define WILDFIRE_IO_BIAS WILDFIRE_IO(0,0) #define WILDFIRE_MEM_BIAS WILDFIRE_MEM(0,0) /* ??? */ /* The IO address space is larger than 0xffff */ #define WILDFIRE_IO_SPACE (8UL*1024*1024) #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * Memory functions. all accesses are done through linear space. */ __EXTERN_INLINE void __iomem *wildfire_ioportmap(unsigned long addr) { return (void __iomem *)(addr + WILDFIRE_IO_BIAS); } __EXTERN_INLINE void __iomem *wildfire_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + WILDFIRE_MEM_BIAS); } __EXTERN_INLINE int wildfire_is_ioaddr(unsigned long addr) { return addr >= WILDFIRE_BASE; } __EXTERN_INLINE int wildfire_is_mmio(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr; return (addr & 0x100000000UL) == 0; } #undef __IO_PREFIX #define __IO_PREFIX wildfire #define wildfire_trivial_rw_bw 1 #define wildfire_trivial_rw_lq 1 #define wildfire_trivial_io_bw 1 #define wildfire_trivial_io_lq 1 #define wildfire_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_WILDFIRE__H__ */ PK ! j(��# # asm-offsets.hnu �[��� #include <generated/asm-offsets.h> PK ! �m�u? ? wrperfmon.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Definitions for use with the Alpha wrperfmon PAL call. */ #ifndef __ALPHA_WRPERFMON_H #define __ALPHA_WRPERFMON_H /* Following commands are implemented on all CPUs */ #define PERFMON_CMD_DISABLE 0 #define PERFMON_CMD_ENABLE 1 #define PERFMON_CMD_DESIRED_EVENTS 2 #define PERFMON_CMD_LOGGING_OPTIONS 3 /* Following commands on EV5/EV56/PCA56 only */ #define PERFMON_CMD_INT_FREQ 4 #define PERFMON_CMD_ENABLE_CLEAR 7 /* Following commands are on EV5 and better CPUs */ #define PERFMON_CMD_READ 5 #define PERFMON_CMD_WRITE 6 /* Following command are on EV6 and better CPUs */ #define PERFMON_CMD_ENABLE_WRITE 7 /* Following command are on EV67 and better CPUs */ #define PERFMON_CMD_I_STAT 8 #define PERFMON_CMD_PMPC 9 /* EV5/EV56/PCA56 Counters */ #define EV5_PCTR_0 (1UL<<0) #define EV5_PCTR_1 (1UL<<1) #define EV5_PCTR_2 (1UL<<2) #define EV5_PCTR_0_COUNT_SHIFT 48 #define EV5_PCTR_1_COUNT_SHIFT 32 #define EV5_PCTR_2_COUNT_SHIFT 16 #define EV5_PCTR_0_COUNT_MASK 0xffffUL #define EV5_PCTR_1_COUNT_MASK 0xffffUL #define EV5_PCTR_2_COUNT_MASK 0x3fffUL /* EV6 Counters */ #define EV6_PCTR_0 (1UL<<0) #define EV6_PCTR_1 (1UL<<1) #define EV6_PCTR_0_COUNT_SHIFT 28 #define EV6_PCTR_1_COUNT_SHIFT 6 #define EV6_PCTR_0_COUNT_MASK 0xfffffUL #define EV6_PCTR_1_COUNT_MASK 0xfffffUL /* EV67 (and subsequent) counters */ #define EV67_PCTR_0 (1UL<<0) #define EV67_PCTR_1 (1UL<<1) #define EV67_PCTR_0_COUNT_SHIFT 28 #define EV67_PCTR_1_COUNT_SHIFT 6 #define EV67_PCTR_0_COUNT_MASK 0xfffffUL #define EV67_PCTR_1_COUNT_MASK 0xfffffUL /* * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint * in Table E-23 regarding the bits that set the event PCTR 1 counts. * Hopefully what we have here is correct. */ #define EV6_PCTR_0_EVENT_MASK 0x10UL #define EV6_PCTR_1_EVENT_MASK 0x0fUL /* EV6 Events */ #define EV6_PCTR_0_CYCLES (0UL << 4) #define EV6_PCTR_0_INSTRUCTIONS (1UL << 4) #define EV6_PCTR_1_CYCLES 0 #define EV6_PCTR_1_BRANCHES 1 #define EV6_PCTR_1_BRANCH_MISPREDICTS 2 #define EV6_PCTR_1_DTB_SINGLE_MISSES 3 #define EV6_PCTR_1_DTB_DOUBLE_MISSES 4 #define EV6_PCTR_1_ITB_MISSES 5 #define EV6_PCTR_1_UNALIGNED_TRAPS 6 #define EV6_PCTR_1_REPLY_TRAPS 7 /* From the Alpha Architecture Reference Manual, 4th edn., 2002 */ #define EV67_PCTR_MODE_MASK 0x10UL #define EV67_PCTR_EVENT_MASK 0x0CUL #define EV67_PCTR_MODE_PROFILEME (1UL<<4) #define EV67_PCTR_MODE_AGGREGATE (0UL<<4) #define EV67_PCTR_INSTR_CYCLES (0UL<<2) #define EV67_PCTR_CYCLES_UNDEF (1UL<<2) #define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2) #define EV67_PCTR_CYCLES_MBOX (3UL<<2) #endif PK ! i��L �L core_t2.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_T2__H__ #define __ALPHA_T2__H__ /* Fit everything into one 128MB HAE window. */ #define T2_ONE_HAE_WINDOW 1 #include <linux/types.h> #include <linux/spinlock.h> #include <asm/compiler.h> /* * T2 is the internal name for the core logic chipset which provides * memory controller and PCI access for the SABLE-based systems. * * This file is based on: * * SABLE I/O Specification * Revision/Update Information: 1.3 * * jestabro@amt.tay1.dec.com Initial Version. * */ #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */ /* GAMMA-SABLE is a SABLE with EV5-based CPUs */ /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */ #define _GAMMA_BIAS 0x8000000000UL #if defined(CONFIG_ALPHA_GENERIC) #define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias #elif defined(CONFIG_ALPHA_GAMMA) #define GAMMA_BIAS _GAMMA_BIAS #else #define GAMMA_BIAS 0 #endif /* * Memory spaces: */ #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL) #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL) #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL) #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL) #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL) #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL) #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL) #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL) #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL) #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL) #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL) #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL) #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL) #define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL) #define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL) #define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL) #define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL) #define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL) #define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL) #define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL) #define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL) #define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL) #define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL) #define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL) /* The CSRs below are T3/T4 only */ #define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL) #define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL) #define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL) #define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL) #define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL) #define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL) #define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL) #define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL) #define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL) #define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL) #define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL) #define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL) #define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL) #define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL) #define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL) #define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL) #define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL) #define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL) #ifndef T2_ONE_HAE_WINDOW #define T2_HAE_ADDRESS T2_HAE_1 #endif /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to 3.8fff.ffff * * +--------------+ 3 8000 0000 * | CPU 0 CSRs | * +--------------+ 3 8100 0000 * | CPU 1 CSRs | * +--------------+ 3 8200 0000 * | CPU 2 CSRs | * +--------------+ 3 8300 0000 * | CPU 3 CSRs | * +--------------+ 3 8400 0000 * | CPU Reserved | * +--------------+ 3 8700 0000 * | Mem Reserved | * +--------------+ 3 8800 0000 * | Mem 0 CSRs | * +--------------+ 3 8900 0000 * | Mem 1 CSRs | * +--------------+ 3 8a00 0000 * | Mem 2 CSRs | * +--------------+ 3 8b00 0000 * | Mem 3 CSRs | * +--------------+ 3 8c00 0000 * | Mem Reserved | * +--------------+ 3 8e00 0000 * | PCI Bridge | * +--------------+ 3 8f00 0000 * | Expansion IO | * +--------------+ 3 9000 0000 * * */ #define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L) #define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L) #define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L) #define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L) #define T2_CPUn_BASE(n) (T2_CPU0_BASE + (((n)&3) * 0x001000000L)) #define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L) #define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L) #define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L) #define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L) /* * Sable CPU Module CSRS * * These are CSRs for hardware other than the CPU chip on the CPU module. * The CPU module has Backup Cache control logic, Cbus control logic, and * interrupt control logic on it. There is a duplicate tag store to speed * up maintaining cache coherency. */ struct sable_cpu_csr { unsigned long bcc; long fill_00[3]; /* Backup Cache Control */ unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */ unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */ unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */ unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */ unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */ unsigned long cbctl; long fill_06[3]; /* CBus Control */ unsigned long cbe; long fill_07[3]; /* CBus Error */ unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */ unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */ unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */ unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */ unsigned long sic; long fill_12[3]; /* System Interrupt Clear */ unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */ unsigned long madrl; long fill_14[3]; /* CBus Miss Address */ unsigned long rev; long fill_15[3]; /* CMIC Revision */ }; /* * Data structure for handling T2 machine checks: */ struct el_t2_frame_header { unsigned int elcf_fid; /* Frame ID (from above) */ unsigned int elcf_size; /* Size of frame in bytes */ }; struct el_t2_procdata_mcheck { unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */ /* EV4-specific fields */ unsigned long elfmc_exc_addr; /* Addr of excepting insn. */ unsigned long elfmc_exc_sum; /* Summary of arith traps. */ unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */ unsigned long elfmc_iccsr; /* IBox hardware enables. */ unsigned long elfmc_pal_base; /* Base address for PALcode. */ unsigned long elfmc_hier; /* Hardware Interrupt Enable. */ unsigned long elfmc_hirr; /* Hardware Interrupt Request. */ unsigned long elfmc_mm_csr; /* D-stream fault info. */ unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */ unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ unsigned long elfmc_abox_ctl; /* ABox Control Register. */ unsigned long elfmc_biu_stat; /* BIU Status. */ unsigned long elfmc_biu_addr; /* BUI Address. */ unsigned long elfmc_biu_ctl; /* BIU Control. */ unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */ unsigned long elfmc_fill_addr;/* Cache block which was being read. */ unsigned long elfmc_va; /* Effective VA of fault or miss. */ unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */ }; /* * Sable processor specific Machine Check Data segment. */ struct el_t2_logout_header { unsigned int elfl_size; /* size in bytes of logout area. */ unsigned int elfl_sbz1:31; /* Should be zero. */ unsigned int elfl_retry:1; /* Retry flag. */ unsigned int elfl_procoffset; /* Processor-specific offset. */ unsigned int elfl_sysoffset; /* Offset of system-specific. */ unsigned int elfl_error_type; /* PAL error type code. */ unsigned int elfl_frame_rev; /* PAL Frame revision. */ }; struct el_t2_sysdata_mcheck { unsigned long elcmc_bcc; /* CSR 0 */ unsigned long elcmc_bcce; /* CSR 1 */ unsigned long elcmc_bccea; /* CSR 2 */ unsigned long elcmc_bcue; /* CSR 3 */ unsigned long elcmc_bcuea; /* CSR 4 */ unsigned long elcmc_dter; /* CSR 5 */ unsigned long elcmc_cbctl; /* CSR 6 */ unsigned long elcmc_cbe; /* CSR 7 */ unsigned long elcmc_cbeal; /* CSR 8 */ unsigned long elcmc_cbeah; /* CSR 9 */ unsigned long elcmc_pmbx; /* CSR 10 */ unsigned long elcmc_ipir; /* CSR 11 */ unsigned long elcmc_sic; /* CSR 12 */ unsigned long elcmc_adlk; /* CSR 13 */ unsigned long elcmc_madrl; /* CSR 14 */ unsigned long elcmc_crrev4; /* CSR 15 */ }; /* * Sable memory error frame - sable pfms section 3.42 */ struct el_t2_data_memory { struct el_t2_frame_header elcm_hdr; /* ID$MEM-FERR = 0x08 */ unsigned int elcm_module; /* Module id. */ unsigned int elcm_res04; /* Reserved. */ unsigned long elcm_merr; /* CSR0: Error Reg 1. */ unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */ unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */ unsigned long elcm_mconf; /* CSR3: Configuration. */ unsigned long elcm_medc1; /* CSR4: EDC Status 1. */ unsigned long elcm_medc2; /* CSR5: EDC Status 2. */ unsigned long elcm_medcc; /* CSR6: EDC Control. */ unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */ unsigned long elcm_mref; /* CSR8: Refresh Control. */ unsigned long elcm_filter; /* CSR9: CRD Filter Control. */ }; /* * Sable other CPU error frame - sable pfms section 3.43 */ struct el_t2_data_other_cpu { short elco_cpuid; /* CPU ID */ short elco_res02[3]; unsigned long elco_bcc; /* CSR 0 */ unsigned long elco_bcce; /* CSR 1 */ unsigned long elco_bccea; /* CSR 2 */ unsigned long elco_bcue; /* CSR 3 */ unsigned long elco_bcuea; /* CSR 4 */ unsigned long elco_dter; /* CSR 5 */ unsigned long elco_cbctl; /* CSR 6 */ unsigned long elco_cbe; /* CSR 7 */ unsigned long elco_cbeal; /* CSR 8 */ unsigned long elco_cbeah; /* CSR 9 */ unsigned long elco_pmbx; /* CSR 10 */ unsigned long elco_ipir; /* CSR 11 */ unsigned long elco_sic; /* CSR 12 */ unsigned long elco_adlk; /* CSR 13 */ unsigned long elco_madrl; /* CSR 14 */ unsigned long elco_crrev4; /* CSR 15 */ }; /* * Sable other CPU error frame - sable pfms section 3.44 */ struct el_t2_data_t2{ struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */ unsigned long elct_iocsr; /* IO Control and Status Register */ unsigned long elct_cerr1; /* Cbus Error Register 1 */ unsigned long elct_cerr2; /* Cbus Error Register 2 */ unsigned long elct_cerr3; /* Cbus Error Register 3 */ unsigned long elct_perr1; /* PCI Error Register 1 */ unsigned long elct_perr2; /* PCI Error Register 2 */ unsigned long elct_hae0_1; /* High Address Extension Register 1 */ unsigned long elct_hae0_2; /* High Address Extension Register 2 */ unsigned long elct_hbase; /* High Base Register */ unsigned long elct_wbase1; /* Window Base Register 1 */ unsigned long elct_wmask1; /* Window Mask Register 1 */ unsigned long elct_tbase1; /* Translated Base Register 1 */ unsigned long elct_wbase2; /* Window Base Register 2 */ unsigned long elct_wmask2; /* Window Mask Register 2 */ unsigned long elct_tbase2; /* Translated Base Register 2 */ unsigned long elct_tdr0; /* TLB Data Register 0 */ unsigned long elct_tdr1; /* TLB Data Register 1 */ unsigned long elct_tdr2; /* TLB Data Register 2 */ unsigned long elct_tdr3; /* TLB Data Register 3 */ unsigned long elct_tdr4; /* TLB Data Register 4 */ unsigned long elct_tdr5; /* TLB Data Register 5 */ unsigned long elct_tdr6; /* TLB Data Register 6 */ unsigned long elct_tdr7; /* TLB Data Register 7 */ }; /* * Sable error log data structure - sable pfms section 3.40 */ struct el_t2_data_corrected { unsigned long elcpb_biu_stat; unsigned long elcpb_biu_addr; unsigned long elcpb_biu_ctl; unsigned long elcpb_fill_syndrome; unsigned long elcpb_fill_addr; unsigned long elcpb_bc_tag; }; /* * Sable error log data structure * Note there are 4 memory slots on sable (see t2.h) */ struct el_t2_frame_mcheck { struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */ struct el_t2_logout_header elfmc_hdr; struct el_t2_procdata_mcheck elfmc_procdata; struct el_t2_sysdata_mcheck elfmc_sysdata; struct el_t2_data_t2 elfmc_t2data; struct el_t2_data_memory elfmc_memdata[4]; struct el_t2_frame_header elfmc_footer; /* empty */ }; /* * Sable error log data structures on memory errors */ struct el_t2_frame_corrected { struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */ struct el_t2_logout_header elfcc_hdr; struct el_t2_data_corrected elfcc_procdata; /* struct el_t2_data_t2 elfcc_t2data; */ /* struct el_t2_data_memory elfcc_memdata[4]; */ struct el_t2_frame_header elfcc_footer; /* empty */ }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * T2 (the core logic PCI/memory support chipset for the SABLE * series of processors uses a sparse address mapping scheme to * get at PCI memory and I/O. */ #define vip volatile int * #define vuip volatile unsigned int * extern inline u8 t2_inb(unsigned long addr) { long result = *(vip) ((addr << 5) + T2_IO + 0x00); return __kernel_extbl(result, addr & 3); } extern inline void t2_outb(u8 b, unsigned long addr) { unsigned long w; w = __kernel_insbl(b, addr & 3); *(vuip) ((addr << 5) + T2_IO + 0x00) = w; mb(); } extern inline u16 t2_inw(unsigned long addr) { long result = *(vip) ((addr << 5) + T2_IO + 0x08); return __kernel_extwl(result, addr & 3); } extern inline void t2_outw(u16 b, unsigned long addr) { unsigned long w; w = __kernel_inswl(b, addr & 3); *(vuip) ((addr << 5) + T2_IO + 0x08) = w; mb(); } extern inline u32 t2_inl(unsigned long addr) { return *(vuip) ((addr << 5) + T2_IO + 0x18); } extern inline void t2_outl(u32 b, unsigned long addr) { *(vuip) ((addr << 5) + T2_IO + 0x18) = b; mb(); } /* * Memory functions. * * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 * which gives 1Gbyte of accessible space which relates exactly * to the amount of PCI memory mapping *into* system address space. * See p 6-17 of the specification but it looks something like this: * * 21164 Address: * * 3 2 1 * 9876543210987654321098765432109876543210 * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset * LL = Transfer length * * PCI Address: * * 3 2 1 * 10987654321098765432109876543210 * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR * */ #ifdef T2_ONE_HAE_WINDOW #define t2_set_hae #else #define t2_set_hae { \ unsigned long msb = addr >> 27; \ addr &= T2_MEM_R1_MASK; \ set_hae(msb); \ } #endif /* * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since * they may be called directly, rather than through the * ioreadNN/iowriteNN routines. */ __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long result; t2_set_hae; result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00); return __kernel_extbl(result, addr & 3); } __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long result; t2_set_hae; result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); return __kernel_extwl(result, addr & 3); } /* * On SABLE with T2, we must use SPARSE memory even for 32-bit access, * because we cannot access all of DENSE without changing its HAE. */ __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long result; t2_set_hae; result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); return result & 0xffffffffUL; } __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long r0, r1, work; t2_set_hae; work = (addr << 5) + T2_SPARSE_MEM + 0x18; r0 = *(vuip)(work); r1 = *(vuip)(work + (4 << 5)); return r1 << 32 | r0; } __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long w; t2_set_hae; w = __kernel_insbl(b, addr & 3); *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; } __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long w; t2_set_hae; w = __kernel_inswl(b, addr & 3); *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w; } /* * On SABLE with T2, we must use SPARSE memory even for 32-bit access, * because we cannot access all of DENSE without changing its HAE. */ __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; t2_set_hae; *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b; } __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long work; t2_set_hae; work = (addr << 5) + T2_SPARSE_MEM + 0x18; *(vuip)work = b; *(vuip)(work + (4 << 5)) = b >> 32; } __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr) { return (void __iomem *)(addr + T2_IO); } __EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + T2_DENSE_MEM); } __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr) { return (long)addr >= 0; } __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr) { return (unsigned long)addr >= T2_DENSE_MEM; } /* New-style ioread interface. The mmio routines are so ugly for T2 that it doesn't make sense to merge the pio and mmio routines. */ #define IOPORT(OS, NS) \ __EXTERN_INLINE unsigned int t2_ioread##NS(const void __iomem *xaddr) \ { \ if (t2_is_mmio(xaddr)) \ return t2_read##OS(xaddr); \ else \ return t2_in##OS((unsigned long)xaddr - T2_IO); \ } \ __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \ { \ if (t2_is_mmio(xaddr)) \ t2_write##OS(b, xaddr); \ else \ t2_out##OS(b, (unsigned long)xaddr - T2_IO); \ } IOPORT(b, 8) IOPORT(w, 16) IOPORT(l, 32) #undef IOPORT #undef vip #undef vuip #undef __IO_PREFIX #define __IO_PREFIX t2 #define t2_trivial_rw_bw 0 #define t2_trivial_rw_lq 0 #define t2_trivial_io_bw 0 #define t2_trivial_io_lq 0 #define t2_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_T2__H__ */ PK ! �T�&� � irqflags.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_IRQFLAGS_H #define __ALPHA_IRQFLAGS_H #include <asm/pal.h> #define IPL_MIN 0 #define IPL_SW0 1 #define IPL_SW1 2 #define IPL_DEV0 3 #define IPL_DEV1 4 #define IPL_TIMER 5 #define IPL_PERF 6 #define IPL_POWERFAIL 6 #define IPL_MCHECK 7 #define IPL_MAX 7 #ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK #undef IPL_MIN #define IPL_MIN __min_ipl extern int __min_ipl; #endif #define getipl() (rdps() & 7) #define setipl(ipl) ((void) swpipl(ipl)) static inline unsigned long arch_local_save_flags(void) { return rdps(); } static inline void arch_local_irq_disable(void) { setipl(IPL_MAX); barrier(); } static inline unsigned long arch_local_irq_save(void) { unsigned long flags = swpipl(IPL_MAX); barrier(); return flags; } static inline void arch_local_irq_enable(void) { barrier(); setipl(IPL_MIN); } static inline void arch_local_irq_restore(unsigned long flags) { barrier(); setipl(flags); barrier(); } static inline bool arch_irqs_disabled_flags(unsigned long flags) { return flags == IPL_MAX; } static inline bool arch_irqs_disabled(void) { return arch_irqs_disabled_flags(getipl()); } #endif /* __ALPHA_IRQFLAGS_H */ PK ! %��u{ { syscall.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ALPHA_SYSCALL_H #define _ASM_ALPHA_SYSCALL_H #include <uapi/linux/audit.h> static inline int syscall_get_arch(struct task_struct *task) { return AUDIT_ARCH_ALPHA; } static inline long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) { return regs->r0; } #endif /* _ASM_ALPHA_SYSCALL_H */ PK ! �2�M� � agp_backend.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_AGP_BACKEND_H #define _ALPHA_AGP_BACKEND_H 1 typedef union _alpha_agp_mode { struct { u32 rate : 3; u32 reserved0 : 1; u32 fw : 1; u32 fourgb : 1; u32 reserved1 : 2; u32 enable : 1; u32 sba : 1; u32 reserved2 : 14; u32 rq : 8; } bits; u32 lw; } alpha_agp_mode; typedef struct _alpha_agp_info { struct pci_controller *hose; struct { dma_addr_t bus_base; unsigned long size; void *sysdata; } aperture; alpha_agp_mode capability; alpha_agp_mode mode; void *private; struct alpha_agp_ops *ops; } alpha_agp_info; struct alpha_agp_ops { int (*setup)(alpha_agp_info *); void (*cleanup)(alpha_agp_info *); int (*configure)(alpha_agp_info *); int (*bind)(alpha_agp_info *, off_t, struct agp_memory *); int (*unbind)(alpha_agp_info *, off_t, struct agp_memory *); unsigned long (*translate)(alpha_agp_info *, dma_addr_t); }; #endif /* _ALPHA_AGP_BACKEND_H */ PK ! � p�; ; bug.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_BUG_H #define _ALPHA_BUG_H #include <linux/linkage.h> #ifdef CONFIG_BUG #include <asm/pal.h> /* ??? Would be nice to use .gprel32 here, but we can't be sure that the function loaded the GP, so this could fail in modules. */ #define BUG() do { \ __asm__ __volatile__( \ "call_pal %0 # bugchk\n\t" \ ".long %1\n\t.8byte %2" \ : : "i"(PAL_bugchk), "i"(__LINE__), "i"(__FILE__)); \ unreachable(); \ } while (0) #define HAVE_ARCH_BUG #endif #include <asm-generic/bug.h> #endif PK ! 4�� delay.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_DELAY_H #define __ALPHA_DELAY_H extern void __delay(int loops); extern void udelay(unsigned long usecs); extern void ndelay(unsigned long nsecs); #define ndelay ndelay #endif /* defined(__ALPHA_DELAY_H) */ PK ! OS=�. . hw_irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_HW_IRQ_H #define _ALPHA_HW_IRQ_H extern volatile unsigned long irq_err_count; DECLARE_PER_CPU(unsigned long, irq_pmi_count); #ifdef CONFIG_ALPHA_GENERIC #define ACTUAL_NR_IRQS alpha_mv.nr_irqs #else #define ACTUAL_NR_IRQS NR_IRQS #endif #endif PK ! ݇<� ftrace.hnu �[��� /* empty */ PK ! $�Kpc c floppy.hnu �[��� /* * Architecture specific parts of the Floppy driver * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1995 */ #ifndef __ASM_ALPHA_FLOPPY_H #define __ASM_ALPHA_FLOPPY_H #define fd_inb(base, reg) inb_p((base) + (reg)) #define fd_outb(value, base, reg) outb_p(value, (base) + (reg)) #define fd_enable_dma() enable_dma(FLOPPY_DMA) #define fd_disable_dma() disable_dma(FLOPPY_DMA) #define fd_request_dma() request_dma(FLOPPY_DMA,"floppy") #define fd_free_dma() free_dma(FLOPPY_DMA) #define fd_clear_dma_ff() clear_dma_ff(FLOPPY_DMA) #define fd_set_dma_mode(mode) set_dma_mode(FLOPPY_DMA,mode) #define fd_set_dma_addr(addr) set_dma_addr(FLOPPY_DMA,virt_to_bus(addr)) #define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA,count) #define fd_enable_irq() enable_irq(FLOPPY_IRQ) #define fd_disable_irq() disable_irq(FLOPPY_IRQ) #define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt,\ 0, "floppy", NULL) #define fd_free_irq() free_irq(FLOPPY_IRQ, NULL) #ifdef CONFIG_PCI #include <linux/pci.h> #define fd_dma_setup(addr,size,mode,io) alpha_fd_dma_setup(addr,size,mode,io) static __inline__ int alpha_fd_dma_setup(char *addr, unsigned long size, int mode, int io) { static unsigned long prev_size; static dma_addr_t bus_addr = 0; static char *prev_addr; static int prev_dir; int dir; dir = (mode != DMA_MODE_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE; if (bus_addr && (addr != prev_addr || size != prev_size || dir != prev_dir)) { /* different from last time -- unmap prev */ pci_unmap_single(isa_bridge, bus_addr, prev_size, prev_dir); bus_addr = 0; } if (!bus_addr) /* need to map it */ bus_addr = pci_map_single(isa_bridge, addr, size, dir); /* remember this one as prev */ prev_addr = addr; prev_size = size; prev_dir = dir; fd_clear_dma_ff(); fd_set_dma_mode(mode); set_dma_addr(FLOPPY_DMA, bus_addr); fd_set_dma_count(size); virtual_dma_port = io; fd_enable_dma(); return 0; } #endif /* CONFIG_PCI */ __inline__ void virtual_dma_init(void) { /* Nothing to do on an Alpha */ } static int FDC1 = 0x3f0; static int FDC2 = -1; /* * Again, the CMOS information doesn't work on the alpha.. */ #define FLOPPY0_TYPE 6 #define FLOPPY1_TYPE 0 #define N_FDC 2 #define N_DRIVE 8 /* * Most Alphas have no problems with floppy DMA crossing 64k borders, * except for certain ones, like XL and RUFFIAN. * * However, the test is simple and fast, and this *is* floppy, after all, * so we do it for all platforms, just to make sure. * * This is advantageous in other circumstances as well, as in moving * about the PCI DMA windows and forcing the floppy to start doing * scatter-gather when it never had before, and there *is* a problem * on that platform... ;-} */ static inline unsigned long CROSS_64KB(void *a, unsigned long s) { unsigned long p = (unsigned long)a; return ((p + s - 1) ^ p) & ~0xffffUL; } #define EXTRA_FLOPPY_PARAMS #endif /* __ASM_ALPHA_FLOPPY_H */ PK ! � t� � hardirq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_HARDIRQ_H #define _ALPHA_HARDIRQ_H void ack_bad_irq(unsigned int irq); #define ack_bad_irq ack_bad_irq #include <asm-generic/hardirq.h> #endif /* _ALPHA_HARDIRQ_H */ PK ! �a�'& '& uaccess.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_UACCESS_H #define __ALPHA_UACCESS_H /* * The fs value determines whether argument validity checking should be * performed or not. If get_fs() == USER_DS, checking is performed, with * get_fs() == KERNEL_DS, checking is bypassed. * * Or at least it did once upon a time. Nowadays it is a mask that * defines which bits of the address space are off limits. This is a * wee bit faster than the above. * * For historical reasons, these macros are grossly misnamed. */ #define KERNEL_DS ((mm_segment_t) { 0UL }) #define USER_DS ((mm_segment_t) { -0x40000000000UL }) #define get_fs() (current_thread_info()->addr_limit) #define set_fs(x) (current_thread_info()->addr_limit = (x)) #define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) /* * Is a address valid? This does a straightforward calculation rather * than tests. * * Address valid if: * - "addr" doesn't have any high-bits set * - AND "size" doesn't have any high-bits set * - AND "addr+size-(size != 0)" doesn't have any high-bits set * - OR we are in kernel mode. */ #define __access_ok(addr, size) ({ \ unsigned long __ao_a = (addr), __ao_b = (size); \ unsigned long __ao_end = __ao_a + __ao_b - !!__ao_b; \ (get_fs().seg & (__ao_a | __ao_b | __ao_end)) == 0; }) #define access_ok(addr, size) \ ({ \ __chk_user_ptr(addr); \ __access_ok(((unsigned long)(addr)), (size)); \ }) /* * These are the main single-value transfer routines. They automatically * use the right size if we just have the right pointer type. * * As the alpha uses the same address space for kernel and user * data, we can just do these as direct assignments. (Of course, the * exception handling means that it's no longer "just"...) * * Careful to not * (a) re-use the arguments for side effects (sizeof/typeof is ok) * (b) require any knowledge of processes at this stage */ #define put_user(x, ptr) \ __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr))) #define get_user(x, ptr) \ __get_user_check((x), (ptr), sizeof(*(ptr))) /* * The "__xxx" versions do not do address space checking, useful when * doing multiple accesses to the same area (the programmer has to do the * checks by hand with "access_ok()") */ #define __put_user(x, ptr) \ __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr))) #define __get_user(x, ptr) \ __get_user_nocheck((x), (ptr), sizeof(*(ptr))) /* * The "lda %1, 2b-1b(%0)" bits are magic to get the assembler to * encode the bits we need for resolving the exception. See the * more extensive comments with fixup_inline_exception below for * more information. */ #define EXC(label,cont,res,err) \ ".section __ex_table,\"a\"\n" \ " .long "#label"-.\n" \ " lda "#res","#cont"-"#label"("#err")\n" \ ".previous\n" extern void __get_user_unknown(void); #define __get_user_nocheck(x, ptr, size) \ ({ \ long __gu_err = 0; \ unsigned long __gu_val; \ __chk_user_ptr(ptr); \ switch (size) { \ case 1: __get_user_8(ptr); break; \ case 2: __get_user_16(ptr); break; \ case 4: __get_user_32(ptr); break; \ case 8: __get_user_64(ptr); break; \ default: __get_user_unknown(); break; \ } \ (x) = (__force __typeof__(*(ptr))) __gu_val; \ __gu_err; \ }) #define __get_user_check(x, ptr, size) \ ({ \ long __gu_err = -EFAULT; \ unsigned long __gu_val = 0; \ const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \ if (__access_ok((unsigned long)__gu_addr, size)) { \ __gu_err = 0; \ switch (size) { \ case 1: __get_user_8(__gu_addr); break; \ case 2: __get_user_16(__gu_addr); break; \ case 4: __get_user_32(__gu_addr); break; \ case 8: __get_user_64(__gu_addr); break; \ default: __get_user_unknown(); break; \ } \ } \ (x) = (__force __typeof__(*(ptr))) __gu_val; \ __gu_err; \ }) struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct __user *)(x)) #define __get_user_64(addr) \ __asm__("1: ldq %0,%2\n" \ "2:\n" \ EXC(1b,2b,%0,%1) \ : "=r"(__gu_val), "=r"(__gu_err) \ : "m"(__m(addr)), "1"(__gu_err)) #define __get_user_32(addr) \ __asm__("1: ldl %0,%2\n" \ "2:\n" \ EXC(1b,2b,%0,%1) \ : "=r"(__gu_val), "=r"(__gu_err) \ : "m"(__m(addr)), "1"(__gu_err)) #ifdef __alpha_bwx__ /* Those lucky bastards with ev56 and later CPUs can do byte/word moves. */ #define __get_user_16(addr) \ __asm__("1: ldwu %0,%2\n" \ "2:\n" \ EXC(1b,2b,%0,%1) \ : "=r"(__gu_val), "=r"(__gu_err) \ : "m"(__m(addr)), "1"(__gu_err)) #define __get_user_8(addr) \ __asm__("1: ldbu %0,%2\n" \ "2:\n" \ EXC(1b,2b,%0,%1) \ : "=r"(__gu_val), "=r"(__gu_err) \ : "m"(__m(addr)), "1"(__gu_err)) #else /* Unfortunately, we can't get an unaligned access trap for the sub-word load, so we have to do a general unaligned operation. */ #define __get_user_16(addr) \ { \ long __gu_tmp; \ __asm__("1: ldq_u %0,0(%3)\n" \ "2: ldq_u %1,1(%3)\n" \ " extwl %0,%3,%0\n" \ " extwh %1,%3,%1\n" \ " or %0,%1,%0\n" \ "3:\n" \ EXC(1b,3b,%0,%2) \ EXC(2b,3b,%0,%2) \ : "=&r"(__gu_val), "=&r"(__gu_tmp), "=r"(__gu_err) \ : "r"(addr), "2"(__gu_err)); \ } #define __get_user_8(addr) \ __asm__("1: ldq_u %0,0(%2)\n" \ " extbl %0,%2,%0\n" \ "2:\n" \ EXC(1b,2b,%0,%1) \ : "=&r"(__gu_val), "=r"(__gu_err) \ : "r"(addr), "1"(__gu_err)) #endif extern void __put_user_unknown(void); #define __put_user_nocheck(x, ptr, size) \ ({ \ long __pu_err = 0; \ __chk_user_ptr(ptr); \ switch (size) { \ case 1: __put_user_8(x, ptr); break; \ case 2: __put_user_16(x, ptr); break; \ case 4: __put_user_32(x, ptr); break; \ case 8: __put_user_64(x, ptr); break; \ default: __put_user_unknown(); break; \ } \ __pu_err; \ }) #define __put_user_check(x, ptr, size) \ ({ \ long __pu_err = -EFAULT; \ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ if (__access_ok((unsigned long)__pu_addr, size)) { \ __pu_err = 0; \ switch (size) { \ case 1: __put_user_8(x, __pu_addr); break; \ case 2: __put_user_16(x, __pu_addr); break; \ case 4: __put_user_32(x, __pu_addr); break; \ case 8: __put_user_64(x, __pu_addr); break; \ default: __put_user_unknown(); break; \ } \ } \ __pu_err; \ }) /* * The "__put_user_xx()" macros tell gcc they read from memory * instead of writing: this is because they do not write to * any memory gcc knows about, so there are no aliasing issues */ #define __put_user_64(x, addr) \ __asm__ __volatile__("1: stq %r2,%1\n" \ "2:\n" \ EXC(1b,2b,$31,%0) \ : "=r"(__pu_err) \ : "m" (__m(addr)), "rJ" (x), "0"(__pu_err)) #define __put_user_32(x, addr) \ __asm__ __volatile__("1: stl %r2,%1\n" \ "2:\n" \ EXC(1b,2b,$31,%0) \ : "=r"(__pu_err) \ : "m"(__m(addr)), "rJ"(x), "0"(__pu_err)) #ifdef __alpha_bwx__ /* Those lucky bastards with ev56 and later CPUs can do byte/word moves. */ #define __put_user_16(x, addr) \ __asm__ __volatile__("1: stw %r2,%1\n" \ "2:\n" \ EXC(1b,2b,$31,%0) \ : "=r"(__pu_err) \ : "m"(__m(addr)), "rJ"(x), "0"(__pu_err)) #define __put_user_8(x, addr) \ __asm__ __volatile__("1: stb %r2,%1\n" \ "2:\n" \ EXC(1b,2b,$31,%0) \ : "=r"(__pu_err) \ : "m"(__m(addr)), "rJ"(x), "0"(__pu_err)) #else /* Unfortunately, we can't get an unaligned access trap for the sub-word write, so we have to do a general unaligned operation. */ #define __put_user_16(x, addr) \ { \ long __pu_tmp1, __pu_tmp2, __pu_tmp3, __pu_tmp4; \ __asm__ __volatile__( \ "1: ldq_u %2,1(%5)\n" \ "2: ldq_u %1,0(%5)\n" \ " inswh %6,%5,%4\n" \ " inswl %6,%5,%3\n" \ " mskwh %2,%5,%2\n" \ " mskwl %1,%5,%1\n" \ " or %2,%4,%2\n" \ " or %1,%3,%1\n" \ "3: stq_u %2,1(%5)\n" \ "4: stq_u %1,0(%5)\n" \ "5:\n" \ EXC(1b,5b,$31,%0) \ EXC(2b,5b,$31,%0) \ EXC(3b,5b,$31,%0) \ EXC(4b,5b,$31,%0) \ : "=r"(__pu_err), "=&r"(__pu_tmp1), \ "=&r"(__pu_tmp2), "=&r"(__pu_tmp3), \ "=&r"(__pu_tmp4) \ : "r"(addr), "r"((unsigned long)(x)), "0"(__pu_err)); \ } #define __put_user_8(x, addr) \ { \ long __pu_tmp1, __pu_tmp2; \ __asm__ __volatile__( \ "1: ldq_u %1,0(%4)\n" \ " insbl %3,%4,%2\n" \ " mskbl %1,%4,%1\n" \ " or %1,%2,%1\n" \ "2: stq_u %1,0(%4)\n" \ "3:\n" \ EXC(1b,3b,$31,%0) \ EXC(2b,3b,$31,%0) \ : "=r"(__pu_err), \ "=&r"(__pu_tmp1), "=&r"(__pu_tmp2) \ : "r"((unsigned long)(x)), "r"(addr), "0"(__pu_err)); \ } #endif /* * Complex access routines */ extern long __copy_user(void *to, const void *from, long len); static inline unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long len) { return __copy_user(to, (__force const void *)from, len); } static inline unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long len) { return __copy_user((__force void *)to, from, len); } extern long __clear_user(void __user *to, long len); extern inline long clear_user(void __user *to, long len) { if (__access_ok((unsigned long)to, len)) len = __clear_user(to, len); return len; } #define user_addr_max() \ (uaccess_kernel() ? ~0UL : TASK_SIZE) extern long strncpy_from_user(char *dest, const char __user *src, long count); extern __must_check long strnlen_user(const char __user *str, long n); #include <asm/extable.h> #endif /* __ALPHA_UACCESS_H */ PK ! `Λ! �! jensen.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_JENSEN_H #define __ALPHA_JENSEN_H #include <asm/compiler.h> /* * Defines for the AlphaPC EISA IO and memory address space. */ /* * NOTE! The memory operations do not set any memory barriers, as it's * not needed for cases like a frame buffer that is essentially memory-like. * You need to do them by hand if the operations depend on ordering. * * Similarly, the port IO operations do a "mb" only after a write operation: * if an mb is needed before (as in the case of doing memory mapped IO * first, and then a port IO operation to the same device), it needs to be * done by hand. * * After the above has bitten me 100 times, I'll give up and just do the * mb all the time, but right now I'm hoping this will work out. Avoiding * mb's may potentially be a noticeable speed improvement, but I can't * honestly say I've tested it. * * Handling interrupts that need to do mb's to synchronize to non-interrupts * is another fun race area. Don't do it (because if you do, I'll have to * do *everything* with interrupts disabled, ugh). */ /* * EISA Interrupt Acknowledge address */ #define EISA_INTA (IDENT_ADDR + 0x100000000UL) /* * FEPROM addresses */ #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL) #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL) /* * VL82C106 base address */ #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL) /* * EISA "Host Address Extension" address (bits 25-31 of the EISA address) */ #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL) /* * "SYSCTL" register address */ #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL) /* * "spare" register address */ #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL) /* * EISA memory address offset */ #define EISA_MEM (IDENT_ADDR + 0x200000000UL) /* * EISA IO address offset */ #define EISA_IO (IDENT_ADDR + 0x300000000UL) #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * Handle the "host address register". This needs to be set * to the high 7 bits of the EISA address. This is also needed * for EISA IO addresses, which are only 16 bits wide (the * hae needs to be set to 0). * * HAE isn't needed for the local IO operations, though. */ #define JENSEN_HAE_ADDRESS EISA_HAE #define JENSEN_HAE_MASK 0x1ffffff __EXTERN_INLINE void jensen_set_hae(unsigned long addr) { /* hae on the Jensen is bits 31:25 shifted right */ addr >>= 25; if (addr != alpha_mv.hae_cache) set_hae(addr); } #define vuip volatile unsigned int * /* * IO functions * * The "local" functions are those that don't go out to the EISA bus, * but instead act on the VL82C106 chip directly.. This is mainly the * keyboard, RTC, printer and first two serial lines.. * * The local stuff makes for some complications, but it seems to be * gone in the PCI version. I hope I can get DEC suckered^H^H^H^H^H^H^H^H * convinced that I need one of the newer machines. */ __EXTERN_INLINE unsigned int jensen_local_inb(unsigned long addr) { return 0xff & *(vuip)((addr << 9) + EISA_VL82C106); } __EXTERN_INLINE void jensen_local_outb(u8 b, unsigned long addr) { *(vuip)((addr << 9) + EISA_VL82C106) = b; mb(); } __EXTERN_INLINE unsigned int jensen_bus_inb(unsigned long addr) { long result; jensen_set_hae(0); result = *(volatile int *)((addr << 7) + EISA_IO + 0x00); return __kernel_extbl(result, addr & 3); } __EXTERN_INLINE void jensen_bus_outb(u8 b, unsigned long addr) { jensen_set_hae(0); *(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101; mb(); } /* * It seems gcc is not very good at optimizing away logical * operations that result in operations across inline functions. * Which is why this is a macro. */ #define jensen_is_local(addr) ( \ /* keyboard */ (addr == 0x60 || addr == 0x64) || \ /* RTC */ (addr == 0x170 || addr == 0x171) || \ /* mb COM2 */ (addr >= 0x2f8 && addr <= 0x2ff) || \ /* mb LPT1 */ (addr >= 0x3bc && addr <= 0x3be) || \ /* mb COM2 */ (addr >= 0x3f8 && addr <= 0x3ff)) __EXTERN_INLINE u8 jensen_inb(unsigned long addr) { if (jensen_is_local(addr)) return jensen_local_inb(addr); else return jensen_bus_inb(addr); } __EXTERN_INLINE void jensen_outb(u8 b, unsigned long addr) { if (jensen_is_local(addr)) jensen_local_outb(b, addr); else jensen_bus_outb(b, addr); } __EXTERN_INLINE u16 jensen_inw(unsigned long addr) { long result; jensen_set_hae(0); result = *(volatile int *) ((addr << 7) + EISA_IO + 0x20); result >>= (addr & 3) * 8; return 0xffffUL & result; } __EXTERN_INLINE u32 jensen_inl(unsigned long addr) { jensen_set_hae(0); return *(vuip) ((addr << 7) + EISA_IO + 0x60); } __EXTERN_INLINE void jensen_outw(u16 b, unsigned long addr) { jensen_set_hae(0); *(vuip) ((addr << 7) + EISA_IO + 0x20) = b * 0x00010001; mb(); } __EXTERN_INLINE void jensen_outl(u32 b, unsigned long addr) { jensen_set_hae(0); *(vuip) ((addr << 7) + EISA_IO + 0x60) = b; mb(); } /* * Memory functions. */ __EXTERN_INLINE u8 jensen_readb(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; long result; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; result = *(volatile int *) ((addr << 7) + EISA_MEM + 0x00); result >>= (addr & 3) * 8; return 0xffUL & result; } __EXTERN_INLINE u16 jensen_readw(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; long result; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; result = *(volatile int *) ((addr << 7) + EISA_MEM + 0x20); result >>= (addr & 3) * 8; return 0xffffUL & result; } __EXTERN_INLINE u32 jensen_readl(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; return *(vuip) ((addr << 7) + EISA_MEM + 0x60); } __EXTERN_INLINE u64 jensen_readq(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long r0, r1; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; addr = (addr << 7) + EISA_MEM + 0x60; r0 = *(vuip) (addr); r1 = *(vuip) (addr + (4 << 7)); return r1 << 32 | r0; } __EXTERN_INLINE void jensen_writeb(u8 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; *(vuip) ((addr << 7) + EISA_MEM + 0x00) = b * 0x01010101; } __EXTERN_INLINE void jensen_writew(u16 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; *(vuip) ((addr << 7) + EISA_MEM + 0x20) = b * 0x00010001; } __EXTERN_INLINE void jensen_writel(u32 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; *(vuip) ((addr << 7) + EISA_MEM + 0x60) = b; } __EXTERN_INLINE void jensen_writeq(u64 b, volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; jensen_set_hae(addr); addr &= JENSEN_HAE_MASK; addr = (addr << 7) + EISA_MEM + 0x60; *(vuip) (addr) = b; *(vuip) (addr + (4 << 7)) = b >> 32; } __EXTERN_INLINE void __iomem *jensen_ioportmap(unsigned long addr) { return (void __iomem *)addr; } __EXTERN_INLINE void __iomem *jensen_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + 0x100000000ul); } __EXTERN_INLINE int jensen_is_ioaddr(unsigned long addr) { return (long)addr >= 0; } __EXTERN_INLINE int jensen_is_mmio(const volatile void __iomem *addr) { return (unsigned long)addr >= 0x100000000ul; } /* New-style ioread interface. All the routines are so ugly for Jensen that it doesn't make sense to merge them. */ #define IOPORT(OS, NS) \ __EXTERN_INLINE unsigned int jensen_ioread##NS(const void __iomem *xaddr) \ { \ if (jensen_is_mmio(xaddr)) \ return jensen_read##OS(xaddr - 0x100000000ul); \ else \ return jensen_in##OS((unsigned long)xaddr); \ } \ __EXTERN_INLINE void jensen_iowrite##NS(u##NS b, void __iomem *xaddr) \ { \ if (jensen_is_mmio(xaddr)) \ jensen_write##OS(b, xaddr - 0x100000000ul); \ else \ jensen_out##OS(b, (unsigned long)xaddr); \ } IOPORT(b, 8) IOPORT(w, 16) IOPORT(l, 32) #undef IOPORT #undef vuip #undef __IO_PREFIX #define __IO_PREFIX jensen #define jensen_trivial_rw_bw 0 #define jensen_trivial_rw_lq 0 #define jensen_trivial_io_bw 0 #define jensen_trivial_io_lq 0 #define jensen_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_JENSEN_H */ PK ! � js< < console.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __AXP_CONSOLE_H #define __AXP_CONSOLE_H #include <uapi/asm/console.h> #ifndef __ASSEMBLY__ extern long callback_puts(long unit, const char *s, long length); extern long callback_getc(long unit); extern long callback_open_console(void); extern long callback_close_console(void); extern long callback_open(const char *device, long length); extern long callback_close(long unit); extern long callback_read(long channel, long count, const char *buf, long lbn); extern long callback_getenv(long id, const char *buf, unsigned long buf_size); extern long callback_setenv(long id, const char *buf, unsigned long buf_size); extern long callback_save_env(void); extern int srm_fixup(unsigned long new_callback_addr, unsigned long new_hwrpb_addr); extern long srm_puts(const char *, long); extern long srm_printk(const char *, ...) __attribute__ ((format (printf, 1, 2))); struct crb_struct; struct hwrpb_struct; extern int callback_init_done; extern void * callback_init(void *); #endif /* __ASSEMBLY__ */ #endif /* __AXP_CONSOLE_H */ PK ! �LN%! %! core_tsunami.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_TSUNAMI__H__ #define __ALPHA_TSUNAMI__H__ #include <linux/types.h> #include <asm/compiler.h> /* * TSUNAMI/TYPHOON are the internal names for the core logic chipset which * provides memory controller and PCI access for the 21264 based systems. * * This file is based on: * * Tsunami System Programmers Manual * Preliminary, Chapters 2-5 * */ /* XXX: Do we need to conditionalize on this? */ #ifdef USE_48_BIT_KSEG #define TS_BIAS 0x80000000000UL #else #define TS_BIAS 0x10000000000UL #endif /* * CChip, DChip, and PChip registers */ typedef struct { volatile unsigned long csr __attribute__((aligned(64))); } tsunami_64; typedef struct { tsunami_64 csc; tsunami_64 mtr; tsunami_64 misc; tsunami_64 mpd; tsunami_64 aar0; tsunami_64 aar1; tsunami_64 aar2; tsunami_64 aar3; tsunami_64 dim0; tsunami_64 dim1; tsunami_64 dir0; tsunami_64 dir1; tsunami_64 drir; tsunami_64 prben; tsunami_64 iic; /* a.k.a. iic0 */ tsunami_64 wdr; /* a.k.a. iic1 */ tsunami_64 mpr0; tsunami_64 mpr1; tsunami_64 mpr2; tsunami_64 mpr3; tsunami_64 mctl; tsunami_64 __pad1; tsunami_64 ttr; tsunami_64 tdr; tsunami_64 dim2; tsunami_64 dim3; tsunami_64 dir2; tsunami_64 dir3; tsunami_64 iic2; tsunami_64 iic3; } tsunami_cchip; typedef struct { tsunami_64 dsc; tsunami_64 str; tsunami_64 drev; } tsunami_dchip; typedef struct { tsunami_64 wsba[4]; tsunami_64 wsm[4]; tsunami_64 tba[4]; tsunami_64 pctl; tsunami_64 plat; tsunami_64 reserved; tsunami_64 perror; tsunami_64 perrmask; tsunami_64 perrset; tsunami_64 tlbiv; tsunami_64 tlbia; tsunami_64 pmonctl; tsunami_64 pmoncnt; } tsunami_pchip; #define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL)) #define TSUNAMI_dchip ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL)) #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL)) #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL)) extern int TSUNAMI_bootcpu; /* * TSUNAMI Pchip Error register. */ #define perror_m_lost 0x1 #define perror_m_serr 0x2 #define perror_m_perr 0x4 #define perror_m_dcrto 0x8 #define perror_m_sge 0x10 #define perror_m_ape 0x20 #define perror_m_ta 0x40 #define perror_m_rdpe 0x80 #define perror_m_nds 0x100 #define perror_m_rto 0x200 #define perror_m_uecc 0x400 #define perror_m_cre 0x800 #define perror_m_addrl 0xFFFFFFFF0000UL #define perror_m_addrh 0x7000000000000UL #define perror_m_cmd 0xF0000000000000UL #define perror_m_syn 0xFF00000000000000UL union TPchipPERROR { struct { unsigned int perror_v_lost : 1; unsigned perror_v_serr : 1; unsigned perror_v_perr : 1; unsigned perror_v_dcrto : 1; unsigned perror_v_sge : 1; unsigned perror_v_ape : 1; unsigned perror_v_ta : 1; unsigned perror_v_rdpe : 1; unsigned perror_v_nds : 1; unsigned perror_v_rto : 1; unsigned perror_v_uecc : 1; unsigned perror_v_cre : 1; unsigned perror_v_rsvd1 : 4; unsigned perror_v_addrl : 32; unsigned perror_v_addrh : 3; unsigned perror_v_rsvd2 : 1; unsigned perror_v_cmd : 4; unsigned perror_v_syn : 8; } perror_r_bits; int perror_q_whole [2]; }; /* * TSUNAMI Pchip Window Space Base Address register. */ #define wsba_m_ena 0x1 #define wsba_m_sg 0x2 #define wsba_m_ptp 0x4 #define wsba_m_addr 0xFFF00000 #define wmask_k_sz1gb 0x3FF00000 union TPchipWSBA { struct { unsigned wsba_v_ena : 1; unsigned wsba_v_sg : 1; unsigned wsba_v_ptp : 1; unsigned wsba_v_rsvd1 : 17; unsigned wsba_v_addr : 12; unsigned wsba_v_rsvd2 : 32; } wsba_r_bits; int wsba_q_whole [2]; }; /* * TSUNAMI Pchip Control Register */ #define pctl_m_fdsc 0x1 #define pctl_m_fbtb 0x2 #define pctl_m_thdis 0x4 #define pctl_m_chaindis 0x8 #define pctl_m_tgtlat 0x10 #define pctl_m_hole 0x20 #define pctl_m_mwin 0x40 #define pctl_m_arbena 0x80 #define pctl_m_prigrp 0x7F00 #define pctl_m_ppri 0x8000 #define pctl_m_rsvd1 0x30000 #define pctl_m_eccen 0x40000 #define pctl_m_padm 0x80000 #define pctl_m_cdqmax 0xF00000 #define pctl_m_rev 0xFF000000 #define pctl_m_crqmax 0xF00000000UL #define pctl_m_ptpmax 0xF000000000UL #define pctl_m_pclkx 0x30000000000UL #define pctl_m_fdsdis 0x40000000000UL #define pctl_m_fdwdis 0x80000000000UL #define pctl_m_ptevrfy 0x100000000000UL #define pctl_m_rpp 0x200000000000UL #define pctl_m_pid 0xC00000000000UL #define pctl_m_rsvd2 0xFFFF000000000000UL union TPchipPCTL { struct { unsigned pctl_v_fdsc : 1; unsigned pctl_v_fbtb : 1; unsigned pctl_v_thdis : 1; unsigned pctl_v_chaindis : 1; unsigned pctl_v_tgtlat : 1; unsigned pctl_v_hole : 1; unsigned pctl_v_mwin : 1; unsigned pctl_v_arbena : 1; unsigned pctl_v_prigrp : 7; unsigned pctl_v_ppri : 1; unsigned pctl_v_rsvd1 : 2; unsigned pctl_v_eccen : 1; unsigned pctl_v_padm : 1; unsigned pctl_v_cdqmax : 4; unsigned pctl_v_rev : 8; unsigned pctl_v_crqmax : 4; unsigned pctl_v_ptpmax : 4; unsigned pctl_v_pclkx : 2; unsigned pctl_v_fdsdis : 1; unsigned pctl_v_fdwdis : 1; unsigned pctl_v_ptevrfy : 1; unsigned pctl_v_rpp : 1; unsigned pctl_v_pid : 2; unsigned pctl_v_rsvd2 : 16; } pctl_r_bits; int pctl_q_whole [2]; }; /* * TSUNAMI Pchip Error Mask Register. */ #define perrmask_m_lost 0x1 #define perrmask_m_serr 0x2 #define perrmask_m_perr 0x4 #define perrmask_m_dcrto 0x8 #define perrmask_m_sge 0x10 #define perrmask_m_ape 0x20 #define perrmask_m_ta 0x40 #define perrmask_m_rdpe 0x80 #define perrmask_m_nds 0x100 #define perrmask_m_rto 0x200 #define perrmask_m_uecc 0x400 #define perrmask_m_cre 0x800 #define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL union TPchipPERRMASK { struct { unsigned int perrmask_v_lost : 1; unsigned perrmask_v_serr : 1; unsigned perrmask_v_perr : 1; unsigned perrmask_v_dcrto : 1; unsigned perrmask_v_sge : 1; unsigned perrmask_v_ape : 1; unsigned perrmask_v_ta : 1; unsigned perrmask_v_rdpe : 1; unsigned perrmask_v_nds : 1; unsigned perrmask_v_rto : 1; unsigned perrmask_v_uecc : 1; unsigned perrmask_v_cre : 1; unsigned perrmask_v_rsvd1 : 20; unsigned perrmask_v_rsvd2 : 32; } perrmask_r_bits; int perrmask_q_whole [2]; }; /* * Memory spaces: */ #define TSUNAMI_HOSE(h) (((unsigned long)(h)) << 33) #define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS) #define TSUNAMI_MEM(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL) #define _TSUNAMI_IACK_SC(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL) #define TSUNAMI_IO(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL) #define TSUNAMI_CONF(h) (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL) #define TSUNAMI_IACK_SC _TSUNAMI_IACK_SC(0) /* hack! */ /* * The canonical non-remaped I/O and MEM addresses have these values * subtracted out. This is arranged so that folks manipulating ISA * devices can use their familiar numbers and have them map to bus 0. */ #define TSUNAMI_IO_BIAS TSUNAMI_IO(0) #define TSUNAMI_MEM_BIAS TSUNAMI_MEM(0) /* The IO address space is larger than 0xffff */ #define TSUNAMI_IO_SPACE (TSUNAMI_CONF(0) - TSUNAMI_IO(0)) /* Offset between ram physical addresses and pci64 DAC bus addresses. */ #define TSUNAMI_DAC_OFFSET (1UL << 40) /* * Data structure for handling TSUNAMI machine checks: */ struct el_TSUNAMI_sysdata_mcheck { }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264) * can only use linear accesses to get at PCI memory and I/O spaces. */ /* * Memory functions. all accesses are done through linear space. */ extern void __iomem *tsunami_ioportmap(unsigned long addr); extern void __iomem *tsunami_ioremap(unsigned long addr, unsigned long size); __EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr) { return addr >= TSUNAMI_BASE; } __EXTERN_INLINE int tsunami_is_mmio(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; return (addr & 0x100000000UL) == 0; } #undef __IO_PREFIX #define __IO_PREFIX tsunami #define tsunami_trivial_rw_bw 1 #define tsunami_trivial_rw_lq 1 #define tsunami_trivial_io_bw 1 #define tsunami_trivial_io_lq 1 #define tsunami_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_TSUNAMI__H__ */ PK ! z�x1 x1 dma.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * include/asm-alpha/dma.h * * This is essentially the same as the i386 DMA stuff, as the AlphaPCs * use ISA-compatible dma. The only extension is support for high-page * registers that allow to set the top 8 bits of a 32-bit DMA address. * This register should be written last when setting up a DMA address * as this will also enable DMA across 64 KB boundaries. */ /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $ * linux/include/asm/dma.h: Defines for using and allocating dma channels. * Written by Hennus Bergman, 1992. * High DMA channel support & info by Hannu Savolainen * and John Boyd, Nov. 1992. */ #ifndef _ASM_DMA_H #define _ASM_DMA_H #include <linux/spinlock.h> #include <asm/io.h> #define dma_outb outb #define dma_inb inb /* * NOTES about DMA transfers: * * controller 1: channels 0-3, byte operations, ports 00-1F * controller 2: channels 4-7, word operations, ports C0-DF * * - ALL registers are 8 bits only, regardless of transfer size * - channel 4 is not used - cascades 1 into 2. * - channels 0-3 are byte - addresses/counts are for physical bytes * - channels 5-7 are word - addresses/counts are for physical words * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries * - transfer count loaded to registers is 1 less than actual count * - controller 2 offsets are all even (2x offsets for controller 1) * - page registers for 5-7 don't use data bit 0, represent 128K pages * - page registers for 0-3 use bit 0, represent 64K pages * * DMA transfers are limited to the lower 16MB of _physical_ memory. * Note that addresses loaded into registers must be _physical_ addresses, * not logical addresses (which may differ if paging is active). * * Address mapping for channels 0-3: * * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) * | ... | | ... | | ... | * | ... | | ... | | ... | * | ... | | ... | | ... | * P7 ... P0 A7 ... A0 A7 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Address mapping for channels 5-7: * * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) * | ... | \ \ ... \ \ \ ... \ \ * | ... | \ \ ... \ \ \ ... \ (not used) * | ... | \ \ ... \ \ \ ... \ * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at * the hardware level, so odd-byte transfers aren't possible). * * Transfer count (_not # bytes_) is limited to 64K, represented as actual * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, * and up to 128K bytes may be transferred on channels 5-7 in one operation. * */ #define MAX_DMA_CHANNELS 8 /* ISA DMA limitations on Alpha platforms, These may be due to SIO (PCI<->ISA bridge) chipset limitation, or just a wiring limit. */ /* The maximum address for ISA DMA transfer on Alpha XL, due to an hardware SIO limitation, is 64MB. */ #define ALPHA_XL_MAX_ISA_DMA_ADDRESS 0x04000000UL /* The maximum address for ISA DMA transfer on RUFFIAN, due to an hardware SIO limitation, is 16MB. */ #define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS 0x01000000UL /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs, due to an hardware SIO chip limitation, is 2GB. */ #define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS 0x80000000UL #define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS 0x80000000UL /* Maximum address for all the others is the complete 32-bit bus address space. */ #define ALPHA_MAX_ISA_DMA_ADDRESS 0x100000000UL #ifdef CONFIG_ALPHA_GENERIC # define MAX_ISA_DMA_ADDRESS (alpha_mv.max_isa_dma_address) #else # if defined(CONFIG_ALPHA_XL) # define MAX_ISA_DMA_ADDRESS ALPHA_XL_MAX_ISA_DMA_ADDRESS # elif defined(CONFIG_ALPHA_RUFFIAN) # define MAX_ISA_DMA_ADDRESS ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS # elif defined(CONFIG_ALPHA_SABLE) # define MAX_ISA_DMA_ADDRESS ALPHA_SABLE_MAX_ISA_DMA_ADDRESS # elif defined(CONFIG_ALPHA_ALCOR) # define MAX_ISA_DMA_ADDRESS ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS # else # define MAX_ISA_DMA_ADDRESS ALPHA_MAX_ISA_DMA_ADDRESS # endif #endif /* If we have the iommu, we don't have any address limitations on DMA. Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone like i386. */ #define MAX_DMA_ADDRESS (alpha_mv.mv_pci_tbi ? \ ~0UL : IDENT_ADDR + 0x01000000) /* 8237 DMA controllers */ #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ /* DMA controller registers */ #define DMA1_CMD_REG 0x08 /* command register (w) */ #define DMA1_STAT_REG 0x08 /* status register (r) */ #define DMA1_REQ_REG 0x09 /* request register (w) */ #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ #define DMA1_MODE_REG 0x0B /* mode register (w) */ #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) #define DMA2_CMD_REG 0xD0 /* command register (w) */ #define DMA2_STAT_REG 0xD0 /* status register (r) */ #define DMA2_REQ_REG 0xD2 /* request register (w) */ #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ #define DMA2_MODE_REG 0xD6 /* mode register (w) */ #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) #define DMA_ADDR_0 0x00 /* DMA address registers */ #define DMA_ADDR_1 0x02 #define DMA_ADDR_2 0x04 #define DMA_ADDR_3 0x06 #define DMA_ADDR_4 0xC0 #define DMA_ADDR_5 0xC4 #define DMA_ADDR_6 0xC8 #define DMA_ADDR_7 0xCC #define DMA_CNT_0 0x01 /* DMA count registers */ #define DMA_CNT_1 0x03 #define DMA_CNT_2 0x05 #define DMA_CNT_3 0x07 #define DMA_CNT_4 0xC2 #define DMA_CNT_5 0xC6 #define DMA_CNT_6 0xCA #define DMA_CNT_7 0xCE #define DMA_PAGE_0 0x87 /* DMA page registers */ #define DMA_PAGE_1 0x83 #define DMA_PAGE_2 0x81 #define DMA_PAGE_3 0x82 #define DMA_PAGE_5 0x8B #define DMA_PAGE_6 0x89 #define DMA_PAGE_7 0x8A #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0) #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1) #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2) #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3) #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4) #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5) #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6) #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7) #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ #define DMA_AUTOINIT 0x10 extern spinlock_t dma_spin_lock; static __inline__ unsigned long claim_dma_lock(void) { unsigned long flags; spin_lock_irqsave(&dma_spin_lock, flags); return flags; } static __inline__ void release_dma_lock(unsigned long flags) { spin_unlock_irqrestore(&dma_spin_lock, flags); } /* enable/disable a specific DMA channel */ static __inline__ void enable_dma(unsigned int dmanr) { if (dmanr<=3) dma_outb(dmanr, DMA1_MASK_REG); else dma_outb(dmanr & 3, DMA2_MASK_REG); } static __inline__ void disable_dma(unsigned int dmanr) { if (dmanr<=3) dma_outb(dmanr | 4, DMA1_MASK_REG); else dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); } /* Clear the 'DMA Pointer Flip Flop'. * Write 0 for LSB/MSB, 1 for MSB/LSB access. * Use this once to initialize the FF to a known state. * After that, keep track of it. :-) * --- In order to do that, the DMA routines below should --- * --- only be used while interrupts are disabled! --- */ static __inline__ void clear_dma_ff(unsigned int dmanr) { if (dmanr<=3) dma_outb(0, DMA1_CLEAR_FF_REG); else dma_outb(0, DMA2_CLEAR_FF_REG); } /* set mode (above) for a specific DMA channel */ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) { if (dmanr<=3) dma_outb(mode | dmanr, DMA1_MODE_REG); else dma_outb(mode | (dmanr&3), DMA2_MODE_REG); } /* set extended mode for a specific DMA channel */ static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode) { if (dmanr<=3) dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG); else dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG); } /* Set only the page register bits of the transfer address. * This is used for successive transfers when we know the contents of * the lower 16 bits of the DMA current address register. */ static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr) { switch(dmanr) { case 0: dma_outb(pagenr, DMA_PAGE_0); dma_outb((pagenr >> 8), DMA_HIPAGE_0); break; case 1: dma_outb(pagenr, DMA_PAGE_1); dma_outb((pagenr >> 8), DMA_HIPAGE_1); break; case 2: dma_outb(pagenr, DMA_PAGE_2); dma_outb((pagenr >> 8), DMA_HIPAGE_2); break; case 3: dma_outb(pagenr, DMA_PAGE_3); dma_outb((pagenr >> 8), DMA_HIPAGE_3); break; case 5: dma_outb(pagenr & 0xfe, DMA_PAGE_5); dma_outb((pagenr >> 8), DMA_HIPAGE_5); break; case 6: dma_outb(pagenr & 0xfe, DMA_PAGE_6); dma_outb((pagenr >> 8), DMA_HIPAGE_6); break; case 7: dma_outb(pagenr & 0xfe, DMA_PAGE_7); dma_outb((pagenr >> 8), DMA_HIPAGE_7); break; } } /* Set transfer address & page bits for specific DMA channel. * Assumes dma flipflop is clear. */ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) { if (dmanr <= 3) { dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); } else { dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); } set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */ } /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for * a specific DMA channel. * You must ensure the parameters are valid. * NOTE: from a manual: "the number of transfers is one more * than the initial word count"! This is taken into account. * Assumes dma flip-flop is clear. * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. */ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) { count--; if (dmanr <= 3) { dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); } else { dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); } } /* Get DMA residue count. After a DMA transfer, this * should return zero. Reading this while a DMA transfer is * still in progress will return unpredictable results. * If called before the channel has been used, it may return 1. * Otherwise, it returns the number of _bytes_ left to transfer. * * Assumes DMA flip-flop is clear. */ static __inline__ int get_dma_residue(unsigned int dmanr) { unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; /* using short to get 16-bit wrap around */ unsigned short count; count = 1 + dma_inb(io_port); count += dma_inb(io_port) << 8; return (dmanr<=3)? count : (count<<1); } /* These are in kernel/dma.c: */ extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ #define KERNEL_HAVE_CHECK_DMA extern int check_dma(unsigned int dmanr); /* From PCI */ #ifdef CONFIG_PCI extern int isa_dma_bridge_buggy; #else #define isa_dma_bridge_buggy (0) #endif #endif /* _ASM_DMA_H */ PK ! l���: : io.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_IO_H #define __ALPHA_IO_H #ifdef __KERNEL__ #include <linux/kernel.h> #include <linux/mm.h> #include <asm/compiler.h> #include <asm/machvec.h> #include <asm/hwrpb.h> /* The generic header contains only prototypes. Including it ensures that the implementation we have here matches that interface. */ #include <asm-generic/iomap.h> /* We don't use IO slowdowns on the Alpha, but.. */ #define __SLOW_DOWN_IO do { } while (0) #define SLOW_DOWN_IO do { } while (0) /* * Virtual -> physical identity mapping starts at this offset */ #ifdef USE_48_BIT_KSEG #define IDENT_ADDR 0xffff800000000000UL #else #define IDENT_ADDR 0xfffffc0000000000UL #endif /* * We try to avoid hae updates (thus the cache), but when we * do need to update the hae, we need to do it atomically, so * that any interrupts wouldn't get confused with the hae * register not being up-to-date with respect to the hardware * value. */ extern inline void __set_hae(unsigned long new_hae) { unsigned long flags = swpipl(IPL_MAX); barrier(); alpha_mv.hae_cache = new_hae; *alpha_mv.hae_register = new_hae; mb(); /* Re-read to make sure it was written. */ new_hae = *alpha_mv.hae_register; setipl(flags); barrier(); } extern inline void set_hae(unsigned long new_hae) { if (new_hae != alpha_mv.hae_cache) __set_hae(new_hae); } /* * Change virtual addresses to physical addresses and vv. */ #ifdef USE_48_BIT_KSEG static inline unsigned long virt_to_phys(volatile void *address) { return (unsigned long)address - IDENT_ADDR; } static inline void * phys_to_virt(unsigned long address) { return (void *) (address + IDENT_ADDR); } #else static inline unsigned long virt_to_phys(volatile void *address) { unsigned long phys = (unsigned long)address; /* Sign-extend from bit 41. */ phys <<= (64 - 41); phys = (long)phys >> (64 - 41); /* Crop to the physical address width of the processor. */ phys &= (1ul << hwrpb->pa_bits) - 1; return phys; } static inline void * phys_to_virt(unsigned long address) { return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); } #endif #define page_to_phys(page) page_to_pa(page) /* Maximum PIO space address supported? */ #define IO_SPACE_LIMIT 0xffff /* * Change addresses as seen by the kernel (virtual) to addresses as * seen by a device (bus), and vice versa. * * Note that this only works for a limited range of kernel addresses, * and very well may not span all memory. Consider this interface * deprecated in favour of the DMA-mapping API. */ extern unsigned long __direct_map_base; extern unsigned long __direct_map_size; static inline unsigned long __deprecated virt_to_bus(volatile void *address) { unsigned long phys = virt_to_phys(address); unsigned long bus = phys + __direct_map_base; return phys <= __direct_map_size ? bus : 0; } #define isa_virt_to_bus virt_to_bus static inline void * __deprecated bus_to_virt(unsigned long address) { void *virt; /* This check is a sanity check but also ensures that bus address 0 maps to virtual address 0 which is useful to detect null pointers (the NCR driver is much simpler if NULL pointers are preserved). */ address -= __direct_map_base; virt = phys_to_virt(address); return (long)address <= 0 ? NULL : virt; } #define isa_bus_to_virt bus_to_virt /* * There are different chipsets to interface the Alpha CPUs to the world. */ #define IO_CONCAT(a,b) _IO_CONCAT(a,b) #define _IO_CONCAT(a,b) a ## _ ## b #ifdef CONFIG_ALPHA_GENERIC /* In a generic kernel, we always go through the machine vector. */ #define REMAP1(TYPE, NAME, QUAL) \ static inline TYPE generic_##NAME(QUAL void __iomem *addr) \ { \ return alpha_mv.mv_##NAME(addr); \ } #define REMAP2(TYPE, NAME, QUAL) \ static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \ { \ alpha_mv.mv_##NAME(b, addr); \ } REMAP1(unsigned int, ioread8, const) REMAP1(unsigned int, ioread16, const) REMAP1(unsigned int, ioread32, const) REMAP1(u8, readb, const volatile) REMAP1(u16, readw, const volatile) REMAP1(u32, readl, const volatile) REMAP1(u64, readq, const volatile) REMAP2(u8, iowrite8, /**/) REMAP2(u16, iowrite16, /**/) REMAP2(u32, iowrite32, /**/) REMAP2(u8, writeb, volatile) REMAP2(u16, writew, volatile) REMAP2(u32, writel, volatile) REMAP2(u64, writeq, volatile) #undef REMAP1 #undef REMAP2 extern inline void __iomem *generic_ioportmap(unsigned long a) { return alpha_mv.mv_ioportmap(a); } static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s) { return alpha_mv.mv_ioremap(a, s); } static inline void generic_iounmap(volatile void __iomem *a) { return alpha_mv.mv_iounmap(a); } static inline int generic_is_ioaddr(unsigned long a) { return alpha_mv.mv_is_ioaddr(a); } static inline int generic_is_mmio(const volatile void __iomem *a) { return alpha_mv.mv_is_mmio(a); } #define __IO_PREFIX generic #define generic_trivial_rw_bw 0 #define generic_trivial_rw_lq 0 #define generic_trivial_io_bw 0 #define generic_trivial_io_lq 0 #define generic_trivial_iounmap 0 #else #if defined(CONFIG_ALPHA_APECS) # include <asm/core_apecs.h> #elif defined(CONFIG_ALPHA_CIA) # include <asm/core_cia.h> #elif defined(CONFIG_ALPHA_IRONGATE) # include <asm/core_irongate.h> #elif defined(CONFIG_ALPHA_JENSEN) # include <asm/jensen.h> #elif defined(CONFIG_ALPHA_LCA) # include <asm/core_lca.h> #elif defined(CONFIG_ALPHA_MARVEL) # include <asm/core_marvel.h> #elif defined(CONFIG_ALPHA_MCPCIA) # include <asm/core_mcpcia.h> #elif defined(CONFIG_ALPHA_POLARIS) # include <asm/core_polaris.h> #elif defined(CONFIG_ALPHA_T2) # include <asm/core_t2.h> #elif defined(CONFIG_ALPHA_TSUNAMI) # include <asm/core_tsunami.h> #elif defined(CONFIG_ALPHA_TITAN) # include <asm/core_titan.h> #elif defined(CONFIG_ALPHA_WILDFIRE) # include <asm/core_wildfire.h> #else #error "What system is this?" #endif #endif /* GENERIC */ /* * We always have external versions of these routines. */ extern u8 inb(unsigned long port); extern u16 inw(unsigned long port); extern u32 inl(unsigned long port); extern void outb(u8 b, unsigned long port); extern void outw(u16 b, unsigned long port); extern void outl(u32 b, unsigned long port); extern u8 readb(const volatile void __iomem *addr); extern u16 readw(const volatile void __iomem *addr); extern u32 readl(const volatile void __iomem *addr); extern u64 readq(const volatile void __iomem *addr); extern void writeb(u8 b, volatile void __iomem *addr); extern void writew(u16 b, volatile void __iomem *addr); extern void writel(u32 b, volatile void __iomem *addr); extern void writeq(u64 b, volatile void __iomem *addr); extern u8 __raw_readb(const volatile void __iomem *addr); extern u16 __raw_readw(const volatile void __iomem *addr); extern u32 __raw_readl(const volatile void __iomem *addr); extern u64 __raw_readq(const volatile void __iomem *addr); extern void __raw_writeb(u8 b, volatile void __iomem *addr); extern void __raw_writew(u16 b, volatile void __iomem *addr); extern void __raw_writel(u32 b, volatile void __iomem *addr); extern void __raw_writeq(u64 b, volatile void __iomem *addr); /* * Mapping from port numbers to __iomem space is pretty easy. */ /* These two have to be extern inline because of the extern prototype from <asm-generic/iomap.h>. It is not legal to mix "extern" and "static" for the same declaration. */ extern inline void __iomem *ioport_map(unsigned long port, unsigned int size) { return IO_CONCAT(__IO_PREFIX,ioportmap) (port); } extern inline void ioport_unmap(void __iomem *addr) { } static inline void __iomem *ioremap(unsigned long port, unsigned long size) { return IO_CONCAT(__IO_PREFIX,ioremap) (port, size); } #define ioremap_wc ioremap #define ioremap_uc ioremap static inline void iounmap(volatile void __iomem *addr) { IO_CONCAT(__IO_PREFIX,iounmap)(addr); } static inline int __is_ioaddr(unsigned long addr) { return IO_CONCAT(__IO_PREFIX,is_ioaddr)(addr); } #define __is_ioaddr(a) __is_ioaddr((unsigned long)(a)) static inline int __is_mmio(const volatile void __iomem *addr) { return IO_CONCAT(__IO_PREFIX,is_mmio)(addr); } /* * If the actual I/O bits are sufficiently trivial, then expand inline. */ #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) extern inline unsigned int ioread8(const void __iomem *addr) { unsigned int ret; mb(); ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr); mb(); return ret; } extern inline unsigned int ioread16(const void __iomem *addr) { unsigned int ret; mb(); ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr); mb(); return ret; } extern inline void iowrite8(u8 b, void __iomem *addr) { mb(); IO_CONCAT(__IO_PREFIX, iowrite8)(b, addr); } extern inline void iowrite16(u16 b, void __iomem *addr) { mb(); IO_CONCAT(__IO_PREFIX, iowrite16)(b, addr); } extern inline u8 inb(unsigned long port) { return ioread8(ioport_map(port, 1)); } extern inline u16 inw(unsigned long port) { return ioread16(ioport_map(port, 2)); } extern inline void outb(u8 b, unsigned long port) { iowrite8(b, ioport_map(port, 1)); } extern inline void outw(u16 b, unsigned long port) { iowrite16(b, ioport_map(port, 2)); } #endif #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) extern inline unsigned int ioread32(const void __iomem *addr) { unsigned int ret; mb(); ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr); mb(); return ret; } extern inline void iowrite32(u32 b, void __iomem *addr) { mb(); IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr); } extern inline u32 inl(unsigned long port) { return ioread32(ioport_map(port, 4)); } extern inline void outl(u32 b, unsigned long port) { iowrite32(b, ioport_map(port, 4)); } #endif #if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1 extern inline u8 __raw_readb(const volatile void __iomem *addr) { return IO_CONCAT(__IO_PREFIX,readb)(addr); } extern inline u16 __raw_readw(const volatile void __iomem *addr) { return IO_CONCAT(__IO_PREFIX,readw)(addr); } extern inline void __raw_writeb(u8 b, volatile void __iomem *addr) { IO_CONCAT(__IO_PREFIX,writeb)(b, addr); } extern inline void __raw_writew(u16 b, volatile void __iomem *addr) { IO_CONCAT(__IO_PREFIX,writew)(b, addr); } extern inline u8 readb(const volatile void __iomem *addr) { u8 ret; mb(); ret = __raw_readb(addr); mb(); return ret; } extern inline u16 readw(const volatile void __iomem *addr) { u16 ret; mb(); ret = __raw_readw(addr); mb(); return ret; } extern inline void writeb(u8 b, volatile void __iomem *addr) { mb(); __raw_writeb(b, addr); } extern inline void writew(u16 b, volatile void __iomem *addr) { mb(); __raw_writew(b, addr); } #endif #if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1 extern inline u32 __raw_readl(const volatile void __iomem *addr) { return IO_CONCAT(__IO_PREFIX,readl)(addr); } extern inline u64 __raw_readq(const volatile void __iomem *addr) { return IO_CONCAT(__IO_PREFIX,readq)(addr); } extern inline void __raw_writel(u32 b, volatile void __iomem *addr) { IO_CONCAT(__IO_PREFIX,writel)(b, addr); } extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) { IO_CONCAT(__IO_PREFIX,writeq)(b, addr); } extern inline u32 readl(const volatile void __iomem *addr) { u32 ret; mb(); ret = __raw_readl(addr); mb(); return ret; } extern inline u64 readq(const volatile void __iomem *addr) { u64 ret; mb(); ret = __raw_readq(addr); mb(); return ret; } extern inline void writel(u32 b, volatile void __iomem *addr) { mb(); __raw_writel(b, addr); } extern inline void writeq(u64 b, volatile void __iomem *addr) { mb(); __raw_writeq(b, addr); } #endif #define ioread16be(p) swab16(ioread16(p)) #define ioread32be(p) swab32(ioread32(p)) #define iowrite16be(v,p) iowrite16(swab16(v), (p)) #define iowrite32be(v,p) iowrite32(swab32(v), (p)) #define inb_p inb #define inw_p inw #define inl_p inl #define outb_p outb #define outw_p outw #define outl_p outl extern u8 readb_relaxed(const volatile void __iomem *addr); extern u16 readw_relaxed(const volatile void __iomem *addr); extern u32 readl_relaxed(const volatile void __iomem *addr); extern u64 readq_relaxed(const volatile void __iomem *addr); #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) extern inline u8 readb_relaxed(const volatile void __iomem *addr) { mb(); return __raw_readb(addr); } extern inline u16 readw_relaxed(const volatile void __iomem *addr) { mb(); return __raw_readw(addr); } #endif #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) extern inline u32 readl_relaxed(const volatile void __iomem *addr) { mb(); return __raw_readl(addr); } extern inline u64 readq_relaxed(const volatile void __iomem *addr) { mb(); return __raw_readq(addr); } #endif #define writeb_relaxed writeb #define writew_relaxed writew #define writel_relaxed writel #define writeq_relaxed writeq /* * String version of IO memory access ops: */ extern void memcpy_fromio(void *, const volatile void __iomem *, long); extern void memcpy_toio(volatile void __iomem *, const void *, long); extern void _memset_c_io(volatile void __iomem *, unsigned long, long); static inline void memset_io(volatile void __iomem *addr, u8 c, long len) { _memset_c_io(addr, 0x0101010101010101UL * c, len); } #define __HAVE_ARCH_MEMSETW_IO static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len) { _memset_c_io(addr, 0x0001000100010001UL * c, len); } /* * String versions of in/out ops: */ extern void insb (unsigned long port, void *dst, unsigned long count); extern void insw (unsigned long port, void *dst, unsigned long count); extern void insl (unsigned long port, void *dst, unsigned long count); extern void outsb (unsigned long port, const void *src, unsigned long count); extern void outsw (unsigned long port, const void *src, unsigned long count); extern void outsl (unsigned long port, const void *src, unsigned long count); /* * The Alpha Jensen hardware for some rather strange reason puts * the RTC clock at 0x170 instead of 0x70. Probably due to some * misguided idea about using 0x70 for NMI stuff. * * These defines will override the defaults when doing RTC queries */ #ifdef CONFIG_ALPHA_GENERIC # define RTC_PORT(x) ((x) + alpha_mv.rtc_port) #else # ifdef CONFIG_ALPHA_JENSEN # define RTC_PORT(x) (0x170+(x)) # else # define RTC_PORT(x) (0x70 + (x)) # endif #endif #define RTC_ALWAYS_BCD 0 /* * Some mucking forons use if[n]def writeq to check if platform has it. * It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them * to play with; for now just use cpp anti-recursion logics and make sure * that damn thing is defined and expands to itself. */ #define writeq writeq #define readq readq /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem * access */ #define xlate_dev_mem_ptr(p) __va(p) #endif /* __KERNEL__ */ #endif /* __ALPHA_IO_H */ PK ! � !P� � xchg.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_CMPXCHG_H #error Do not include xchg.h directly! #else /* * xchg/xchg_local and cmpxchg/cmpxchg_local share the same code * except that local version do not have the expensive memory barrier. * So this file is included twice from asm/cmpxchg.h. */ /* * Atomic exchange. * Since it can be used to implement critical sections * it must clobber "memory" (also for interrupts in UP). */ static inline unsigned long ____xchg(_u8, volatile char *m, unsigned long val) { unsigned long ret, tmp, addr64; __asm__ __volatile__( " andnot %4,7,%3\n" " insbl %1,%4,%1\n" "1: ldq_l %2,0(%3)\n" " extbl %2,%4,%0\n" " mskbl %2,%4,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%3)\n" " beq %2,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64) : "r" ((long)m), "1" (val) : "memory"); return ret; } static inline unsigned long ____xchg(_u16, volatile short *m, unsigned long val) { unsigned long ret, tmp, addr64; __asm__ __volatile__( " andnot %4,7,%3\n" " inswl %1,%4,%1\n" "1: ldq_l %2,0(%3)\n" " extwl %2,%4,%0\n" " mskwl %2,%4,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%3)\n" " beq %2,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64) : "r" ((long)m), "1" (val) : "memory"); return ret; } static inline unsigned long ____xchg(_u32, volatile int *m, unsigned long val) { unsigned long dummy; __asm__ __volatile__( "1: ldl_l %0,%4\n" " bis $31,%3,%1\n" " stl_c %1,%2\n" " beq %1,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (val), "=&r" (dummy), "=m" (*m) : "rI" (val), "m" (*m) : "memory"); return val; } static inline unsigned long ____xchg(_u64, volatile long *m, unsigned long val) { unsigned long dummy; __asm__ __volatile__( "1: ldq_l %0,%4\n" " bis $31,%3,%1\n" " stq_c %1,%2\n" " beq %1,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" : "=&r" (val), "=&r" (dummy), "=m" (*m) : "rI" (val), "m" (*m) : "memory"); return val; } /* This function doesn't exist, so you'll get a linker error if something tries to do an invalid xchg(). */ extern void __xchg_called_with_bad_pointer(void); static __always_inline unsigned long ____xchg(, volatile void *ptr, unsigned long x, int size) { switch (size) { case 1: return ____xchg(_u8, ptr, x); case 2: return ____xchg(_u16, ptr, x); case 4: return ____xchg(_u32, ptr, x); case 8: return ____xchg(_u64, ptr, x); } __xchg_called_with_bad_pointer(); return x; } /* * Atomic compare and exchange. Compare OLD with MEM, if identical, * store NEW in MEM. Return the initial value in MEM. Success is * indicated by comparing RETURN with OLD. */ static inline unsigned long ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new) { unsigned long prev, tmp, cmp, addr64; __asm__ __volatile__( " andnot %5,7,%4\n" " insbl %1,%5,%1\n" "1: ldq_l %2,0(%4)\n" " extbl %2,%5,%0\n" " cmpeq %0,%6,%3\n" " beq %3,2f\n" " mskbl %2,%5,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%4)\n" " beq %2,3f\n" "2:\n" ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64) : "r" ((long)m), "Ir" (old), "1" (new) : "memory"); return prev; } static inline unsigned long ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new) { unsigned long prev, tmp, cmp, addr64; __asm__ __volatile__( " andnot %5,7,%4\n" " inswl %1,%5,%1\n" "1: ldq_l %2,0(%4)\n" " extwl %2,%5,%0\n" " cmpeq %0,%6,%3\n" " beq %3,2f\n" " mskwl %2,%5,%2\n" " or %1,%2,%2\n" " stq_c %2,0(%4)\n" " beq %2,3f\n" "2:\n" ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64) : "r" ((long)m), "Ir" (old), "1" (new) : "memory"); return prev; } static inline unsigned long ____cmpxchg(_u32, volatile int *m, int old, int new) { unsigned long prev, cmp; __asm__ __volatile__( "1: ldl_l %0,%5\n" " cmpeq %0,%3,%1\n" " beq %1,2f\n" " mov %4,%1\n" " stl_c %1,%2\n" " beq %1,3f\n" "2:\n" ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r"(prev), "=&r"(cmp), "=m"(*m) : "r"((long) old), "r"(new), "m"(*m) : "memory"); return prev; } static inline unsigned long ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new) { unsigned long prev, cmp; __asm__ __volatile__( "1: ldq_l %0,%5\n" " cmpeq %0,%3,%1\n" " beq %1,2f\n" " mov %4,%1\n" " stq_c %1,%2\n" " beq %1,3f\n" "2:\n" ".subsection 2\n" "3: br 1b\n" ".previous" : "=&r"(prev), "=&r"(cmp), "=m"(*m) : "r"((long) old), "r"(new), "m"(*m) : "memory"); return prev; } /* This function doesn't exist, so you'll get a linker error if something tries to do an invalid cmpxchg(). */ extern void __cmpxchg_called_with_bad_pointer(void); static __always_inline unsigned long ____cmpxchg(, volatile void *ptr, unsigned long old, unsigned long new, int size) { switch (size) { case 1: return ____cmpxchg(_u8, ptr, old, new); case 2: return ____cmpxchg(_u16, ptr, old, new); case 4: return ____cmpxchg(_u32, ptr, old, new); case 8: return ____cmpxchg(_u64, ptr, old, new); } __cmpxchg_called_with_bad_pointer(); return old; } #endif PK ! 1�=�� � switch_to.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_SWITCH_TO_H #define __ALPHA_SWITCH_TO_H struct task_struct; extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct *); #define switch_to(P,N,L) \ do { \ (L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \ check_mmu_context(); \ } while (0) #endif /* __ALPHA_SWITCH_TO_H */ PK ! J|{#!1 !1 pgtable.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_PGTABLE_H #define _ALPHA_PGTABLE_H #include <asm-generic/pgtable-nopud.h> /* * This file contains the functions and defines necessary to modify and use * the Alpha page table tree. * * This hopefully works with any standard Alpha page-size, as defined * in <asm/page.h> (currently 8192). */ #include <linux/mmzone.h> #include <asm/page.h> #include <asm/processor.h> /* For TASK_SIZE */ #include <asm/machvec.h> #include <asm/setup.h> struct mm_struct; struct vm_area_struct; /* Certain architectures need to do special things when PTEs * within a page table are directly modified. Thus, the following * hook is made available. */ #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) /* PMD_SHIFT determines the size of the area a second-level page table can map */ #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) /* PGDIR_SHIFT determines what a third-level page table entry can map */ #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3)) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* * Entries per page directory level: the Alpha is three-level, with * all levels having a one-page page table. */ #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3)) #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3)) #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) /* Number of pointers that fit on a page: this will go away. */ #define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3)) #ifdef CONFIG_ALPHA_LARGE_VMALLOC #define VMALLOC_START 0xfffffe0000000000 #else #define VMALLOC_START (-2*PGDIR_SIZE) #endif #define VMALLOC_END (-PGDIR_SIZE) /* * OSF/1 PAL-code-imposed page table bits */ #define _PAGE_VALID 0x0001 #define _PAGE_FOR 0x0002 /* used for page protection (fault on read) */ #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */ #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */ #define _PAGE_ASM 0x0010 #define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */ #define _PAGE_URE 0x0200 /* xxx */ #define _PAGE_KWE 0x1000 /* used to do the dirty bit in software */ #define _PAGE_UWE 0x2000 /* used to do the dirty bit in software */ /* .. and these are ours ... */ #define _PAGE_DIRTY 0x20000 #define _PAGE_ACCESSED 0x40000 /* * NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it. * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use * the KRE/URE bits to watch for it. That way we don't need to overload the * KWE/UWE bits with both handling dirty and accessed. * * Note that the kernel uses the accessed bit just to check whether to page * out a page or not, so it doesn't have to be exact anyway. */ #define __DIRTY_BITS (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE) #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE) #define _PFN_MASK 0xFFFFFFFF00000000UL #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS) #define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS) /* * All the normal masks have the "page accessed" bits on, as any time they are used, * the page is accessed. They are cleared only by the page-out routines */ #define PAGE_NONE __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE) #define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS) #define PAGE_COPY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW) #define PAGE_READONLY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW) #define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE) #define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x)) #define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW)) #define _PAGE_S(x) _PAGE_NORMAL(x) /* * The hardware can handle write-only mappings, but as the Alpha * architecture does byte-wide writes with a read-modify-write * sequence, it's not practical to have write-without-read privs. * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in * arch/alpha/mm/fault.c) */ /* xwr */ #define __P000 _PAGE_P(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR) #define __P001 _PAGE_P(_PAGE_FOE | _PAGE_FOW) #define __P010 _PAGE_P(_PAGE_FOE) #define __P011 _PAGE_P(_PAGE_FOE) #define __P100 _PAGE_P(_PAGE_FOW | _PAGE_FOR) #define __P101 _PAGE_P(_PAGE_FOW) #define __P110 _PAGE_P(0) #define __P111 _PAGE_P(0) #define __S000 _PAGE_S(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR) #define __S001 _PAGE_S(_PAGE_FOE | _PAGE_FOW) #define __S010 _PAGE_S(_PAGE_FOE) #define __S011 _PAGE_S(_PAGE_FOE) #define __S100 _PAGE_S(_PAGE_FOW | _PAGE_FOR) #define __S101 _PAGE_S(_PAGE_FOW) #define __S110 _PAGE_S(0) #define __S111 _PAGE_S(0) /* * pgprot_noncached() is only for infiniband pci support, and a real * implementation for RAM would be more complicated. */ #define pgprot_noncached(prot) (prot) /* * BAD_PAGETABLE is used when we need a bogus page-table, while * BAD_PAGE is used for a bogus page. * * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. */ extern pte_t __bad_page(void); extern pmd_t * __bad_pagetable(void); extern unsigned long __zero_page(void); #define BAD_PAGETABLE __bad_pagetable() #define BAD_PAGE __bad_page() #define ZERO_PAGE(vaddr) (virt_to_page(ZERO_PGE)) /* number of bits that fit into a memory pointer */ #define BITS_PER_PTR (8*sizeof(unsigned long)) /* to align the pointer to a pointer address */ #define PTR_MASK (~(sizeof(void*)-1)) /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ #define SIZEOF_PTR_LOG2 3 /* to find an entry in a page-table */ #define PAGE_PTR(address) \ ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) /* * On certain platforms whose physical address space can overlap KSEG, * namely EV6 and above, we must re-twiddle the physaddr to restore the * correct high-order bits. * * This is extremely confusing until you realize that this is actually * just working around a userspace bug. The X server was intending to * provide the physical address but instead provided the KSEG address. * Or tried to, except it's not representable. * * On Tsunami there's nothing meaningful at 0x40000000000, so this is * a safe thing to do. Come the first core logic that does put something * in this area -- memory or whathaveyou -- then this hack will have * to go away. So be prepared! */ #if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG) #error "EV6-only feature in a generic kernel" #endif #if defined(CONFIG_ALPHA_GENERIC) || \ (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG)) #define KSEG_PFN (0xc0000000000UL >> PAGE_SHIFT) #define PHYS_TWIDDLE(pfn) \ ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \ ? ((pfn) ^= KSEG_PFN) : (pfn)) #else #define PHYS_TWIDDLE(pfn) (pfn) #endif /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. */ #define page_to_pa(page) (page_to_pfn(page) << PAGE_SHIFT) #define pte_pfn(pte) (pte_val(pte) >> 32) #define pte_page(pte) pfn_to_page(pte_pfn(pte)) #define mk_pte(page, pgprot) \ ({ \ pte_t pte; \ \ pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot); \ pte; \ }) extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot) { pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; } extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep) { pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); } extern inline void pud_set(pud_t * pudp, pmd_t * pmdp) { pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); } extern inline unsigned long pmd_page_vaddr(pmd_t pmd) { return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET; } #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> 32)) #define pud_page(pud) (pfn_to_page(pud_val(pud) >> 32)) extern inline pmd_t *pud_pgtable(pud_t pgd) { return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT))); } extern inline int pte_none(pte_t pte) { return !pte_val(pte); } extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; } extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { pte_val(*ptep) = 0; } extern inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); } extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; } extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_VALID; } extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; } extern inline int pud_none(pud_t pud) { return !pud_val(pud); } extern inline int pud_bad(pud_t pud) { return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; } extern inline int pud_present(pud_t pud) { return pud_val(pud) & _PAGE_VALID; } extern inline void pud_clear(pud_t * pudp) { pud_val(*pudp) = 0; } /* * The following only work if pte_present() is true. * Undefined behaviour if not.. */ extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); } extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; } extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; } extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; } extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_FOW; return pte; } extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; } extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; } /* * The smp_rmb() in the following functions are required to order the load of * *dir (the pointer in the top level page table) with any subsequent load of * the returned pmd_t *ret (ret is data dependent on *dir). * * If this ordering is not enforced, the CPU might load an older value of * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for * more details. * * Note that we never change the mm->pgd pointer after the task is running, so * pgd_offset does not require such a barrier. */ /* Find an entry in the second-level page table.. */ extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address) { pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); smp_rmb(); /* see above */ return ret; } #define pmd_offset pmd_offset /* Find an entry in the third-level page table.. */ extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address) { pte_t *ret = (pte_t *) pmd_page_vaddr(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1)); smp_rmb(); /* see above */ return ret; } #define pte_offset_kernel pte_offset_kernel extern pgd_t swapper_pg_dir[1024]; /* * The Alpha doesn't have any external MMU info: the kernel page * tables contain all the necessary information. */ extern inline void update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep) { } /* * Non-present pages: high 24 bits are offset, next 8 bits type, * low 32 bits zero. */ extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) { pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; } #define __swp_type(x) (((x).val >> 32) & 0xff) #define __swp_offset(x) ((x).val >> 40) #define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) #define kern_addr_valid(addr) (1) #define pte_ERROR(e) \ printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) #define pmd_ERROR(e) \ printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) extern void paging_init(void); /* We have our own get_unmapped_area */ #define HAVE_ARCH_UNMAPPED_AREA #endif /* _ALPHA_PGTABLE_H */ PK ! -���% % machvec.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_MACHVEC_H #define __ALPHA_MACHVEC_H 1 #include <linux/types.h> /* * This file gets pulled in by asm/io.h from user space. We don't * want most of this escaping. */ #ifdef __KERNEL__ /* The following structure vectors all of the I/O and IRQ manipulation from the generic kernel to the hardware specific backend. */ struct task_struct; struct mm_struct; struct vm_area_struct; struct linux_hose_info; struct pci_dev; struct pci_ops; struct pci_controller; struct _alpha_agp_info; struct rtc_time; struct alpha_machine_vector { /* This "belongs" down below with the rest of the runtime variables, but it is convenient for entry.S if these two slots are at the beginning of the struct. */ unsigned long hae_cache; unsigned long *hae_register; int nr_irqs; int rtc_port; int rtc_boot_cpu_only; unsigned int max_asn; unsigned long max_isa_dma_address; unsigned long irq_probe_mask; unsigned long iack_sc; unsigned long min_io_address; unsigned long min_mem_address; unsigned long pci_dac_offset; void (*mv_pci_tbi)(struct pci_controller *hose, dma_addr_t start, dma_addr_t end); unsigned int (*mv_ioread8)(const void __iomem *); unsigned int (*mv_ioread16)(const void __iomem *); unsigned int (*mv_ioread32)(const void __iomem *); void (*mv_iowrite8)(u8, void __iomem *); void (*mv_iowrite16)(u16, void __iomem *); void (*mv_iowrite32)(u32, void __iomem *); u8 (*mv_readb)(const volatile void __iomem *); u16 (*mv_readw)(const volatile void __iomem *); u32 (*mv_readl)(const volatile void __iomem *); u64 (*mv_readq)(const volatile void __iomem *); void (*mv_writeb)(u8, volatile void __iomem *); void (*mv_writew)(u16, volatile void __iomem *); void (*mv_writel)(u32, volatile void __iomem *); void (*mv_writeq)(u64, volatile void __iomem *); void __iomem *(*mv_ioportmap)(unsigned long); void __iomem *(*mv_ioremap)(unsigned long, unsigned long); void (*mv_iounmap)(volatile void __iomem *); int (*mv_is_ioaddr)(unsigned long); int (*mv_is_mmio)(const volatile void __iomem *); void (*mv_switch_mm)(struct mm_struct *, struct mm_struct *, struct task_struct *); void (*mv_activate_mm)(struct mm_struct *, struct mm_struct *); void (*mv_flush_tlb_current)(struct mm_struct *); void (*mv_flush_tlb_current_page)(struct mm_struct * mm, struct vm_area_struct *vma, unsigned long addr); void (*update_irq_hw)(unsigned long, unsigned long, int); void (*ack_irq)(unsigned long); void (*device_interrupt)(unsigned long vector); void (*machine_check)(unsigned long vector, unsigned long la); void (*smp_callin)(void); void (*init_arch)(void); void (*init_irq)(void); void (*init_rtc)(void); void (*init_pci)(void); void (*kill_arch)(int); u8 (*pci_swizzle)(struct pci_dev *, u8 *); int (*pci_map_irq)(const struct pci_dev *, u8, u8); struct pci_ops *pci_ops; struct _alpha_agp_info *(*agp_info)(void); const char *vector_name; /* System specific parameters. */ union { struct { unsigned long gru_int_req_bits; } cia; struct { unsigned long gamma_bias; } t2; struct { unsigned int route_tab; } sio; } sys; }; extern struct alpha_machine_vector alpha_mv; #ifdef CONFIG_ALPHA_GENERIC extern int alpha_using_srm; extern int alpha_using_qemu; #else # ifdef CONFIG_ALPHA_SRM # define alpha_using_srm 1 # else # define alpha_using_srm 0 # endif # ifdef CONFIG_ALPHA_QEMU # define alpha_using_qemu 1 # else # define alpha_using_qemu 0 # endif #endif /* GENERIC */ #endif /* __KERNEL__ */ #endif /* __ALPHA_MACHVEC_H */ PK ! �6$� � agp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef AGP_H #define AGP_H 1 #include <asm/io.h> /* dummy for now */ #define map_page_into_agp(page) do { } while (0) #define unmap_page_from_agp(page) do { } while (0) #define flush_agp_cache() mb() /* GATT allocation. Returns/accepts GATT kernel virtual address. */ #define alloc_gatt_pages(order) \ ((char *)__get_free_pages(GFP_KERNEL, (order))) #define free_gatt_pages(table, order) \ free_pages((unsigned long)(table), (order)) #endif PK ! y�9I I module.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_MODULE_H #define _ALPHA_MODULE_H #include <asm-generic/module.h> struct mod_arch_specific { unsigned int gotsecindex; }; #define ARCH_SHF_SMALL SHF_ALPHA_GPREL #ifdef MODULE asm(".section .got,\"aws\",@progbits; .align 3; .previous"); #endif #endif /*_ALPHA_MODULE_H*/ PK ! ]x5 � � emergency-restart.hnu �[��� #ifndef _ASM_EMERGENCY_RESTART_H #define _ASM_EMERGENCY_RESTART_H #include <asm-generic/emergency-restart.h> #endif /* _ASM_EMERGENCY_RESTART_H */ PK ! �E��- �- core_mcpcia.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_MCPCIA__H__ #define __ALPHA_MCPCIA__H__ /* Define to experiment with fitting everything into one 128MB HAE window. One window per bus, that is. */ #define MCPCIA_ONE_HAE_WINDOW 1 #include <linux/types.h> #include <asm/compiler.h> #include <asm/mce.h> /* * MCPCIA is the internal name for a core logic chipset which provides * PCI access for the RAWHIDE family of systems. * * This file is based on: * * RAWHIDE System Programmer's Manual * 16-May-96 * Rev. 1.4 * */ /*------------------------------------------------------------------------** ** ** ** I/O procedures ** ** ** ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers ** ** inportbxt: 8 bits only ** ** inport: alias of inportw ** ** outport: alias of outportw ** ** ** ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers ** ** inmembxt: 8 bits only ** ** inmem: alias of inmemw ** ** outmem: alias of outmemw ** ** ** **------------------------------------------------------------------------*/ /* MCPCIA ADDRESS BIT DEFINITIONS * * 3333 3333 3322 2222 2222 1111 1111 11 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- * 1 000 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- * | |\| * | Byte Enable --+ | * | Transfer Length --+ * +-- IO space, not cached * * Byte Transfer * Enable Length Transfer Byte Address * adr<6:5> adr<4:3> Length Enable Adder * --------------------------------------------- * 00 00 Byte 1110 0x000 * 01 00 Byte 1101 0x020 * 10 00 Byte 1011 0x040 * 11 00 Byte 0111 0x060 * * 00 01 Word 1100 0x008 * 01 01 Word 1001 0x028 <= Not supported in this code. * 10 01 Word 0011 0x048 * * 00 10 Tribyte 1000 0x010 * 01 10 Tribyte 0001 0x030 * * 10 11 Longword 0000 0x058 * * Note that byte enables are asserted low. * */ #define MCPCIA_MAX_HOSES 4 #define MCPCIA_MID(m) ((unsigned long)(m) << 33) /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */ #define MCPCIA_HOSE2MID(h) ((h) + 4) #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */ /* * Memory spaces: */ #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m)) #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m)) #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m)) #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m)) #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m)) #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m)) #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m)) #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m)) /* * General Registers */ #define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000) #define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040) #define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080) #define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100) #define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400) #define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440) #define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480) #define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0) /* * Interrupt Control registers */ #define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500) #define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540) #define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580) #define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0) #define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600) #define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640) #define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680) #define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00) #define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40) /* * Performance Monitor registers */ #define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300) #define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340) /* * Diagnostic Registers */ #define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700) #define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0) /* * Error registers */ #define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800) #define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840) #define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880) #define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040) #define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000) #define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040) #define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080) #define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000) #define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040) #define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080) /* * PCI Address Translation Registers. */ #define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300) #define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340) #define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400) #define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440) #define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480) #define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500) #define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540) #define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580) #define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600) #define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640) #define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680) #define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700) #define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740) #define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780) /* Hack! Only words for bus 0. */ #ifndef MCPCIA_ONE_HAE_WINDOW #define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4) #endif #define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4) /* * The canonical non-remaped I/O and MEM addresses have these values * subtracted out. This is arranged so that folks manipulating ISA * devices can use their familiar numbers and have them map to bus 0. */ #define MCPCIA_IO_BIAS MCPCIA_IO(4) #define MCPCIA_MEM_BIAS MCPCIA_DENSE(4) /* Offset between ram physical addresses and pci64 DAC bus addresses. */ #define MCPCIA_DAC_OFFSET (1UL << 40) /* * Data structure for handling MCPCIA machine checks: */ struct el_MCPCIA_uncorrected_frame_mcheck { struct el_common header; struct el_common_EV5_uncorrectable_mcheck procdata; }; #ifdef __KERNEL__ #ifndef __EXTERN_INLINE #define __EXTERN_INLINE extern inline #define __IO_EXTERN_INLINE #endif /* * I/O functions: * * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164) * and EV56 (21164a) processors, can use either a sparse address mapping * scheme, or the so-called byte-word PCI address space, to get at PCI memory * and I/O. * * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE. */ /* * Memory functions. 64-bit and 32-bit accesses are done through * dense memory space, everything else through sparse space. * * For reading and writing 8 and 16 bit quantities we need to * go through one of the three sparse address mapping regions * and use the HAE_MEM CSR to provide some bits of the address. * The following few routines use only sparse address region 1 * which gives 1Gbyte of accessible space which relates exactly * to the amount of PCI memory mapping *into* system address space. * See p 6-17 of the specification but it looks something like this: * * 21164 Address: * * 3 2 1 * 9876543210987654321098765432109876543210 * 1ZZZZ0.PCI.QW.Address............BBLL * * ZZ = SBZ * BB = Byte offset * LL = Transfer length * * PCI Address: * * 3 2 1 * 10987654321098765432109876543210 * HHH....PCI.QW.Address........ 00 * * HHH = 31:29 HAE_MEM CSR * */ #define vip volatile int __force * #define vuip volatile unsigned int __force * #ifndef MCPCIA_ONE_HAE_WINDOW #define MCPCIA_FROB_MMIO \ if (__mcpcia_is_mmio(hose)) { \ set_hae(hose & 0xffffffff); \ hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \ } #else #define MCPCIA_FROB_MMIO \ if (__mcpcia_is_mmio(hose)) { \ hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \ } #endif extern inline int __mcpcia_is_mmio(unsigned long addr) { return (addr & 0x80000000UL) == 0; } __EXTERN_INLINE unsigned int mcpcia_ioread8(const void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; unsigned long result; MCPCIA_FROB_MMIO; result = *(vip) ((addr << 5) + hose + 0x00); return __kernel_extbl(result, addr & 3); } __EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; unsigned long w; MCPCIA_FROB_MMIO; w = __kernel_insbl(b, addr & 3); *(vuip) ((addr << 5) + hose + 0x00) = w; } __EXTERN_INLINE unsigned int mcpcia_ioread16(const void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; unsigned long result; MCPCIA_FROB_MMIO; result = *(vip) ((addr << 5) + hose + 0x08); return __kernel_extwl(result, addr & 3); } __EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; unsigned long w; MCPCIA_FROB_MMIO; w = __kernel_inswl(b, addr & 3); *(vuip) ((addr << 5) + hose + 0x08) = w; } __EXTERN_INLINE unsigned int mcpcia_ioread32(const void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr; if (!__mcpcia_is_mmio(addr)) addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18; return *(vuip)addr; } __EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr) { unsigned long addr = (unsigned long)xaddr; if (!__mcpcia_is_mmio(addr)) addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18; *(vuip)addr = b; } __EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr) { return (void __iomem *)(addr + MCPCIA_IO_BIAS); } __EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr, unsigned long size) { return (void __iomem *)(addr + MCPCIA_MEM_BIAS); } __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr) { return addr >= MCPCIA_SPARSE(0); } __EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; return __mcpcia_is_mmio(addr); } #undef MCPCIA_FROB_MMIO #undef vip #undef vuip #undef __IO_PREFIX #define __IO_PREFIX mcpcia #define mcpcia_trivial_rw_bw 2 #define mcpcia_trivial_rw_lq 1 #define mcpcia_trivial_io_bw 0 #define mcpcia_trivial_io_lq 0 #define mcpcia_trivial_iounmap 1 #include <asm/io_trivial.h> #ifdef __IO_EXTERN_INLINE #undef __EXTERN_INLINE #undef __IO_EXTERN_INLINE #endif #endif /* __KERNEL__ */ #endif /* __ALPHA_MCPCIA__H__ */ PK ! �MIU IU xor.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * include/asm-alpha/xor.h * * Optimized RAID-5 checksumming functions for alpha EV5 and EV6 */ extern void xor_alpha_2(unsigned long, unsigned long *, unsigned long *); extern void xor_alpha_3(unsigned long, unsigned long *, unsigned long *, unsigned long *); extern void xor_alpha_4(unsigned long, unsigned long *, unsigned long *, unsigned long *, unsigned long *); extern void xor_alpha_5(unsigned long, unsigned long *, unsigned long *, unsigned long *, unsigned long *, unsigned long *); extern void xor_alpha_prefetch_2(unsigned long, unsigned long *, unsigned long *); extern void xor_alpha_prefetch_3(unsigned long, unsigned long *, unsigned long *, unsigned long *); extern void xor_alpha_prefetch_4(unsigned long, unsigned long *, unsigned long *, unsigned long *, unsigned long *); extern void xor_alpha_prefetch_5(unsigned long, unsigned long *, unsigned long *, unsigned long *, unsigned long *, unsigned long *); asm(" \n\ .text \n\ .align 3 \n\ .ent xor_alpha_2 \n\ xor_alpha_2: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ .align 4 \n\ 2: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,8($17) \n\ ldq $3,8($18) \n\ \n\ ldq $4,16($17) \n\ ldq $5,16($18) \n\ ldq $6,24($17) \n\ ldq $7,24($18) \n\ \n\ ldq $19,32($17) \n\ ldq $20,32($18) \n\ ldq $21,40($17) \n\ ldq $22,40($18) \n\ \n\ ldq $23,48($17) \n\ ldq $24,48($18) \n\ ldq $25,56($17) \n\ xor $0,$1,$0 # 7 cycles from $1 load \n\ \n\ ldq $27,56($18) \n\ xor $2,$3,$2 \n\ stq $0,0($17) \n\ xor $4,$5,$4 \n\ \n\ stq $2,8($17) \n\ xor $6,$7,$6 \n\ stq $4,16($17) \n\ xor $19,$20,$19 \n\ \n\ stq $6,24($17) \n\ xor $21,$22,$21 \n\ stq $19,32($17) \n\ xor $23,$24,$23 \n\ \n\ stq $21,40($17) \n\ xor $25,$27,$25 \n\ stq $23,48($17) \n\ subq $16,1,$16 \n\ \n\ stq $25,56($17) \n\ addq $17,64,$17 \n\ addq $18,64,$18 \n\ bgt $16,2b \n\ \n\ ret \n\ .end xor_alpha_2 \n\ \n\ .align 3 \n\ .ent xor_alpha_3 \n\ xor_alpha_3: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ .align 4 \n\ 3: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,0($19) \n\ ldq $3,8($17) \n\ \n\ ldq $4,8($18) \n\ ldq $6,16($17) \n\ ldq $7,16($18) \n\ ldq $21,24($17) \n\ \n\ ldq $22,24($18) \n\ ldq $24,32($17) \n\ ldq $25,32($18) \n\ ldq $5,8($19) \n\ \n\ ldq $20,16($19) \n\ ldq $23,24($19) \n\ ldq $27,32($19) \n\ nop \n\ \n\ xor $0,$1,$1 # 8 cycles from $0 load \n\ xor $3,$4,$4 # 6 cycles from $4 load \n\ xor $6,$7,$7 # 6 cycles from $7 load \n\ xor $21,$22,$22 # 5 cycles from $22 load \n\ \n\ xor $1,$2,$2 # 9 cycles from $2 load \n\ xor $24,$25,$25 # 5 cycles from $25 load \n\ stq $2,0($17) \n\ xor $4,$5,$5 # 6 cycles from $5 load \n\ \n\ stq $5,8($17) \n\ xor $7,$20,$20 # 7 cycles from $20 load \n\ stq $20,16($17) \n\ xor $22,$23,$23 # 7 cycles from $23 load \n\ \n\ stq $23,24($17) \n\ xor $25,$27,$27 # 7 cycles from $27 load \n\ stq $27,32($17) \n\ nop \n\ \n\ ldq $0,40($17) \n\ ldq $1,40($18) \n\ ldq $3,48($17) \n\ ldq $4,48($18) \n\ \n\ ldq $6,56($17) \n\ ldq $7,56($18) \n\ ldq $2,40($19) \n\ ldq $5,48($19) \n\ \n\ ldq $20,56($19) \n\ xor $0,$1,$1 # 4 cycles from $1 load \n\ xor $3,$4,$4 # 5 cycles from $4 load \n\ xor $6,$7,$7 # 5 cycles from $7 load \n\ \n\ xor $1,$2,$2 # 4 cycles from $2 load \n\ xor $4,$5,$5 # 5 cycles from $5 load \n\ stq $2,40($17) \n\ xor $7,$20,$20 # 4 cycles from $20 load \n\ \n\ stq $5,48($17) \n\ subq $16,1,$16 \n\ stq $20,56($17) \n\ addq $19,64,$19 \n\ \n\ addq $18,64,$18 \n\ addq $17,64,$17 \n\ bgt $16,3b \n\ ret \n\ .end xor_alpha_3 \n\ \n\ .align 3 \n\ .ent xor_alpha_4 \n\ xor_alpha_4: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ .align 4 \n\ 4: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,0($19) \n\ ldq $3,0($20) \n\ \n\ ldq $4,8($17) \n\ ldq $5,8($18) \n\ ldq $6,8($19) \n\ ldq $7,8($20) \n\ \n\ ldq $21,16($17) \n\ ldq $22,16($18) \n\ ldq $23,16($19) \n\ ldq $24,16($20) \n\ \n\ ldq $25,24($17) \n\ xor $0,$1,$1 # 6 cycles from $1 load \n\ ldq $27,24($18) \n\ xor $2,$3,$3 # 6 cycles from $3 load \n\ \n\ ldq $0,24($19) \n\ xor $1,$3,$3 \n\ ldq $1,24($20) \n\ xor $4,$5,$5 # 7 cycles from $5 load \n\ \n\ stq $3,0($17) \n\ xor $6,$7,$7 \n\ xor $21,$22,$22 # 7 cycles from $22 load \n\ xor $5,$7,$7 \n\ \n\ stq $7,8($17) \n\ xor $23,$24,$24 # 7 cycles from $24 load \n\ ldq $2,32($17) \n\ xor $22,$24,$24 \n\ \n\ ldq $3,32($18) \n\ ldq $4,32($19) \n\ ldq $5,32($20) \n\ xor $25,$27,$27 # 8 cycles from $27 load \n\ \n\ ldq $6,40($17) \n\ ldq $7,40($18) \n\ ldq $21,40($19) \n\ ldq $22,40($20) \n\ \n\ stq $24,16($17) \n\ xor $0,$1,$1 # 9 cycles from $1 load \n\ xor $2,$3,$3 # 5 cycles from $3 load \n\ xor $27,$1,$1 \n\ \n\ stq $1,24($17) \n\ xor $4,$5,$5 # 5 cycles from $5 load \n\ ldq $23,48($17) \n\ ldq $24,48($18) \n\ \n\ ldq $25,48($19) \n\ xor $3,$5,$5 \n\ ldq $27,48($20) \n\ ldq $0,56($17) \n\ \n\ ldq $1,56($18) \n\ ldq $2,56($19) \n\ xor $6,$7,$7 # 8 cycles from $6 load \n\ ldq $3,56($20) \n\ \n\ stq $5,32($17) \n\ xor $21,$22,$22 # 8 cycles from $22 load \n\ xor $7,$22,$22 \n\ xor $23,$24,$24 # 5 cycles from $24 load \n\ \n\ stq $22,40($17) \n\ xor $25,$27,$27 # 5 cycles from $27 load \n\ xor $24,$27,$27 \n\ xor $0,$1,$1 # 5 cycles from $1 load \n\ \n\ stq $27,48($17) \n\ xor $2,$3,$3 # 4 cycles from $3 load \n\ xor $1,$3,$3 \n\ subq $16,1,$16 \n\ \n\ stq $3,56($17) \n\ addq $20,64,$20 \n\ addq $19,64,$19 \n\ addq $18,64,$18 \n\ \n\ addq $17,64,$17 \n\ bgt $16,4b \n\ ret \n\ .end xor_alpha_4 \n\ \n\ .align 3 \n\ .ent xor_alpha_5 \n\ xor_alpha_5: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ .align 4 \n\ 5: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,0($19) \n\ ldq $3,0($20) \n\ \n\ ldq $4,0($21) \n\ ldq $5,8($17) \n\ ldq $6,8($18) \n\ ldq $7,8($19) \n\ \n\ ldq $22,8($20) \n\ ldq $23,8($21) \n\ ldq $24,16($17) \n\ ldq $25,16($18) \n\ \n\ ldq $27,16($19) \n\ xor $0,$1,$1 # 6 cycles from $1 load \n\ ldq $28,16($20) \n\ xor $2,$3,$3 # 6 cycles from $3 load \n\ \n\ ldq $0,16($21) \n\ xor $1,$3,$3 \n\ ldq $1,24($17) \n\ xor $3,$4,$4 # 7 cycles from $4 load \n\ \n\ stq $4,0($17) \n\ xor $5,$6,$6 # 7 cycles from $6 load \n\ xor $7,$22,$22 # 7 cycles from $22 load \n\ xor $6,$23,$23 # 7 cycles from $23 load \n\ \n\ ldq $2,24($18) \n\ xor $22,$23,$23 \n\ ldq $3,24($19) \n\ xor $24,$25,$25 # 8 cycles from $25 load \n\ \n\ stq $23,8($17) \n\ xor $25,$27,$27 # 8 cycles from $27 load \n\ ldq $4,24($20) \n\ xor $28,$0,$0 # 7 cycles from $0 load \n\ \n\ ldq $5,24($21) \n\ xor $27,$0,$0 \n\ ldq $6,32($17) \n\ ldq $7,32($18) \n\ \n\ stq $0,16($17) \n\ xor $1,$2,$2 # 6 cycles from $2 load \n\ ldq $22,32($19) \n\ xor $3,$4,$4 # 4 cycles from $4 load \n\ \n\ ldq $23,32($20) \n\ xor $2,$4,$4 \n\ ldq $24,32($21) \n\ ldq $25,40($17) \n\ \n\ ldq $27,40($18) \n\ ldq $28,40($19) \n\ ldq $0,40($20) \n\ xor $4,$5,$5 # 7 cycles from $5 load \n\ \n\ stq $5,24($17) \n\ xor $6,$7,$7 # 7 cycles from $7 load \n\ ldq $1,40($21) \n\ ldq $2,48($17) \n\ \n\ ldq $3,48($18) \n\ xor $7,$22,$22 # 7 cycles from $22 load \n\ ldq $4,48($19) \n\ xor $23,$24,$24 # 6 cycles from $24 load \n\ \n\ ldq $5,48($20) \n\ xor $22,$24,$24 \n\ ldq $6,48($21) \n\ xor $25,$27,$27 # 7 cycles from $27 load \n\ \n\ stq $24,32($17) \n\ xor $27,$28,$28 # 8 cycles from $28 load \n\ ldq $7,56($17) \n\ xor $0,$1,$1 # 6 cycles from $1 load \n\ \n\ ldq $22,56($18) \n\ ldq $23,56($19) \n\ ldq $24,56($20) \n\ ldq $25,56($21) \n\ \n\ xor $28,$1,$1 \n\ xor $2,$3,$3 # 9 cycles from $3 load \n\ xor $3,$4,$4 # 9 cycles from $4 load \n\ xor $5,$6,$6 # 8 cycles from $6 load \n\ \n\ stq $1,40($17) \n\ xor $4,$6,$6 \n\ xor $7,$22,$22 # 7 cycles from $22 load \n\ xor $23,$24,$24 # 6 cycles from $24 load \n\ \n\ stq $6,48($17) \n\ xor $22,$24,$24 \n\ subq $16,1,$16 \n\ xor $24,$25,$25 # 8 cycles from $25 load \n\ \n\ stq $25,56($17) \n\ addq $21,64,$21 \n\ addq $20,64,$20 \n\ addq $19,64,$19 \n\ \n\ addq $18,64,$18 \n\ addq $17,64,$17 \n\ bgt $16,5b \n\ ret \n\ .end xor_alpha_5 \n\ \n\ .align 3 \n\ .ent xor_alpha_prefetch_2 \n\ xor_alpha_prefetch_2: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ \n\ ldq $31, 0($17) \n\ ldq $31, 0($18) \n\ \n\ ldq $31, 64($17) \n\ ldq $31, 64($18) \n\ \n\ ldq $31, 128($17) \n\ ldq $31, 128($18) \n\ \n\ ldq $31, 192($17) \n\ ldq $31, 192($18) \n\ .align 4 \n\ 2: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,8($17) \n\ ldq $3,8($18) \n\ \n\ ldq $4,16($17) \n\ ldq $5,16($18) \n\ ldq $6,24($17) \n\ ldq $7,24($18) \n\ \n\ ldq $19,32($17) \n\ ldq $20,32($18) \n\ ldq $21,40($17) \n\ ldq $22,40($18) \n\ \n\ ldq $23,48($17) \n\ ldq $24,48($18) \n\ ldq $25,56($17) \n\ ldq $27,56($18) \n\ \n\ ldq $31,256($17) \n\ xor $0,$1,$0 # 8 cycles from $1 load \n\ ldq $31,256($18) \n\ xor $2,$3,$2 \n\ \n\ stq $0,0($17) \n\ xor $4,$5,$4 \n\ stq $2,8($17) \n\ xor $6,$7,$6 \n\ \n\ stq $4,16($17) \n\ xor $19,$20,$19 \n\ stq $6,24($17) \n\ xor $21,$22,$21 \n\ \n\ stq $19,32($17) \n\ xor $23,$24,$23 \n\ stq $21,40($17) \n\ xor $25,$27,$25 \n\ \n\ stq $23,48($17) \n\ subq $16,1,$16 \n\ stq $25,56($17) \n\ addq $17,64,$17 \n\ \n\ addq $18,64,$18 \n\ bgt $16,2b \n\ ret \n\ .end xor_alpha_prefetch_2 \n\ \n\ .align 3 \n\ .ent xor_alpha_prefetch_3 \n\ xor_alpha_prefetch_3: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ \n\ ldq $31, 0($17) \n\ ldq $31, 0($18) \n\ ldq $31, 0($19) \n\ \n\ ldq $31, 64($17) \n\ ldq $31, 64($18) \n\ ldq $31, 64($19) \n\ \n\ ldq $31, 128($17) \n\ ldq $31, 128($18) \n\ ldq $31, 128($19) \n\ \n\ ldq $31, 192($17) \n\ ldq $31, 192($18) \n\ ldq $31, 192($19) \n\ .align 4 \n\ 3: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,0($19) \n\ ldq $3,8($17) \n\ \n\ ldq $4,8($18) \n\ ldq $6,16($17) \n\ ldq $7,16($18) \n\ ldq $21,24($17) \n\ \n\ ldq $22,24($18) \n\ ldq $24,32($17) \n\ ldq $25,32($18) \n\ ldq $5,8($19) \n\ \n\ ldq $20,16($19) \n\ ldq $23,24($19) \n\ ldq $27,32($19) \n\ nop \n\ \n\ xor $0,$1,$1 # 8 cycles from $0 load \n\ xor $3,$4,$4 # 7 cycles from $4 load \n\ xor $6,$7,$7 # 6 cycles from $7 load \n\ xor $21,$22,$22 # 5 cycles from $22 load \n\ \n\ xor $1,$2,$2 # 9 cycles from $2 load \n\ xor $24,$25,$25 # 5 cycles from $25 load \n\ stq $2,0($17) \n\ xor $4,$5,$5 # 6 cycles from $5 load \n\ \n\ stq $5,8($17) \n\ xor $7,$20,$20 # 7 cycles from $20 load \n\ stq $20,16($17) \n\ xor $22,$23,$23 # 7 cycles from $23 load \n\ \n\ stq $23,24($17) \n\ xor $25,$27,$27 # 7 cycles from $27 load \n\ stq $27,32($17) \n\ nop \n\ \n\ ldq $0,40($17) \n\ ldq $1,40($18) \n\ ldq $3,48($17) \n\ ldq $4,48($18) \n\ \n\ ldq $6,56($17) \n\ ldq $7,56($18) \n\ ldq $2,40($19) \n\ ldq $5,48($19) \n\ \n\ ldq $20,56($19) \n\ ldq $31,256($17) \n\ ldq $31,256($18) \n\ ldq $31,256($19) \n\ \n\ xor $0,$1,$1 # 6 cycles from $1 load \n\ xor $3,$4,$4 # 5 cycles from $4 load \n\ xor $6,$7,$7 # 5 cycles from $7 load \n\ xor $1,$2,$2 # 4 cycles from $2 load \n\ \n\ xor $4,$5,$5 # 5 cycles from $5 load \n\ xor $7,$20,$20 # 4 cycles from $20 load \n\ stq $2,40($17) \n\ subq $16,1,$16 \n\ \n\ stq $5,48($17) \n\ addq $19,64,$19 \n\ stq $20,56($17) \n\ addq $18,64,$18 \n\ \n\ addq $17,64,$17 \n\ bgt $16,3b \n\ ret \n\ .end xor_alpha_prefetch_3 \n\ \n\ .align 3 \n\ .ent xor_alpha_prefetch_4 \n\ xor_alpha_prefetch_4: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ \n\ ldq $31, 0($17) \n\ ldq $31, 0($18) \n\ ldq $31, 0($19) \n\ ldq $31, 0($20) \n\ \n\ ldq $31, 64($17) \n\ ldq $31, 64($18) \n\ ldq $31, 64($19) \n\ ldq $31, 64($20) \n\ \n\ ldq $31, 128($17) \n\ ldq $31, 128($18) \n\ ldq $31, 128($19) \n\ ldq $31, 128($20) \n\ \n\ ldq $31, 192($17) \n\ ldq $31, 192($18) \n\ ldq $31, 192($19) \n\ ldq $31, 192($20) \n\ .align 4 \n\ 4: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,0($19) \n\ ldq $3,0($20) \n\ \n\ ldq $4,8($17) \n\ ldq $5,8($18) \n\ ldq $6,8($19) \n\ ldq $7,8($20) \n\ \n\ ldq $21,16($17) \n\ ldq $22,16($18) \n\ ldq $23,16($19) \n\ ldq $24,16($20) \n\ \n\ ldq $25,24($17) \n\ xor $0,$1,$1 # 6 cycles from $1 load \n\ ldq $27,24($18) \n\ xor $2,$3,$3 # 6 cycles from $3 load \n\ \n\ ldq $0,24($19) \n\ xor $1,$3,$3 \n\ ldq $1,24($20) \n\ xor $4,$5,$5 # 7 cycles from $5 load \n\ \n\ stq $3,0($17) \n\ xor $6,$7,$7 \n\ xor $21,$22,$22 # 7 cycles from $22 load \n\ xor $5,$7,$7 \n\ \n\ stq $7,8($17) \n\ xor $23,$24,$24 # 7 cycles from $24 load \n\ ldq $2,32($17) \n\ xor $22,$24,$24 \n\ \n\ ldq $3,32($18) \n\ ldq $4,32($19) \n\ ldq $5,32($20) \n\ xor $25,$27,$27 # 8 cycles from $27 load \n\ \n\ ldq $6,40($17) \n\ ldq $7,40($18) \n\ ldq $21,40($19) \n\ ldq $22,40($20) \n\ \n\ stq $24,16($17) \n\ xor $0,$1,$1 # 9 cycles from $1 load \n\ xor $2,$3,$3 # 5 cycles from $3 load \n\ xor $27,$1,$1 \n\ \n\ stq $1,24($17) \n\ xor $4,$5,$5 # 5 cycles from $5 load \n\ ldq $23,48($17) \n\ xor $3,$5,$5 \n\ \n\ ldq $24,48($18) \n\ ldq $25,48($19) \n\ ldq $27,48($20) \n\ ldq $0,56($17) \n\ \n\ ldq $1,56($18) \n\ ldq $2,56($19) \n\ ldq $3,56($20) \n\ xor $6,$7,$7 # 8 cycles from $6 load \n\ \n\ ldq $31,256($17) \n\ xor $21,$22,$22 # 8 cycles from $22 load \n\ ldq $31,256($18) \n\ xor $7,$22,$22 \n\ \n\ ldq $31,256($19) \n\ xor $23,$24,$24 # 6 cycles from $24 load \n\ ldq $31,256($20) \n\ xor $25,$27,$27 # 6 cycles from $27 load \n\ \n\ stq $5,32($17) \n\ xor $24,$27,$27 \n\ xor $0,$1,$1 # 7 cycles from $1 load \n\ xor $2,$3,$3 # 6 cycles from $3 load \n\ \n\ stq $22,40($17) \n\ xor $1,$3,$3 \n\ stq $27,48($17) \n\ subq $16,1,$16 \n\ \n\ stq $3,56($17) \n\ addq $20,64,$20 \n\ addq $19,64,$19 \n\ addq $18,64,$18 \n\ \n\ addq $17,64,$17 \n\ bgt $16,4b \n\ ret \n\ .end xor_alpha_prefetch_4 \n\ \n\ .align 3 \n\ .ent xor_alpha_prefetch_5 \n\ xor_alpha_prefetch_5: \n\ .prologue 0 \n\ srl $16, 6, $16 \n\ \n\ ldq $31, 0($17) \n\ ldq $31, 0($18) \n\ ldq $31, 0($19) \n\ ldq $31, 0($20) \n\ ldq $31, 0($21) \n\ \n\ ldq $31, 64($17) \n\ ldq $31, 64($18) \n\ ldq $31, 64($19) \n\ ldq $31, 64($20) \n\ ldq $31, 64($21) \n\ \n\ ldq $31, 128($17) \n\ ldq $31, 128($18) \n\ ldq $31, 128($19) \n\ ldq $31, 128($20) \n\ ldq $31, 128($21) \n\ \n\ ldq $31, 192($17) \n\ ldq $31, 192($18) \n\ ldq $31, 192($19) \n\ ldq $31, 192($20) \n\ ldq $31, 192($21) \n\ .align 4 \n\ 5: \n\ ldq $0,0($17) \n\ ldq $1,0($18) \n\ ldq $2,0($19) \n\ ldq $3,0($20) \n\ \n\ ldq $4,0($21) \n\ ldq $5,8($17) \n\ ldq $6,8($18) \n\ ldq $7,8($19) \n\ \n\ ldq $22,8($20) \n\ ldq $23,8($21) \n\ ldq $24,16($17) \n\ ldq $25,16($18) \n\ \n\ ldq $27,16($19) \n\ xor $0,$1,$1 # 6 cycles from $1 load \n\ ldq $28,16($20) \n\ xor $2,$3,$3 # 6 cycles from $3 load \n\ \n\ ldq $0,16($21) \n\ xor $1,$3,$3 \n\ ldq $1,24($17) \n\ xor $3,$4,$4 # 7 cycles from $4 load \n\ \n\ stq $4,0($17) \n\ xor $5,$6,$6 # 7 cycles from $6 load \n\ xor $7,$22,$22 # 7 cycles from $22 load \n\ xor $6,$23,$23 # 7 cycles from $23 load \n\ \n\ ldq $2,24($18) \n\ xor $22,$23,$23 \n\ ldq $3,24($19) \n\ xor $24,$25,$25 # 8 cycles from $25 load \n\ \n\ stq $23,8($17) \n\ xor $25,$27,$27 # 8 cycles from $27 load \n\ ldq $4,24($20) \n\ xor $28,$0,$0 # 7 cycles from $0 load \n\ \n\ ldq $5,24($21) \n\ xor $27,$0,$0 \n\ ldq $6,32($17) \n\ ldq $7,32($18) \n\ \n\ stq $0,16($17) \n\ xor $1,$2,$2 # 6 cycles from $2 load \n\ ldq $22,32($19) \n\ xor $3,$4,$4 # 4 cycles from $4 load \n\ \n\ ldq $23,32($20) \n\ xor $2,$4,$4 \n\ ldq $24,32($21) \n\ ldq $25,40($17) \n\ \n\ ldq $27,40($18) \n\ ldq $28,40($19) \n\ ldq $0,40($20) \n\ xor $4,$5,$5 # 7 cycles from $5 load \n\ \n\ stq $5,24($17) \n\ xor $6,$7,$7 # 7 cycles from $7 load \n\ ldq $1,40($21) \n\ ldq $2,48($17) \n\ \n\ ldq $3,48($18) \n\ xor $7,$22,$22 # 7 cycles from $22 load \n\ ldq $4,48($19) \n\ xor $23,$24,$24 # 6 cycles from $24 load \n\ \n\ ldq $5,48($20) \n\ xor $22,$24,$24 \n\ ldq $6,48($21) \n\ xor $25,$27,$27 # 7 cycles from $27 load \n\ \n\ stq $24,32($17) \n\ xor $27,$28,$28 # 8 cycles from $28 load \n\ ldq $7,56($17) \n\ xor $0,$1,$1 # 6 cycles from $1 load \n\ \n\ ldq $22,56($18) \n\ ldq $23,56($19) \n\ ldq $24,56($20) \n\ ldq $25,56($21) \n\ \n\ ldq $31,256($17) \n\ xor $28,$1,$1 \n\ ldq $31,256($18) \n\ xor $2,$3,$3 # 9 cycles from $3 load \n\ \n\ ldq $31,256($19) \n\ xor $3,$4,$4 # 9 cycles from $4 load \n\ ldq $31,256($20) \n\ xor $5,$6,$6 # 8 cycles from $6 load \n\ \n\ stq $1,40($17) \n\ xor $4,$6,$6 \n\ xor $7,$22,$22 # 7 cycles from $22 load \n\ xor $23,$24,$24 # 6 cycles from $24 load \n\ \n\ stq $6,48($17) \n\ xor $22,$24,$24 \n\ ldq $31,256($21) \n\ xor $24,$25,$25 # 8 cycles from $25 load \n\ \n\ stq $25,56($17) \n\ subq $16,1,$16 \n\ addq $21,64,$21 \n\ addq $20,64,$20 \n\ \n\ addq $19,64,$19 \n\ addq $18,64,$18 \n\ addq $17,64,$17 \n\ bgt $16,5b \n\ \n\ ret \n\ .end xor_alpha_prefetch_5 \n\ "); static struct xor_block_template xor_block_alpha = { .name = "alpha", .do_2 = xor_alpha_2, .do_3 = xor_alpha_3, .do_4 = xor_alpha_4, .do_5 = xor_alpha_5, }; static struct xor_block_template xor_block_alpha_prefetch = { .name = "alpha prefetch", .do_2 = xor_alpha_prefetch_2, .do_3 = xor_alpha_prefetch_3, .do_4 = xor_alpha_prefetch_4, .do_5 = xor_alpha_prefetch_5, }; /* For grins, also test the generic routines. */ #include <asm-generic/xor.h> #undef XOR_TRY_TEMPLATES #define XOR_TRY_TEMPLATES \ do { \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_32regs); \ xor_speed(&xor_block_alpha); \ xor_speed(&xor_block_alpha_prefetch); \ } while (0) /* Force the use of alpha_prefetch if EV6, as it is significantly faster in the cold cache case. */ #define XOR_SELECT_TEMPLATE(FASTEST) \ (implver() == IMPLVER_EV6 ? &xor_block_alpha_prefetch : FASTEST) PK ! 8f�; ; timex.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * linux/include/asm-alpha/timex.h * * ALPHA architecture timex specifications */ #ifndef _ASMALPHA_TIMEX_H #define _ASMALPHA_TIMEX_H /* With only one or two oddballs, we use the RTC as the ticker, selecting the 32.768kHz reference clock, which nicely divides down to our HZ. */ #define CLOCK_TICK_RATE 32768 /* * Standard way to access the cycle counter. * Currently only used on SMP for scheduling. * * Only the low 32 bits are available as a continuously counting entity. * But this only means we'll force a reschedule every 8 seconds or so, * which isn't an evil thing. */ typedef unsigned int cycles_t; static inline cycles_t get_cycles (void) { cycles_t ret; __asm__ __volatile__ ("rpcc %0" : "=r"(ret)); return ret; } #define get_cycles get_cycles #endif PK ! ,S�V topology.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_ALPHA_TOPOLOGY_H #define _ASM_ALPHA_TOPOLOGY_H #include <linux/smp.h> #include <linux/threads.h> #include <linux/numa.h> #include <asm/machvec.h> # include <asm-generic/topology.h> #endif /* _ASM_ALPHA_TOPOLOGY_H */ PK ! �ׂO# O# bitops.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_BITOPS_H #define _ALPHA_BITOPS_H #ifndef _LINUX_BITOPS_H #error only <linux/bitops.h> can be included directly #endif #include <asm/compiler.h> #include <asm/barrier.h> /* * Copyright 1994, Linus Torvalds. */ /* * These have to be done with inline assembly: that way the bit-setting * is guaranteed to be atomic. All bit operations return 0 if the bit * was cleared before the operation and != 0 if it was not. * * To get proper branch prediction for the main line, we must branch * forward to code at the end of this object's .text section, then * branch back to restart the operation. * * bit 0 is the LSB of addr; bit 64 is the LSB of (addr+1). */ static inline void set_bit(unsigned long nr, volatile void * addr) { unsigned long temp; int *m = ((int *) addr) + (nr >> 5); __asm__ __volatile__( "1: ldl_l %0,%3\n" " bis %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (*m) :"Ir" (1UL << (nr & 31)), "m" (*m)); } /* * WARNING: non atomic version. */ static inline void __set_bit(unsigned long nr, volatile void * addr) { int *m = ((int *) addr) + (nr >> 5); *m |= 1 << (nr & 31); } static inline void clear_bit(unsigned long nr, volatile void * addr) { unsigned long temp; int *m = ((int *) addr) + (nr >> 5); __asm__ __volatile__( "1: ldl_l %0,%3\n" " bic %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (*m) :"Ir" (1UL << (nr & 31)), "m" (*m)); } static inline void clear_bit_unlock(unsigned long nr, volatile void * addr) { smp_mb(); clear_bit(nr, addr); } /* * WARNING: non atomic version. */ static __inline__ void __clear_bit(unsigned long nr, volatile void * addr) { int *m = ((int *) addr) + (nr >> 5); *m &= ~(1 << (nr & 31)); } static inline void __clear_bit_unlock(unsigned long nr, volatile void * addr) { smp_mb(); __clear_bit(nr, addr); } static inline void change_bit(unsigned long nr, volatile void * addr) { unsigned long temp; int *m = ((int *) addr) + (nr >> 5); __asm__ __volatile__( "1: ldl_l %0,%3\n" " xor %0,%2,%0\n" " stl_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (*m) :"Ir" (1UL << (nr & 31)), "m" (*m)); } /* * WARNING: non atomic version. */ static __inline__ void __change_bit(unsigned long nr, volatile void * addr) { int *m = ((int *) addr) + (nr >> 5); *m ^= 1 << (nr & 31); } static inline int test_and_set_bit(unsigned long nr, volatile void *addr) { unsigned long oldbit; unsigned long temp; int *m = ((int *) addr) + (nr >> 5); __asm__ __volatile__( #ifdef CONFIG_SMP " mb\n" #endif "1: ldl_l %0,%4\n" " and %0,%3,%2\n" " bne %2,2f\n" " xor %0,%3,%0\n" " stl_c %0,%1\n" " beq %0,3f\n" "2:\n" #ifdef CONFIG_SMP " mb\n" #endif ".subsection 2\n" "3: br 1b\n" ".previous" :"=&r" (temp), "=m" (*m), "=&r" (oldbit) :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory"); return oldbit != 0; } static inline int test_and_set_bit_lock(unsigned long nr, volatile void *addr) { unsigned long oldbit; unsigned long temp; int *m = ((int *) addr) + (nr >> 5); __asm__ __volatile__( "1: ldl_l %0,%4\n" " and %0,%3,%2\n" " bne %2,2f\n" " xor %0,%3,%0\n" " stl_c %0,%1\n" " beq %0,3f\n" "2:\n" #ifdef CONFIG_SMP " mb\n" #endif ".subsection 2\n" "3: br 1b\n" ".previous" :"=&r" (temp), "=m" (*m), "=&r" (oldbit) :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory"); return oldbit != 0; } /* * WARNING: non atomic version. */ static inline int __test_and_set_bit(unsigned long nr, volatile void * addr) { unsigned long mask = 1 << (nr & 0x1f); int *m = ((int *) addr) + (nr >> 5); int old = *m; *m = old | mask; return (old & mask) != 0; } static inline int test_and_clear_bit(unsigned long nr, volatile void * addr) { unsigned long oldbit; unsigned long temp; int *m = ((int *) addr) + (nr >> 5); __asm__ __volatile__( #ifdef CONFIG_SMP " mb\n" #endif "1: ldl_l %0,%4\n" " and %0,%3,%2\n" " beq %2,2f\n" " xor %0,%3,%0\n" " stl_c %0,%1\n" " beq %0,3f\n" "2:\n" #ifdef CONFIG_SMP " mb\n" #endif ".subsection 2\n" "3: br 1b\n" ".previous" :"=&r" (temp), "=m" (*m), "=&r" (oldbit) :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory"); return oldbit != 0; } /* * WARNING: non atomic version. */ static inline int __test_and_clear_bit(unsigned long nr, volatile void * addr) { unsigned long mask = 1 << (nr & 0x1f); int *m = ((int *) addr) + (nr >> 5); int old = *m; *m = old & ~mask; return (old & mask) != 0; } static inline int test_and_change_bit(unsigned long nr, volatile void * addr) { unsigned long oldbit; unsigned long temp; int *m = ((int *) addr) + (nr >> 5); __asm__ __volatile__( #ifdef CONFIG_SMP " mb\n" #endif "1: ldl_l %0,%4\n" " and %0,%3,%2\n" " xor %0,%3,%0\n" " stl_c %0,%1\n" " beq %0,3f\n" #ifdef CONFIG_SMP " mb\n" #endif ".subsection 2\n" "3: br 1b\n" ".previous" :"=&r" (temp), "=m" (*m), "=&r" (oldbit) :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory"); return oldbit != 0; } /* * WARNING: non atomic version. */ static __inline__ int __test_and_change_bit(unsigned long nr, volatile void * addr) { unsigned long mask = 1 << (nr & 0x1f); int *m = ((int *) addr) + (nr >> 5); int old = *m; *m = old ^ mask; return (old & mask) != 0; } static inline int test_bit(int nr, const volatile void * addr) { return (1UL & (((const int *) addr)[nr >> 5] >> (nr & 31))) != 0UL; } /* * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. * * Do a binary search on the bits. Due to the nature of large * constants on the alpha, it is worthwhile to split the search. */ static inline unsigned long ffz_b(unsigned long x) { unsigned long sum, x1, x2, x4; x = ~x & -~x; /* set first 0 bit, clear others */ x1 = x & 0xAA; x2 = x & 0xCC; x4 = x & 0xF0; sum = x2 ? 2 : 0; sum += (x4 != 0) * 4; sum += (x1 != 0); return sum; } static inline unsigned long ffz(unsigned long word) { #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67) /* Whee. EV67 can calculate it directly. */ return __kernel_cttz(~word); #else unsigned long bits, qofs, bofs; bits = __kernel_cmpbge(word, ~0UL); qofs = ffz_b(bits); bits = __kernel_extbl(word, qofs); bofs = ffz_b(bits); return qofs*8 + bofs; #endif } /* * __ffs = Find First set bit in word. Undefined if no set bit exists. */ static inline unsigned long __ffs(unsigned long word) { #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67) /* Whee. EV67 can calculate it directly. */ return __kernel_cttz(word); #else unsigned long bits, qofs, bofs; bits = __kernel_cmpbge(0, word); qofs = ffz_b(bits); bits = __kernel_extbl(word, qofs); bofs = ffz_b(~bits); return qofs*8 + bofs; #endif } #ifdef __KERNEL__ /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above __ffs. */ static inline int ffs(int word) { int result = __ffs(word) + 1; return word ? result : 0; } /* * fls: find last bit set. */ #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67) static inline int fls64(unsigned long word) { return 64 - __kernel_ctlz(word); } #else extern const unsigned char __flsm1_tab[256]; static inline int fls64(unsigned long x) { unsigned long t, a, r; t = __kernel_cmpbge (x, 0x0101010101010101UL); a = __flsm1_tab[t]; t = __kernel_extbl (x, a); r = a*8 + __flsm1_tab[t] + (x != 0); return r; } #endif static inline unsigned long __fls(unsigned long x) { return fls64(x) - 1; } static inline int fls(unsigned int x) { return fls64(x); } /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word */ #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67) /* Whee. EV67 can calculate it directly. */ static inline unsigned long __arch_hweight64(unsigned long w) { return __kernel_ctpop(w); } static inline unsigned int __arch_hweight32(unsigned int w) { return __arch_hweight64(w); } static inline unsigned int __arch_hweight16(unsigned int w) { return __arch_hweight64(w & 0xffff); } static inline unsigned int __arch_hweight8(unsigned int w) { return __arch_hweight64(w & 0xff); } #else #include <asm-generic/bitops/arch_hweight.h> #endif #include <asm-generic/bitops/const_hweight.h> #endif /* __KERNEL__ */ #include <asm-generic/bitops/find.h> #ifdef __KERNEL__ /* * Every architecture must define this function. It's the fastest * way of searching a 100-bit bitmap. It's guaranteed that at least * one of the 100 bits is cleared. */ static inline unsigned long sched_find_first_bit(const unsigned long b[2]) { unsigned long b0, b1, ofs, tmp; b0 = b[0]; b1 = b[1]; ofs = (b0 ? 0 : 64); tmp = (b0 ? b0 : b1); return __ffs(tmp) + ofs; } #include <asm-generic/bitops/le.h> #include <asm-generic/bitops/ext2-atomic-setbit.h> #endif /* __KERNEL__ */ #endif /* _ALPHA_BITOPS_H */ PK ! 'P�1; ; irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_IRQ_H #define _ALPHA_IRQ_H /* * linux/include/alpha/irq.h * * (C) 1994 Linus Torvalds */ #include <linux/linkage.h> #if defined(CONFIG_ALPHA_GENERIC) /* Here NR_IRQS is not exact, but rather an upper bound. This is used many places throughout the kernel to size static arrays. That's ok, we'll use alpha_mv.nr_irqs when we want the real thing. */ /* When LEGACY_START_ADDRESS is selected, we leave out: TITAN WILDFIRE MARVEL This helps keep the kernel object size reasonable for the majority of machines. */ # if defined(CONFIG_ALPHA_LEGACY_START_ADDRESS) # define NR_IRQS (128) /* max is RAWHIDE/TAKARA */ # else # define NR_IRQS (32768 + 16) /* marvel - 32 pids */ # endif #elif defined(CONFIG_ALPHA_CABRIOLET) || \ defined(CONFIG_ALPHA_EB66P) || \ defined(CONFIG_ALPHA_EB164) || \ defined(CONFIG_ALPHA_PC164) || \ defined(CONFIG_ALPHA_LX164) # define NR_IRQS 35 #elif defined(CONFIG_ALPHA_EB66) || \ defined(CONFIG_ALPHA_EB64P) || \ defined(CONFIG_ALPHA_MIKASA) # define NR_IRQS 32 #elif defined(CONFIG_ALPHA_ALCOR) || \ defined(CONFIG_ALPHA_MIATA) || \ defined(CONFIG_ALPHA_RUFFIAN) || \ defined(CONFIG_ALPHA_RX164) || \ defined(CONFIG_ALPHA_NORITAKE) # define NR_IRQS 48 #elif defined(CONFIG_ALPHA_SABLE) || \ defined(CONFIG_ALPHA_SX164) # define NR_IRQS 40 #elif defined(CONFIG_ALPHA_DP264) || \ defined(CONFIG_ALPHA_LYNX) || \ defined(CONFIG_ALPHA_SHARK) # define NR_IRQS 64 #elif defined(CONFIG_ALPHA_TITAN) #define NR_IRQS 80 #elif defined(CONFIG_ALPHA_RAWHIDE) || \ defined(CONFIG_ALPHA_TAKARA) || \ defined(CONFIG_ALPHA_EIGER) # define NR_IRQS 128 #elif defined(CONFIG_ALPHA_WILDFIRE) # define NR_IRQS 2048 /* enuff for 8 QBBs */ #elif defined(CONFIG_ALPHA_MARVEL) # define NR_IRQS (32768 + 16) /* marvel - 32 pids*/ #else /* everyone else */ # define NR_IRQS 16 #endif static __inline__ int irq_canonicalize(int irq) { /* * XXX is this true for all Alpha's? The old serial driver * did it this way for years without any complaints, so.... */ return ((irq == 2) ? 9 : irq); } struct pt_regs; extern void (*perf_irq)(unsigned long, struct pt_regs *); #endif /* _ALPHA_IRQ_H */ PK ! �؍� � pgalloc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_PGALLOC_H #define _ALPHA_PGALLOC_H #include <linux/mm.h> #include <linux/mmzone.h> #include <asm-generic/pgalloc.h> /* * Allocate and free page tables. The xxx_kernel() versions are * used to allocate a kernel page table - this turns on ASN bits * if any. */ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte) { pmd_set(pmd, (pte_t *)(page_to_pa(pte) + PAGE_OFFSET)); } static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) { pmd_set(pmd, pte); } static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) { pud_set(pud, pmd); } extern pgd_t *pgd_alloc(struct mm_struct *mm); #endif /* _ALPHA_PGALLOC_H */ PK ! ̍Lo� � spinlock_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ALPHA_SPINLOCK_TYPES_H #define _ALPHA_SPINLOCK_TYPES_H #ifndef __LINUX_SPINLOCK_TYPES_H # error "please don't include this file directly" #endif typedef struct { volatile unsigned int lock; } arch_spinlock_t; #define __ARCH_SPIN_LOCK_UNLOCKED { 0 } typedef struct { volatile unsigned int lock; } arch_rwlock_t; #define __ARCH_RW_LOCK_UNLOCKED { 0 } #endif PK ! %�V� � string.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_STRING_H__ #define __ALPHA_STRING_H__ #ifdef __KERNEL__ /* * GCC of any recent vintage doesn't do stupid things with bcopy. * EGCS 1.1 knows all about expanding memcpy inline, others don't. * * Similarly for a memset with data = 0. */ #define __HAVE_ARCH_MEMCPY extern void * memcpy(void *, const void *, size_t); #define __HAVE_ARCH_MEMMOVE extern void * memmove(void *, const void *, size_t); /* For backward compatibility with modules. Unused otherwise. */ extern void * __memcpy(void *, const void *, size_t); #define memcpy __builtin_memcpy #define __HAVE_ARCH_MEMSET extern void * __constant_c_memset(void *, unsigned long, size_t); extern void * ___memset(void *, int, size_t); extern void * __memset(void *, int, size_t); extern void * memset(void *, int, size_t); /* For gcc 3.x, we cannot have the inline function named "memset" because the __builtin_memset will attempt to resolve to the inline as well, leading to a "sorry" about unimplemented recursive inlining. */ extern inline void *__memset(void *s, int c, size_t n) { if (__builtin_constant_p(c)) { if (__builtin_constant_p(n)) { return __builtin_memset(s, c, n); } else { unsigned long c8 = (c & 0xff) * 0x0101010101010101UL; return __constant_c_memset(s, c8, n); } } return ___memset(s, c, n); } #define memset __memset #define __HAVE_ARCH_STRCPY extern char * strcpy(char *,const char *); #define __HAVE_ARCH_STRNCPY extern char * strncpy(char *, const char *, size_t); #define __HAVE_ARCH_STRCAT extern char * strcat(char *, const char *); #define __HAVE_ARCH_STRNCAT extern char * strncat(char *, const char *, size_t); #define __HAVE_ARCH_STRCHR extern char * strchr(const char *,int); #define __HAVE_ARCH_STRRCHR extern char * strrchr(const char *,int); #define __HAVE_ARCH_STRLEN extern size_t strlen(const char *); #define __HAVE_ARCH_MEMCHR extern void * memchr(const void *, int, size_t); /* The following routine is like memset except that it writes 16-bit aligned values. The DEST and COUNT parameters must be even for correct operation. */ #define __HAVE_ARCH_MEMSET16 extern void * __memset16(void *dest, unsigned short, size_t count); static inline void *memset16(uint16_t *p, uint16_t v, size_t n) { if (__builtin_constant_p(v)) return __constant_c_memset(p, 0x0001000100010001UL * v, n * 2); return __memset16(p, v, n * 2); } #endif /* __KERNEL__ */ #endif /* __ALPHA_STRING_H__ */ PK ! J\D� � device.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Arch specific extensions to struct device */ #include <asm-generic/device.h> PK ! K� +1 1 unistd.hnu �[��� PK ! t� -� � i setup.hnu �[��� PK ! � ��� � Y Kbuildnu �[��� PK ! �^r�] ] page.hnu �[��� PK ! 9u��s s � signal.hnu �[��� PK ! ���o� � Z ptrace.hnu �[��� PK ! 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