PK!ffcobalt.hnu[/* * The Cobalt board ID information. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1997 Cobalt Microserver * Copyright (C) 1997, 2003 Ralf Baechle * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv) */ #ifndef __ASM_COBALT_H #define __ASM_COBALT_H extern int cobalt_board_id; #define COBALT_BRD_ID_QUBE1 0x3 #define COBALT_BRD_ID_RAQ1 0x4 #define COBALT_BRD_ID_QUBE2 0x5 #define COBALT_BRD_ID_RAQ2 0x6 #endif /* __ASM_COBALT_H */ PK!zJJmach-gt64120.hnu[/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2006 Yoichi Yuasa */ #ifndef _COBALT_MACH_GT64120_H #define _COBALT_MACH_GT64120_H /* * Cobalt uses GT64111. GT64111 is almost the same as GT64120. */ #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE) #endif /* _COBALT_MACH_GT64120_H */ PK!uf=cpu-feature-overrides.hnu[/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H #define cpu_has_tlb 1 #define cpu_has_4kex 1 #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 #define cpu_has_tx39_cache 0 #define cpu_has_32fpr 1 #define cpu_has_counter 1 #define cpu_has_watch 0 #define cpu_has_divec 1 #define cpu_has_vce 0 #define cpu_has_cache_cdex_p 0 #define cpu_has_cache_cdex_s 0 #define cpu_has_prefetch 0 #define cpu_has_mcheck 0 #define cpu_has_ejtag 0 #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 0 #ifdef CONFIG_64BIT #define cpu_has_llsc 0 #else #define cpu_has_llsc 1 #endif #define cpu_has_mips16 0 #define cpu_has_mips16e2 0 #define cpu_has_mdmx 0 #define cpu_has_mips3d 0 #define cpu_has_smartmips 0 #define cpu_has_vtag_icache 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_dsp 0 #define cpu_has_dsp2 0 #define cpu_has_mipsmt 0 #define cpu_has_userlocal 0 #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 #define cpu_has_mips64r1 0 #define cpu_has_mips64r2 0 #endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */ PK!girq.hnu[/* * Cobalt IRQ definitions. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1997 Cobalt Microserver * Copyright (C) 1997, 2003 Ralf Baechle * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) * Copyright (C) 2007 Yoichi Yuasa */ #ifndef _ASM_COBALT_IRQ_H #define _ASM_COBALT_IRQ_H /* * i8259 interrupts used on Cobalt: * * 8 - RTC * 9 - PCI slot * 14 - IDE0 * 15 - IDE1(no connector on board) */ #define I8259A_IRQ_BASE 0 #define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) /* * CPU interrupts used on Cobalt: * * 0 - Software interrupt 0 (unused) * 1 - Software interrupt 0 (unused) * 2 - cascade GT64111 * 3 - ethernet or SCSI host controller * 4 - ethernet * 5 - 16550 UART * 6 - cascade i8259 * 7 - CP0 counter */ #define MIPS_CPU_IRQ_BASE 16 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) #define GT641XX_IRQ_BASE 24 #include #define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) #endif /* _ASM_COBALT_IRQ_H */ PK!ffcobalt.hnu[PK!zJJmach-gt64120.hnu[PK!uf=&cpu-feature-overrides.hnu[PK!g irq.hnu[PK2